ath10k: split up pci irq code
Hardware waits until host signals whether it has chosen MSI(-X) or shared legacy interrupts. It is not required for the driver to register interrupt handlers immediately. This patch prepares the pci irq code for more changes. Signed-off-by: Michal Kazior <michal.kazior@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
This commit is contained in:
Michal Kazior
Kalle Valo
parent
e539887b15
commit
fc15ca13a6
@ -55,8 +55,10 @@ static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pipe_info);
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static void ath10k_pci_stop_ce(struct ath10k *ar);
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static int ath10k_pci_device_reset(struct ath10k *ar);
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static int ath10k_pci_wait_for_target_init(struct ath10k *ar);
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static int ath10k_pci_start_intr(struct ath10k *ar);
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static void ath10k_pci_stop_intr(struct ath10k *ar);
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static int ath10k_pci_init_irq(struct ath10k *ar);
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static int ath10k_pci_deinit_irq(struct ath10k *ar);
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static int ath10k_pci_request_irq(struct ath10k *ar);
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static void ath10k_pci_free_irq(struct ath10k *ar);
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static const struct ce_attr host_ce_config_wlan[] = {
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/* CE0: host->target HTC control and raw streams */
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@ -1354,7 +1356,7 @@ static void ath10k_pci_hif_stop(struct ath10k *ar)
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ath10k_dbg(ATH10K_DBG_PCI, "%s\n", __func__);
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/* Irqs are never explicitly re-enabled. They are implicitly re-enabled
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* by ath10k_pci_start_intr(). */
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* by upon power_up. */
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ath10k_pci_disable_irqs(ar);
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ath10k_pci_stop_ce(ar);
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@ -1900,34 +1902,40 @@ static int ath10k_pci_hif_power_up(struct ath10k *ar)
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goto err_ce;
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}
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ret = ath10k_pci_start_intr(ar);
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ret = ath10k_pci_init_irq(ar);
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if (ret) {
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ath10k_err("failed to start interrupt handling: %d\n", ret);
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ath10k_err("failed to init irqs: %d\n", ret);
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goto err_ce;
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}
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ret = ath10k_pci_request_irq(ar);
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if (ret) {
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ath10k_err("failed to request irqs: %d\n", ret);
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goto err_deinit_irq;
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}
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ret = ath10k_pci_wait_for_target_init(ar);
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if (ret) {
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ath10k_err("failed to wait for target to init: %d\n", ret);
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goto err_irq;
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goto err_free_irq;
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}
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ret = ath10k_ce_enable_err_irq(ar);
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if (ret) {
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ath10k_err("failed to enable CE error irq: %d\n", ret);
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goto err_irq;
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goto err_free_irq;
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}
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ret = ath10k_pci_init_config(ar);
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if (ret) {
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ath10k_err("failed to setup init config: %d\n", ret);
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goto err_irq;
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goto err_free_irq;
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}
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ret = ath10k_pci_wake_target_cpu(ar);
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if (ret) {
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ath10k_err("could not wake up target CPU: %d\n", ret);
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goto err_irq;
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goto err_free_irq;
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}
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ath10k_pci_start_bmi(ar);
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@ -1944,11 +1952,12 @@ static int ath10k_pci_hif_power_up(struct ath10k *ar)
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return 0;
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err_irq:
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ath10k_ce_disable_interrupts(ar);
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ath10k_pci_stop_intr(ar);
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err_free_irq:
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ath10k_pci_free_irq(ar);
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ath10k_pci_kill_tasklet(ar);
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ath10k_pci_device_reset(ar);
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err_deinit_irq:
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ath10k_pci_deinit_irq(ar);
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err_ce:
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ath10k_pci_ce_deinit(ar);
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err_ps:
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@ -1962,7 +1971,8 @@ static void ath10k_pci_hif_power_down(struct ath10k *ar)
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{
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struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
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ath10k_pci_stop_intr(ar);
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ath10k_pci_free_irq(ar);
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ath10k_pci_deinit_irq(ar);
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ath10k_pci_device_reset(ar);
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ath10k_pci_ce_deinit(ar);
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@ -2152,24 +2162,17 @@ static void ath10k_pci_tasklet(unsigned long data)
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}
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}
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static int ath10k_pci_start_intr_msix(struct ath10k *ar, int num)
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static int ath10k_pci_request_irq_msix(struct ath10k *ar)
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{
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struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
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int ret;
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int i;
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ret = pci_enable_msi_block(ar_pci->pdev, num);
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if (ret)
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return ret;
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int ret, i;
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ret = request_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW,
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ath10k_pci_msi_fw_handler,
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IRQF_SHARED, "ath10k_pci", ar);
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if (ret) {
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ath10k_warn("request_irq(%d) failed %d\n",
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ath10k_warn("failed to request MSI-X fw irq %d: %d\n",
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ar_pci->pdev->irq + MSI_ASSIGN_FW, ret);
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pci_disable_msi(ar_pci->pdev);
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return ret;
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}
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@ -2178,45 +2181,21 @@ static int ath10k_pci_start_intr_msix(struct ath10k *ar, int num)
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ath10k_pci_per_engine_handler,
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IRQF_SHARED, "ath10k_pci", ar);
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if (ret) {
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ath10k_warn("request_irq(%d) failed %d\n",
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ath10k_warn("failed to request MSI-X ce irq %d: %d\n",
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ar_pci->pdev->irq + i, ret);
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for (i--; i >= MSI_ASSIGN_CE_INITIAL; i--)
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free_irq(ar_pci->pdev->irq + i, ar);
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free_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW, ar);
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pci_disable_msi(ar_pci->pdev);
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return ret;
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}
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}
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ath10k_dbg(ATH10K_DBG_BOOT,
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"MSI-X interrupt handling (%d intrs)\n", num);
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return 0;
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}
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static int ath10k_pci_start_intr_msi(struct ath10k *ar)
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{
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struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
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int ret;
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ret = pci_enable_msi(ar_pci->pdev);
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if (ret < 0)
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return ret;
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ret = request_irq(ar_pci->pdev->irq,
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ath10k_pci_interrupt_handler,
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IRQF_SHARED, "ath10k_pci", ar);
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if (ret < 0) {
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pci_disable_msi(ar_pci->pdev);
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return ret;
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}
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ath10k_dbg(ATH10K_DBG_BOOT, "MSI interrupt handling\n");
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return 0;
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}
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static int ath10k_pci_start_intr_legacy(struct ath10k *ar)
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static int ath10k_pci_request_irq_msi(struct ath10k *ar)
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{
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struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
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int ret;
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@ -2224,88 +2203,50 @@ static int ath10k_pci_start_intr_legacy(struct ath10k *ar)
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ret = request_irq(ar_pci->pdev->irq,
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ath10k_pci_interrupt_handler,
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IRQF_SHARED, "ath10k_pci", ar);
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if (ret < 0)
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return ret;
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ret = ath10k_pci_wake(ar);
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if (ret) {
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free_irq(ar_pci->pdev->irq, ar);
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ath10k_err("failed to wake up target: %d\n", ret);
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ath10k_warn("failed to request MSI irq %d: %d\n",
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ar_pci->pdev->irq, ret);
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return ret;
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}
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/*
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* A potential race occurs here: The CORE_BASE write
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* depends on target correctly decoding AXI address but
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* host won't know when target writes BAR to CORE_CTRL.
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* This write might get lost if target has NOT written BAR.
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* For now, fix the race by repeating the write in below
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* synchronization checking.
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*/
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iowrite32(PCIE_INTR_FIRMWARE_MASK |
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PCIE_INTR_CE_MASK_ALL,
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ar_pci->mem + (SOC_CORE_BASE_ADDRESS |
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PCIE_INTR_ENABLE_ADDRESS));
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ath10k_pci_sleep(ar);
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ath10k_dbg(ATH10K_DBG_BOOT, "legacy interrupt handling\n");
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return 0;
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}
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static int ath10k_pci_start_intr(struct ath10k *ar)
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static int ath10k_pci_request_irq_legacy(struct ath10k *ar)
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{
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struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
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int num = MSI_NUM_REQUEST;
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int ret;
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int i;
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tasklet_init(&ar_pci->intr_tq, ath10k_pci_tasklet, (unsigned long) ar);
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tasklet_init(&ar_pci->msi_fw_err, ath10k_msi_err_tasklet,
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(unsigned long) ar);
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for (i = 0; i < CE_COUNT; i++) {
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ar_pci->pipe_info[i].ar_pci = ar_pci;
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tasklet_init(&ar_pci->pipe_info[i].intr,
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ath10k_pci_ce_tasklet,
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(unsigned long)&ar_pci->pipe_info[i]);
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}
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if (!test_bit(ATH10K_PCI_FEATURE_MSI_X, ar_pci->features))
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num = 1;
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if (num > 1) {
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ret = ath10k_pci_start_intr_msix(ar, num);
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if (ret == 0)
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goto exit;
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ath10k_dbg(ATH10K_DBG_BOOT,
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"MSI-X didn't succeed (%d), trying MSI\n", ret);
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num = 1;
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}
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if (num == 1) {
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ret = ath10k_pci_start_intr_msi(ar);
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if (ret == 0)
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goto exit;
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ath10k_dbg(ATH10K_DBG_BOOT,
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"MSI didn't succeed (%d), trying legacy INTR\n",
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ret);
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num = 0;
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}
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ret = ath10k_pci_start_intr_legacy(ar);
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ret = request_irq(ar_pci->pdev->irq,
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ath10k_pci_interrupt_handler,
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IRQF_SHARED, "ath10k_pci", ar);
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if (ret) {
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ath10k_warn("Failed to start legacy interrupts: %d\n", ret);
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ath10k_warn("failed to request legacy irq %d: %d\n",
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ar_pci->pdev->irq, ret);
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return ret;
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}
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exit:
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ar_pci->num_msi_intrs = num;
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return ret;
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return 0;
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}
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static void ath10k_pci_stop_intr(struct ath10k *ar)
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static int ath10k_pci_request_irq(struct ath10k *ar)
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{
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struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
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switch (ar_pci->num_msi_intrs) {
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case 0:
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return ath10k_pci_request_irq_legacy(ar);
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case 1:
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return ath10k_pci_request_irq_msi(ar);
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case MSI_NUM_REQUEST:
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return ath10k_pci_request_irq_msix(ar);
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}
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ath10k_warn("unknown irq configuration upon request\n");
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return -EINVAL;
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}
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static void ath10k_pci_free_irq(struct ath10k *ar)
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{
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struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
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int i;
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@ -2314,9 +2255,105 @@ static void ath10k_pci_stop_intr(struct ath10k *ar)
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* or MSI or MSI-X */
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for (i = 0; i < max(1, ar_pci->num_msi_intrs); i++)
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free_irq(ar_pci->pdev->irq + i, ar);
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}
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if (ar_pci->num_msi_intrs > 0)
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static void ath10k_pci_init_irq_tasklets(struct ath10k *ar)
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{
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struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
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int i;
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tasklet_init(&ar_pci->intr_tq, ath10k_pci_tasklet, (unsigned long)ar);
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tasklet_init(&ar_pci->msi_fw_err, ath10k_msi_err_tasklet,
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(unsigned long)ar);
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for (i = 0; i < CE_COUNT; i++) {
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ar_pci->pipe_info[i].ar_pci = ar_pci;
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tasklet_init(&ar_pci->pipe_info[i].intr, ath10k_pci_ce_tasklet,
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(unsigned long)&ar_pci->pipe_info[i]);
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}
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}
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static int ath10k_pci_init_irq(struct ath10k *ar)
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{
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struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
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int ret;
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ath10k_pci_init_irq_tasklets(ar);
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if (!test_bit(ATH10K_PCI_FEATURE_MSI_X, ar_pci->features))
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goto msi;
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/* Try MSI-X */
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ar_pci->num_msi_intrs = MSI_NUM_REQUEST;
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ret = pci_enable_msi_block(ar_pci->pdev, ar_pci->num_msi_intrs);
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if (ret == 0)
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return 0;
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if (ret > 0)
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pci_disable_msi(ar_pci->pdev);
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msi:
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/* Try MSI */
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ar_pci->num_msi_intrs = 1;
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ret = pci_enable_msi(ar_pci->pdev);
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if (ret == 0)
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return 0;
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/* Try legacy irq
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*
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* A potential race occurs here: The CORE_BASE write
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* depends on target correctly decoding AXI address but
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* host won't know when target writes BAR to CORE_CTRL.
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* This write might get lost if target has NOT written BAR.
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* For now, fix the race by repeating the write in below
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* synchronization checking. */
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ar_pci->num_msi_intrs = 0;
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ret = ath10k_pci_wake(ar);
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if (ret) {
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ath10k_warn("failed to wake target: %d\n", ret);
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return ret;
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}
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ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
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PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
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ath10k_pci_sleep(ar);
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return 0;
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}
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static int ath10k_pci_deinit_irq_legacy(struct ath10k *ar)
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{
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int ret;
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ret = ath10k_pci_wake(ar);
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if (ret) {
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ath10k_warn("failed to wake target: %d\n", ret);
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return ret;
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}
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ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
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0);
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ath10k_pci_sleep(ar);
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return 0;
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}
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static int ath10k_pci_deinit_irq(struct ath10k *ar)
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{
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struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
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switch (ar_pci->num_msi_intrs) {
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case 0:
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return ath10k_pci_deinit_irq_legacy(ar);
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case 1:
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/* fall-through */
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case MSI_NUM_REQUEST:
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pci_disable_msi(ar_pci->pdev);
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return 0;
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}
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ath10k_warn("unknown irq configuration upon deinit\n");
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return -EINVAL;
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}
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static int ath10k_pci_wait_for_target_init(struct ath10k *ar)
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