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ASoC: fsl_micfil: use define for OSR default value

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The OSR (OverSampling Rate) setting is set once to the default value
and never changed throughout the driver. Nevertheless the value is
read back from the register for further calculations. Just use the
default value because we know what we have written.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shengjiu Wang <shengjiu.wang@gmail.com>
Link: https://lore.kernel.org/r/20220414162249.3934543-14-s.hauer@pengutronix.de
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Sascha Hauer 2022-04-14 18:22:41 +02:00 committed by Mark Brown
parent 2495ba26e8
commit fb855b8d46
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
2 changed files with 5 additions and 5 deletions
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9
sound/soc/fsl/fsl_micfil.c
View File

@ -29,6 +29,8 @@
#define FSL_MICFIL_RATES SNDRV_PCM_RATE_8000_48000
#define FSL_MICFIL_FORMATS (SNDRV_PCM_FMTBIT_S16_LE)
#define MICFIL_OSR_DEFAULT 16
struct fsl_micfil {
struct platform_device *pdev;
struct regmap *regmap;
@ -112,11 +114,11 @@ static inline int get_pdm_clk(struct fsl_micfil *micfil,
unsigned int rate)
{
u32 ctrl2_reg;
int qsel, osr;
int qsel;
int bclk;
int osr = MICFIL_OSR_DEFAULT;
regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
osr = 16 - FIELD_GET(MICFIL_CTRL2_CICOSR, ctrl2_reg);
qsel = FIELD_GET(MICFIL_CTRL2_QSEL, ctrl2_reg);
switch (qsel) {
@ -282,7 +284,7 @@ static int fsl_set_clock_params(struct device *dev, unsigned int rate)
/* set CICOSR */
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
MICFIL_CTRL2_CICOSR,
FIELD_PREP(MICFIL_CTRL2_CICOSR, MICFIL_CTRL2_CICOSR_DEFAULT));
FIELD_PREP(MICFIL_CTRL2_CICOSR, 16 - MICFIL_OSR_DEFAULT));
if (ret)
return ret;
@ -673,7 +675,6 @@ static int fsl_micfil_probe(struct platform_device *pdev)
micfil->dma_params_rx.addr = res->start + REG_MICFIL_DATACH0;
micfil->dma_params_rx.maxburst = MICFIL_DMA_MAXBURST_RX;
platform_set_drvdata(pdev, micfil);
pm_runtime_enable(&pdev->dev);

1
sound/soc/fsl/fsl_micfil.h
View File

@ -58,7 +58,6 @@
#define MICFIL_QSEL_VLOW2_QUALITY 4
#define MICFIL_CTRL2_CICOSR GENMASK(19, 16)
#define MICFIL_CTRL2_CICOSR_DEFAULT 0
#define MICFIL_CTRL2_CLKDIV GENMASK(7, 0)
/* MICFIL Status Register -- REG_MICFIL_STAT 0x08 */