Merge tag 'drm-next-2020-06-02' of git://anongit.freedesktop.org/drm/drm
Pull drm updates from Dave Airlie:
"Highlights:
- Core DRM had a lot of refactoring around managed drm resources to
make drivers simpler.
- Intel Tigerlake support is on by default
- amdgpu now support p2p PCI buffer sharing and encrypted GPU memory
Details:
core:
- uapi: error out EBUSY when existing master
- uapi: rework SET/DROP MASTER permission handling
- remove drm_pci.h
- drm_pci* are now legacy
- introduced managed DRM resources
- subclassing support for drm_framebuffer
- simple encoder helper
- edid improvements
- vblank + writeback documentation improved
- drm/mm - optimise tree searches
- port drivers to use devm_drm_dev_alloc
dma-buf:
- add flag for p2p buffer support
mst:
- ACT timeout improvements
- remove drm_dp_mst_has_audio
- don't use 2nd TX slot - spec recommends against it
bridge:
- dw-hdmi various improvements
- chrontel ch7033 support
- fix stack issues with old gcc
hdmi:
- add unpack function for drm infoframe
fbdev:
- misc fbdev driver fixes
i915:
- uapi: global sseu pinning
- uapi: OA buffer polling
- uapi: remove generated perf code
- uapi: per-engine default property values in sysfs
- Tigerlake GEN12 enabled.
- Lots of gem refactoring
- Tigerlake enablement patches
- move to drm_device logging
- Icelake gamma HW readout
- push MST link retrain to hotplug work
- bandwidth atomic helpers
- ICL fixes
- RPS/GT refactoring
- Cherryview full-ppgtt support
- i915 locking guidelines documented
- require linear fb stride to be 512 multiple on gen9
- Tigerlake SAGV support
amdgpu:
- uapi: encrypted GPU memory handling
- uapi: add MEM_SYNC IB flag
- p2p dma-buf support
- export VRAM dma-bufs
- FRU chip access support
- RAS/SR-IOV updates
- Powerplay locking fixes
- VCN DPG (powergating) enablement
- GFX10 clockgating fixes
- DC fixes
- GPU reset fixes
- navi SDMA fix
- expose FP16 for modesetting
- DP 1.4 compliance fixes
- gfx10 soft recovery
- Improved Critical Thermal Faults handling
- resizable BAR on gmc10
amdkfd:
- uapi: GWS resource management
- track GPU memory per process
- report PCI domain in topology
radeon:
- safe reg list generator fixes
nouveau:
- HD audio fixes on recent systems
- vGPU detection (fail probe if we're on one, for now)
- Interlaced mode fixes (mostly avoidance on Turing, which doesn't support it)
- SVM improvements/fixes
- NVIDIA format modifier support
- Misc other fixes.
adv7511:
- HDMI SPDIF support
ast:
- allocate crtc state size
- fix double assignment
- fix suspend
bochs:
- drop connector register
cirrus:
- move to tiny drivers.
exynos:
- fix imported dma-buf mapping
- enable runtime PM
- fixes and cleanups
mediatek:
- DPI pin mode swap
- config mipi_tx current/impedance
lima:
- devfreq + cooling device support
- task handling improvements
- runtime PM support
pl111:
- vexpress init improvements
- fix module auto-load
rcar-du:
- DT bindings conversion to YAML
- Planes zpos sanity check and fix
- MAINTAINERS entry for LVDS panel driver
mcde:
- fix return value
mgag200:
- use managed config init
stm:
- read endpoints from DT
vboxvideo:
- use PCI managed functions
- drop WC mtrr
vkms:
- enable cursor by default
rockchip:
- afbc support
virtio:
- various cleanups
qxl:
- fix cursor notify port
hisilicon:
- 128-byte stride alignment fix
sun4i:
- improved format handling"
* tag 'drm-next-2020-06-02' of git://anongit.freedesktop.org/drm/drm: (1401 commits)
drm/amd/display: Fix potential integer wraparound resulting in a hang
drm/amd/display: drop cursor position check in atomic test
drm/amdgpu: fix device attribute node create failed with multi gpu
drm/nouveau: use correct conflicting framebuffer API
drm/vblank: Fix -Wformat compile warnings on some arches
drm/amdgpu: Sync with VM root BO when switching VM to CPU update mode
drm/amd/display: Handle GPU reset for DC block
drm/amdgpu: add apu flags (v2)
drm/amd/powerpay: Disable gfxoff when setting manual mode on picasso and raven
drm/amdgpu: fix pm sysfs node handling (v2)
drm/amdgpu: move gpu_info parsing after common early init
drm/amdgpu: move discovery gfx config fetching
drm/nouveau/dispnv50: fix runtime pm imbalance on error
drm/nouveau: fix runtime pm imbalance on error
drm/nouveau: fix runtime pm imbalance on error
drm/nouveau/debugfs: fix runtime pm imbalance on error
drm/nouveau/nouveau/hmm: fix migrate zero page to GPU
drm/nouveau/nouveau/hmm: fix nouveau_dmem_chunk allocations
drm/nouveau/kms/nv50-: Share DP SST mode_valid() handling with MST
drm/nouveau/kms/nv50-: Move 8BPC limit for MST into nv50_mstc_get_modes()
...
This commit is contained in:
Linus Torvalds
@@ -133,6 +133,11 @@ extern "C" {
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* releasing the memory
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*/
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#define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9)
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/* Flag that BO will be encrypted and that the TMZ bit should be
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* set in the PTEs when mapping this buffer via GPUVM or
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* accessing it with various hw blocks
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*/
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#define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10)
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struct drm_amdgpu_gem_create_in {
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/** the requested memory size */
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@@ -559,7 +564,7 @@ struct drm_amdgpu_cs_in {
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/** Handle of resource list associated with CS */
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__u32 bo_list_handle;
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__u32 num_chunks;
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__u32 _pad;
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__u32 flags;
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/** this points to __u64 * which point to cs chunks */
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__u64 chunks;
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};
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@@ -593,6 +598,14 @@ union drm_amdgpu_cs {
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*/
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#define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4)
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/* Flag the IB as secure (TMZ)
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*/
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#define AMDGPU_IB_FLAGS_SECURE (1 << 5)
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/* Tell KMD to flush and invalidate caches
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*/
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#define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6)
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struct drm_amdgpu_cs_chunk_ib {
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__u32 _pad;
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/** AMDGPU_IB_FLAG_* */
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@@ -354,9 +354,12 @@ extern "C" {
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* a platform-dependent stride. On top of that the memory can apply
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* platform-depending swizzling of some higher address bits into bit6.
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*
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* This format is highly platforms specific and not useful for cross-driver
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* sharing. It exists since on a given platform it does uniquely identify the
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* layout in a simple way for i915-specific userspace.
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* Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
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* On earlier platforms the is highly platforms specific and not useful for
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* cross-driver sharing. It exists since on a given platform it does uniquely
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* identify the layout in a simple way for i915-specific userspace, which
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* facilitated conversion of userspace to modifiers. Additionally the exact
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* format on some really old platforms is not known.
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*/
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#define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)
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@@ -369,9 +372,12 @@ extern "C" {
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* memory can apply platform-depending swizzling of some higher address bits
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* into bit6.
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*
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* This format is highly platforms specific and not useful for cross-driver
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* sharing. It exists since on a given platform it does uniquely identify the
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* layout in a simple way for i915-specific userspace.
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* Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
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* On earlier platforms the is highly platforms specific and not useful for
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* cross-driver sharing. It exists since on a given platform it does uniquely
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* identify the layout in a simple way for i915-specific userspace, which
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* facilitated conversion of userspace to modifiers. Additionally the exact
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* format on some really old platforms is not known.
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*/
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#define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2)
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@@ -521,7 +527,113 @@ extern "C" {
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#define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)
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/*
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* 16Bx2 Block Linear layout, used by desktop GPUs, and Tegra K1 and later
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* Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80,
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* and Tegra GPUs starting with Tegra K1.
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*
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* Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies
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* based on the architecture generation. GOBs themselves are then arranged in
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* 3D blocks, with the block dimensions (in terms of GOBs) always being a power
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* of two, and hence expressible as their log2 equivalent (E.g., "2" represents
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* a block depth or height of "4").
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*
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* Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
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* in full detail.
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*
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* Macro
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* Bits Param Description
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* ---- ----- -----------------------------------------------------------------
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*
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* 3:0 h log2(height) of each block, in GOBs. Placed here for
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* compatibility with the existing
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* DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
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*
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* 4:4 - Must be 1, to indicate block-linear layout. Necessary for
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* compatibility with the existing
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* DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
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*
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* 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block
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* size). Must be zero.
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*
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* Note there is no log2(width) parameter. Some portions of the
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* hardware support a block width of two gobs, but it is impractical
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* to use due to lack of support elsewhere, and has no known
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* benefits.
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*
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* 11:9 - Reserved (To support 2D-array textures with variable array stride
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* in blocks, specified via log2(tile width in blocks)). Must be
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* zero.
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*
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* 19:12 k Page Kind. This value directly maps to a field in the page
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* tables of all GPUs >= NV50. It affects the exact layout of bits
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* in memory and can be derived from the tuple
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*
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* (format, GPU model, compression type, samples per pixel)
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*
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* Where compression type is defined below. If GPU model were
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* implied by the format modifier, format, or memory buffer, page
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* kind would not need to be included in the modifier itself, but
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* since the modifier should define the layout of the associated
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* memory buffer independent from any device or other context, it
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* must be included here.
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*
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* 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed
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* starting with Fermi GPUs. Additionally, the mapping between page
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* kind and bit layout has changed at various points.
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*
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* 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping
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* 1 = Gob Height 4, G80 - GT2XX Page Kind mapping
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* 2 = Gob Height 8, Turing+ Page Kind mapping
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* 3 = Reserved for future use.
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*
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* 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further
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* bit remapping step that occurs at an even lower level than the
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* page kind and block linear swizzles. This causes the layout of
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* surfaces mapped in those SOC's GPUs to be incompatible with the
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* equivalent mapping on other GPUs in the same system.
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*
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* 0 = Tegra K1 - Tegra Parker/TX2 Layout.
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* 1 = Desktop GPU and Tegra Xavier+ Layout
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*
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* 25:23 c Lossless Framebuffer Compression type.
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*
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* 0 = none
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* 1 = ROP/3D, layout 1, exact compression format implied by Page
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* Kind field
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* 2 = ROP/3D, layout 2, exact compression format implied by Page
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* Kind field
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* 3 = CDE horizontal
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* 4 = CDE vertical
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* 5 = Reserved for future use
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* 6 = Reserved for future use
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* 7 = Reserved for future use
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*
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* 55:25 - Reserved for future use. Must be zero.
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*/
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#define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \
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fourcc_mod_code(NVIDIA, (0x10 | \
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((h) & 0xf) | \
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(((k) & 0xff) << 12) | \
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(((g) & 0x3) << 20) | \
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(((s) & 0x1) << 22) | \
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(((c) & 0x7) << 23)))
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/* To grandfather in prior block linear format modifiers to the above layout,
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* the page kind "0", which corresponds to "pitch/linear" and hence is unusable
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* with block-linear layouts, is remapped within drivers to the value 0xfe,
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* which corresponds to the "generic" kind used for simple single-sample
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* uncompressed color formats on Fermi - Volta GPUs.
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*/
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static inline __u64
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drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
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{
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if (!(modifier & 0x10) || (modifier & (0xff << 12)))
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return modifier;
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else
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return modifier | (0xfe << 12);
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}
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/*
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* 16Bx2 Block Linear layout, used by Tegra K1 and later
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*
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* Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
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* vertically by a power of 2 (1 to 32 GOBs) to form a block.
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@@ -542,20 +654,20 @@ extern "C" {
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* in full detail.
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*/
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#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \
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fourcc_mod_code(NVIDIA, 0x10 | ((v) & 0xf))
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DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v))
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#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \
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fourcc_mod_code(NVIDIA, 0x10)
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DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0)
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#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \
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fourcc_mod_code(NVIDIA, 0x11)
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DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1)
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#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \
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fourcc_mod_code(NVIDIA, 0x12)
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DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2)
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#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \
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fourcc_mod_code(NVIDIA, 0x13)
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DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3)
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#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \
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fourcc_mod_code(NVIDIA, 0x14)
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DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4)
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#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \
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fourcc_mod_code(NVIDIA, 0x15)
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DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5)
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/*
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* Some Broadcom modifiers take parameters, for example the number of
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@@ -1969,6 +1969,30 @@ enum drm_i915_perf_property_id {
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*/
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DRM_I915_PERF_PROP_HOLD_PREEMPTION,
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/**
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* Specifying this pins all contexts to the specified SSEU power
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* configuration for the duration of the recording.
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*
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* This parameter's value is a pointer to a struct
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* drm_i915_gem_context_param_sseu.
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*
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* This property is available in perf revision 4.
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*/
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DRM_I915_PERF_PROP_GLOBAL_SSEU,
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/**
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* This optional parameter specifies the timer interval in nanoseconds
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* at which the i915 driver will check the OA buffer for available data.
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* Minimum allowed value is 100 microseconds. A default value is used by
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* the driver if this parameter is not specified. Note that larger timer
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* values will reduce cpu consumption during OA perf captures. However,
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* excessively large values would potentially result in OA buffer
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* overwrites as captures reach end of the OA buffer.
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*
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* This property is available in perf revision 5.
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*/
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DRM_I915_PERF_PROP_POLL_OA_PERIOD,
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DRM_I915_PERF_PROP_MAX /* non-ABI */
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};
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@@ -251,7 +251,7 @@ struct kfd_memory_exception_failure {
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__u32 imprecise; /* Can't determine the exact fault address */
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};
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/* memory exception data*/
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/* memory exception data */
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struct kfd_hsa_memory_exception_data {
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struct kfd_memory_exception_failure failure;
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__u64 va;
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@@ -410,6 +410,20 @@ struct kfd_ioctl_unmap_memory_from_gpu_args {
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__u32 n_success; /* to/from KFD */
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};
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/* Allocate GWS for specific queue
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*
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* @queue_id: queue's id that GWS is allocated for
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* @num_gws: how many GWS to allocate
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* @first_gws: index of the first GWS allocated.
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* only support contiguous GWS allocation
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*/
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struct kfd_ioctl_alloc_queue_gws_args {
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__u32 queue_id; /* to KFD */
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__u32 num_gws; /* to KFD */
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__u32 first_gws; /* from KFD */
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__u32 pad;
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};
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struct kfd_ioctl_get_dmabuf_info_args {
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__u64 size; /* from KFD */
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__u64 metadata_ptr; /* to KFD */
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@@ -529,7 +543,10 @@ enum kfd_mmio_remap {
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#define AMDKFD_IOC_IMPORT_DMABUF \
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AMDKFD_IOWR(0x1D, struct kfd_ioctl_import_dmabuf_args)
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#define AMDKFD_IOC_ALLOC_QUEUE_GWS \
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AMDKFD_IOWR(0x1E, struct kfd_ioctl_alloc_queue_gws_args)
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#define AMDKFD_COMMAND_START 0x01
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#define AMDKFD_COMMAND_END 0x1E
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#define AMDKFD_COMMAND_END 0x1F
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#endif
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Reference in New Issue
Block a user