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ASoC: AMD: Send correct channel for configuring DMA descriptors

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Earlier, ch1 was used to define ACP-SYSMEM transfer and ch2 for
ACP-I2S transfer. With recent patches ch1 is used to define channel
order number 1 and ch2 as channel order number 2. Thus,
Playback:
ch1:SYSMEM->ACP
ch2:ACP->I2S
Capture:
ch1:I2S->ACP
ch1:ACP->SYSMEM

Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Agrawal, Akshu 2018-07-16 15:02:40 +08:00 committed by Mark Brown
parent 8452112baa
commit fa9d2f17c2
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
1 changed files with 22 additions and 4 deletions
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26
sound/soc/amd/acp-pcm-dma.c
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@ -322,17 +322,27 @@ static void config_acp_dma(void __iomem *acp_mmio,
struct audio_substream_data *rtd,
u32 asic_type)
{
u16 ch_acp_sysmem, ch_acp_i2s;
acp_pte_config(acp_mmio, rtd->pg, rtd->num_of_pages,
rtd->pte_offset);
if (rtd->direction == SNDRV_PCM_STREAM_PLAYBACK) {
ch_acp_sysmem = rtd->ch1;
ch_acp_i2s = rtd->ch2;
} else {
ch_acp_i2s = rtd->ch1;
ch_acp_sysmem = rtd->ch2;
}
/* Configure System memory <-> ACP SRAM DMA descriptors */
set_acp_sysmem_dma_descriptors(acp_mmio, rtd->size,
rtd->direction, rtd->pte_offset,
rtd->ch1, rtd->sram_bank,
ch_acp_sysmem, rtd->sram_bank,
rtd->dma_dscr_idx_1, asic_type);
/* Configure ACP SRAM <-> I2S DMA descriptors */
set_acp_to_i2s_dma_descriptors(acp_mmio, rtd->size,
rtd->direction, rtd->sram_bank,
rtd->destination, rtd->ch2,
rtd->destination, ch_acp_i2s,
rtd->dma_dscr_idx_2, asic_type);
}
@ -995,16 +1005,24 @@ static int acp_dma_prepare(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct audio_substream_data *rtd = runtime->private_data;
u16 ch_acp_sysmem, ch_acp_i2s;
if (!rtd)
return -EINVAL;
if (rtd->direction == SNDRV_PCM_STREAM_PLAYBACK) {
ch_acp_sysmem = rtd->ch1;
ch_acp_i2s = rtd->ch2;
} else {
ch_acp_i2s = rtd->ch1;
ch_acp_sysmem = rtd->ch2;
}
config_acp_dma_channel(rtd->acp_mmio,
rtd->ch1,
ch_acp_sysmem,
rtd->dma_dscr_idx_1,
NUM_DSCRS_PER_CHANNEL, 0);
config_acp_dma_channel(rtd->acp_mmio,
rtd->ch2,
ch_acp_i2s,
rtd->dma_dscr_idx_2,
NUM_DSCRS_PER_CHANNEL, 0);
return 0;