leandrof/linux
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

ARM: 9058/1: cache-v7: refactor v7_invalidate_l1 to avoid clobbering r5/r6

Browse Source 
The cache invalidation code in v7_invalidate_l1 can be tweaked to
re-read the associativity from CCSIDR, and keep the way identifier
component in a single register that is assigned in the outer loop. This
way, we need 2 registers less.

Given that the number of sets is typically much larger than the
associativity, rearrange the code so that the outer loop has the fewer
number of iterations, ensuring that the re-read of CCSIDR only occurs a
handful of times in practice.

Fix the whitespace while at it, and update the comment to indicate that
this code is no longer a clone of anything else.

Acked-by: Nicolas Pitre <nico@fluxnic.net>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
This commit is contained in:
Ard Biesheuvel
2021-02-11 09:23:09 +01:00
committed by Russell King
parent c0e50736e8
commit f9e7a99fb6
1 changed files with 25 additions and 26 deletions
Download Patch File Download Diff File Expand all files Collapse all files

51
arch/arm/mm/cache-v7.S
View File

@@ -33,9 +33,8 @@ icache_size:
* processor. We fix this by performing an invalidate, rather than a * processor. We fix this by performing an invalidate, rather than a
* clean + invalidate, before jumping into the kernel. * clean + invalidate, before jumping into the kernel.
* *
* This function is cloned from arch/arm/mach-tegra/headsmp.S, and needs * This function needs to be called for both secondary cores startup and
* to be called for both secondary cores startup and primary core resume * primary core resume procedures.
* procedures.
*/ */
ENTRY(v7_invalidate_l1) ENTRY(v7_invalidate_l1)
mov r0, #0 mov r0, #0
@@ -43,30 +42,30 @@ ENTRY(v7_invalidate_l1)
isb isb
mrc p15, 1, r0, c0, c0, 0 @ read cache geometry from CCSIDR mrc p15, 1, r0, c0, c0, 0 @ read cache geometry from CCSIDR
movw r1, #0x7fff movw r3, #0x3ff
and r2, r1, r0, lsr #13 and r3, r3, r0, lsr #3 @ 'Associativity' in CCSIDR[12:3]
movw r1, #0x3ff
and r3, r1, r0, lsr #3 @ NumWays - 1
add r2, r2, #1 @ NumSets
and r0, r0, #0x7
add r0, r0, #4 @ SetShift
clz r1, r3 @ WayShift clz r1, r3 @ WayShift
add r4, r3, #1 @ NumWays mov r2, #1
1: sub r2, r2, #1 @ NumSets-- mov r3, r3, lsl r1 @ NumWays-1 shifted into bits [31:...]
mov r3, r4 @ Temp = NumWays movs r1, r2, lsl r1 @ #1 shifted left by same amount
2: subs r3, r3, #1 @ Temp-- moveq r1, #1 @ r1 needs value > 0 even if only 1 way
mov r5, r3, lsl r1
mov r6, r2, lsl r0 and r2, r0, #0x7
orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift) add r2, r2, #4 @ SetShift
mcr p15, 0, r5, c7, c6, 2
bgt 2b 1: movw r4, #0x7fff
cmp r2, #0 and r0, r4, r0, lsr #13 @ 'NumSets' in CCSIDR[27:13]
bgt 1b
dsb st 2: mov r4, r0, lsl r2 @ NumSet << SetShift
orr r4, r4, r3 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
mcr p15, 0, r4, c7, c6, 2
subs r0, r0, #1 @ Set--
bpl 2b
subs r3, r3, r1 @ Way--
bcc 3f
mrc p15, 1, r0, c0, c0, 0 @ re-read cache geometry from CCSIDR
b 1b
3: dsb st
isb isb
ret lr ret lr
ENDPROC(v7_invalidate_l1) ENDPROC(v7_invalidate_l1)