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arm64: dts: ls1088a: use constants in the clockgen phandle

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Now that we have constants, use them. This is just a mechanical change.

Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Michael Walle 2020-12-29 12:47:38 +01:00 committed by Shawn Guo
parent 973fb5e174
commit f9799323bd
1 changed files with 64 additions and 27 deletions
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91
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
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@ -7,6 +7,7 @@
* Harninder Rai <harninder.rai@nxp.com>
*
*/
#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
@ -30,7 +31,7 @@
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
clocks = <&clockgen 1 0>;
clocks = <&clockgen QORIQ_CLK_CMUX 0>;
cpu-idle-states = <&CPU_PH20>;
#cooling-cells = <2>;
};
@ -39,7 +40,7 @@
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
clocks = <&clockgen 1 0>;
clocks = <&clockgen QORIQ_CLK_CMUX 0>;
cpu-idle-states = <&CPU_PH20>;
#cooling-cells = <2>;
};
@ -48,7 +49,7 @@
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x2>;
clocks = <&clockgen 1 0>;
clocks = <&clockgen QORIQ_CLK_CMUX 0>;
cpu-idle-states = <&CPU_PH20>;
#cooling-cells = <2>;
};
@ -57,7 +58,7 @@
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x3>;
clocks = <&clockgen 1 0>;
clocks = <&clockgen QORIQ_CLK_CMUX 0>;
cpu-idle-states = <&CPU_PH20>;
#cooling-cells = <2>;
};
@ -66,7 +67,7 @@
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x100>;
clocks = <&clockgen 1 1>;
clocks = <&clockgen QORIQ_CLK_CMUX 1>;
cpu-idle-states = <&CPU_PH20>;
#cooling-cells = <2>;
};
@ -75,7 +76,7 @@
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x101>;
clocks = <&clockgen 1 1>;
clocks = <&clockgen QORIQ_CLK_CMUX 1>;
cpu-idle-states = <&CPU_PH20>;
#cooling-cells = <2>;
};
@ -84,7 +85,7 @@
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x102>;
clocks = <&clockgen 1 1>;
clocks = <&clockgen QORIQ_CLK_CMUX 1>;
cpu-idle-states = <&CPU_PH20>;
#cooling-cells = <2>;
};
@ -93,7 +94,7 @@
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x103>;
clocks = <&clockgen 1 1>;
clocks = <&clockgen QORIQ_CLK_CMUX 1>;
cpu-idle-states = <&CPU_PH20>;
#cooling-cells = <2>;
};
@ -310,7 +311,8 @@
reg = <0x0 0x2100000 0x0 0x10000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dspi";
clocks = <&clockgen 4 1>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
spi-num-chipselects = <6>;
status = "disabled";
};
@ -318,7 +320,8 @@
duart0: serial@21c0500 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21c0500 0x0 0x100>;
clocks = <&clockgen 4 3>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>;
interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@ -326,7 +329,8 @@
duart1: serial@21c0600 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21c0600 0x0 0x100>;
clocks = <&clockgen 4 3>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>;
interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@ -391,7 +395,8 @@
#size-cells = <0>;
reg = <0x0 0x2000000 0x0 0x10000>;
interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 7>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(8)>;
status = "disabled";
};
@ -401,7 +406,8 @@
#size-cells = <0>;
reg = <0x0 0x2010000 0x0 0x10000>;
interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 7>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(8)>;
status = "disabled";
};
@ -411,7 +417,8 @@
#size-cells = <0>;
reg = <0x0 0x2020000 0x0 0x10000>;
interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 7>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(8)>;
status = "disabled";
};
@ -421,7 +428,8 @@
#size-cells = <0>;
reg = <0x0 0x2030000 0x0 0x10000>;
interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 7>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(8)>;
status = "disabled";
};
@ -434,7 +442,10 @@
reg-names = "QuadSPI", "QuadSPI-memory";
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "qspi_en", "qspi";
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>,
<&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>;
status = "disabled";
};
@ -443,7 +454,7 @@
reg = <0x0 0x2140000 0x0 0x10000>;
interrupts = <0 28 0x4>; /* Level high type */
clock-frequency = <0>;
clocks = <&clockgen 2 1>;
clocks = <&clockgen QORIQ_CLK_HWACCEL 1>;
voltage-ranges = <1800 1800 3300 3300>;
sdhci,auto-cmd12;
little-endian;
@ -478,7 +489,8 @@
<0x7 0x100520 0x0 0x4>;
reg-names = "ahci", "sata-ecc";
interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 3>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>;
dma-coherent;
status = "disabled";
};
@ -729,7 +741,8 @@
ptp-timer@8b95000 {
compatible = "fsl,dpaa2-ptp";
reg = <0x0 0x8b95000 0x0 0x100>;
clocks = <&clockgen 4 0>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
little-endian;
fsl,extts-fifo;
};
@ -818,56 +831,80 @@
cluster1_core0_watchdog: wdt@c000000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc000000 0x0 0x1000>;
clocks = <&clockgen 4 15>, <&clockgen 4 15>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>,
<&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
clock-names = "wdog_clk", "apb_pclk";
};
cluster1_core1_watchdog: wdt@c010000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc010000 0x0 0x1000>;
clocks = <&clockgen 4 15>, <&clockgen 4 15>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>,
<&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
clock-names = "wdog_clk", "apb_pclk";
};
cluster1_core2_watchdog: wdt@c020000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc020000 0x0 0x1000>;
clocks = <&clockgen 4 15>, <&clockgen 4 15>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>,
<&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
clock-names = "wdog_clk", "apb_pclk";
};
cluster1_core3_watchdog: wdt@c030000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc030000 0x0 0x1000>;
clocks = <&clockgen 4 15>, <&clockgen 4 15>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>,
<&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
clock-names = "wdog_clk", "apb_pclk";
};
cluster2_core0_watchdog: wdt@c100000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc100000 0x0 0x1000>;
clocks = <&clockgen 4 15>, <&clockgen 4 15>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>,
<&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
clock-names = "wdog_clk", "apb_pclk";
};
cluster2_core1_watchdog: wdt@c110000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc110000 0x0 0x1000>;
clocks = <&clockgen 4 15>, <&clockgen 4 15>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>,
<&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
clock-names = "wdog_clk", "apb_pclk";
};
cluster2_core2_watchdog: wdt@c120000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc120000 0x0 0x1000>;
clocks = <&clockgen 4 15>, <&clockgen 4 15>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>,
<&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
clock-names = "wdog_clk", "apb_pclk";
};
cluster2_core3_watchdog: wdt@c130000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc130000 0x0 0x1000>;
clocks = <&clockgen 4 15>, <&clockgen 4 15>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>,
<&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
clock-names = "wdog_clk", "apb_pclk";
};