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Merge branch 'master' into next

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Merge master back into next, this allows us to resolve some conflicts in
arch/powerpc/Kconfig, and also re-sort the symbols under config PPC so
that they are in alphabetical order again.
This commit is contained in:
Michael Ellerman
2021-05-08 21:12:55 +10:00
parent 32b48bf851 dd860052c9
commit f96271cefe
1332 changed files with 34066 additions and 14651 deletions
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30
Documentation/ABI/testing/sysfs-bus-event_source-devices-dsa Normal file
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@@ -0,0 +1,30 @@
What: /sys/bus/event_source/devices/dsa*/format
Date: April 2021
KernelVersion: 5.13
Contact: Tom Zanussi <tom.zanussi@linux.intel.com>
Description: Read-only. Attribute group to describe the magic bits
that go into perf_event_attr.config or
perf_event_attr.config1 for the IDXD DSA pmu. (See also
ABI/testing/sysfs-bus-event_source-devices-format).
Each attribute in this group defines a bit range in
perf_event_attr.config or perf_event_attr.config1.
All supported attributes are listed below (See the
IDXD DSA Spec for possible attribute values)::
event_category = "config:0-3" - event category
event = "config:4-31" - event ID
filter_wq = "config1:0-31" - workqueue filter
filter_tc = "config1:32-39" - traffic class filter
filter_pgsz = "config1:40-43" - page size filter
filter_sz = "config1:44-51" - transfer size filter
filter_eng = "config1:52-59" - engine filter
What: /sys/bus/event_source/devices/dsa*/cpumask
Date: April 2021
KernelVersion: 5.13
Contact: Tom Zanussi <tom.zanussi@linux.intel.com>
Description: Read-only. This file always returns the cpu to which the
IDXD DSA pmu is bound for access to all dsa pmu
performance monitoring events.

2
Documentation/ABI/testing/sysfs-devices-system-cpu
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@@ -285,7 +285,7 @@ Description: Disable L3 cache indices
All AMD processors with L3 caches provide this functionality. All AMD processors with L3 caches provide this functionality.
For details, see BKDGs at For details, see BKDGs at
http://developer.amd.com/documentation/guides/Pages/default.aspx https://www.amd.com/en/support/tech-docs?keyword=bios+kernel
What: /sys/devices/system/cpu/cpufreq/boost What: /sys/devices/system/cpu/cpufreq/boost

9
Documentation/ABI/testing/sysfs-driver-input-exc3000
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@@ -15,3 +15,12 @@ Description: Reports the model identification provided by the touchscreen, fo
Access: Read Access: Read
Valid values: Represented as string Valid values: Represented as string
What: /sys/bus/i2c/devices/xxx/type
Date: Jan 2021
Contact: linux-input@vger.kernel.org
Description: Reports the type identification provided by the touchscreen, for example "PCAP82H80 Series"
Access: Read
Valid values: Represented as string

31
Documentation/ABI/testing/sysfs-fs-f2fs
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@@ -276,7 +276,7 @@ Date April 2019
Contact: "Daniel Rosenberg" <drosen@google.com> Contact: "Daniel Rosenberg" <drosen@google.com>
Description: If checkpoint=disable, it displays the number of blocks that Description: If checkpoint=disable, it displays the number of blocks that
are unusable. are unusable.
If checkpoint=enable it displays the enumber of blocks that If checkpoint=enable it displays the number of blocks that
would be unusable if checkpoint=disable were to be set. would be unusable if checkpoint=disable were to be set.
What: /sys/fs/f2fs/<disk>/encoding What: /sys/fs/f2fs/<disk>/encoding
@@ -409,3 +409,32 @@ Description: Give a way to change checkpoint merge daemon's io priority.
I/O priority "3". We can select the class between "rt" and "be", I/O priority "3". We can select the class between "rt" and "be",
and set the I/O priority within valid range of it. "," delimiter and set the I/O priority within valid range of it. "," delimiter
is necessary in between I/O class and priority number. is necessary in between I/O class and priority number.
What: /sys/fs/f2fs/<disk>/ovp_segments
Date: March 2021
Contact: "Jaegeuk Kim" <jaegeuk@kernel.org>
Description: Shows the number of overprovision segments.
What: /sys/fs/f2fs/<disk>/compr_written_block
Date: March 2021
Contact: "Daeho Jeong" <daehojeong@google.com>
Description: Show the block count written after compression since mount. Note
that when the compressed blocks are deleted, this count doesn't
decrease. If you write "0" here, you can initialize
compr_written_block and compr_saved_block to "0".
What: /sys/fs/f2fs/<disk>/compr_saved_block
Date: March 2021
Contact: "Daeho Jeong" <daehojeong@google.com>
Description: Show the saved block count with compression since mount. Note
that when the compressed blocks are deleted, this count doesn't
decrease. If you write "0" here, you can initialize
compr_written_block and compr_saved_block to "0".
What: /sys/fs/f2fs/<disk>/compr_new_inode
Date: March 2021
Contact: "Daeho Jeong" <daehojeong@google.com>
Description: Show the count of inode newly enabled for compression since mount.
Note that when the compression is disabled for the files, this count
doesn't decrease. If you write "0" here, you can initialize
compr_new_inode to "0".

25
Documentation/ABI/testing/sysfs-kernel-mm-cma Normal file
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@@ -0,0 +1,25 @@
What: /sys/kernel/mm/cma/
Date: Feb 2021
Contact: Minchan Kim <minchan@kernel.org>
Description:
/sys/kernel/mm/cma/ contains a subdirectory for each CMA
heap name (also sometimes called CMA areas).
Each CMA heap subdirectory (that is, each
/sys/kernel/mm/cma/<cma-heap-name> directory) contains the
following items:
alloc_pages_success
alloc_pages_fail
What: /sys/kernel/mm/cma/<cma-heap-name>/alloc_pages_success
Date: Feb 2021
Contact: Minchan Kim <minchan@kernel.org>
Description:
the number of pages CMA API succeeded to allocate
What: /sys/kernel/mm/cma/<cma-heap-name>/alloc_pages_fail
Date: Feb 2021
Contact: Minchan Kim <minchan@kernel.org>
Description:
the number of pages CMA API failed to allocate

2
Documentation/admin-guide/devices.txt
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@@ -4,7 +4,7 @@
1 char Memory devices 1 char Memory devices
1 = /dev/mem Physical memory access 1 = /dev/mem Physical memory access
2 = /dev/kmem Kernel virtual memory access 2 = /dev/kmem OBSOLETE - replaced by /proc/kcore
3 = /dev/null Null device 3 = /dev/null Null device
4 = /dev/port I/O port access 4 = /dev/port I/O port access
5 = /dev/zero Null byte source 5 = /dev/zero Null byte source

11
Documentation/admin-guide/gpio/gpio-mockup.rst
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@@ -17,17 +17,18 @@ module.
gpio_mockup_ranges gpio_mockup_ranges
This parameter takes an argument in the form of an array of integer This parameter takes an argument in the form of an array of integer
pairs. Each pair defines the base GPIO number (if any) and the number pairs. Each pair defines the base GPIO number (non-negative integer)
of lines exposed by the chip. If the base GPIO is -1, the gpiolib and the first number after the last of this chip. If the base GPIO
will assign it automatically. is -1, the gpiolib will assign it automatically. while the following
parameter is the number of lines exposed by the chip.
Example: gpio_mockup_ranges=-1,8,-1,16,405,4 Example: gpio_mockup_ranges=-1,8,-1,16,405,409
The line above creates three chips. The first one will expose 8 lines, The line above creates three chips. The first one will expose 8 lines,
the second 16 and the third 4. The base GPIO for the third chip is set the second 16 and the third 4. The base GPIO for the third chip is set
to 405 while for two first chips it will be assigned automatically. to 405 while for two first chips it will be assigned automatically.
gpio_named_lines gpio_mockup_named_lines
This parameter doesn't take any arguments. It lets the driver know that This parameter doesn't take any arguments. It lets the driver know that
GPIO lines exposed by it should be named. GPIO lines exposed by it should be named.

41
Documentation/admin-guide/kernel-parameters.txt
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@@ -1469,6 +1469,12 @@
Don't use this when you are not running on the Don't use this when you are not running on the
android emulator android emulator
gpio-mockup.gpio_mockup_ranges
[HW] Sets the ranges of gpiochip of for this device.
Format: <start1>,<end1>,<start2>,<end2>...
gpio-mockup.gpio_mockup_named_lines
[HW] Let the driver know GPIO lines should be named.
gpt [EFI] Forces disk with valid GPT signature but gpt [EFI] Forces disk with valid GPT signature but
invalid Protective MBR to be treated as GPT. If the invalid Protective MBR to be treated as GPT. If the
primary GPT is corrupted, it enables the backup/alternate primary GPT is corrupted, it enables the backup/alternate
@@ -1492,10 +1498,6 @@
Format: <unsigned int> such that (rxsize & ~0x1fffc0) == 0. Format: <unsigned int> such that (rxsize & ~0x1fffc0) == 0.
Default: 1024 Default: 1024
gpio-mockup.gpio_mockup_ranges
[HW] Sets the ranges of gpiochip of for this device.
Format: <start1>,<end1>,<start2>,<end2>...
hardlockup_all_cpu_backtrace= hardlockup_all_cpu_backtrace=
[KNL] Should the hard-lockup detector generate [KNL] Should the hard-lockup detector generate
backtraces on all cpus. backtraces on all cpus.
@@ -1833,6 +1835,18 @@
initcall functions. Useful for debugging built-in initcall functions. Useful for debugging built-in
modules and initcalls. modules and initcalls.
initramfs_async= [KNL]
Format: <bool>
Default: 1
This parameter controls whether the initramfs
image is unpacked asynchronously, concurrently
with devices being probed and
initialized. This should normally just work,
but as a debugging aid, one can get the
historical behaviour of the initramfs
unpacking being completed before device_ and
late_ initcalls.
initrd= [BOOT] Specify the location of the initial ramdisk initrd= [BOOT] Specify the location of the initial ramdisk
initrdmem= [KNL] Specify a physical address and size from which to initrdmem= [KNL] Specify a physical address and size from which to
@@ -2802,7 +2816,24 @@
seconds. Use this parameter to check at some seconds. Use this parameter to check at some
other rate. 0 disables periodic checking. other rate. 0 disables periodic checking.
memtest= [KNL,X86,ARM,PPC] Enable memtest memory_hotplug.memmap_on_memory
[KNL,X86,ARM] Boolean flag to enable this feature.
Format: {on | off (default)}
When enabled, runtime hotplugged memory will
allocate its internal metadata (struct pages)
from the hotadded memory which will allow to
hotadd a lot of memory without requiring
additional memory to do so.
This feature is disabled by default because it
has some implication on large (e.g. GB)
allocations in some configurations (e.g. small
memory blocks).
The state of the flag can be read in
/sys/module/memory_hotplug/parameters/memmap_on_memory.
Note that even when enabled, there are a few cases where
the feature is not effective.
memtest= [KNL,X86,ARM,PPC,RISCV] Enable memtest
Format: <integer> Format: <integer>
default : 0 <disable> default : 0 <disable>
Specifies the number of memtest passes to be Specifies the number of memtest passes to be

9
Documentation/admin-guide/mm/memory-hotplug.rst
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@@ -357,6 +357,15 @@ creates ZONE_MOVABLE as following.
Unfortunately, there is no information to show which memory block belongs Unfortunately, there is no information to show which memory block belongs
to ZONE_MOVABLE. This is TBD. to ZONE_MOVABLE. This is TBD.
.. note::
Techniques that rely on long-term pinnings of memory (especially, RDMA and
vfio) are fundamentally problematic with ZONE_MOVABLE and, therefore, memory
hot remove. Pinned pages cannot reside on ZONE_MOVABLE, to guarantee that
memory can still get hot removed - be aware that pinning can fail even if
there is plenty of free memory in ZONE_MOVABLE. In addition, using
ZONE_MOVABLE might make page pinning more expensive, because pages have to be
migrated off that zone first.
.. _memory_hotplug_how_to_offline_memory: .. _memory_hotplug_how_to_offline_memory:
How to offline memory How to offline memory

99
Documentation/admin-guide/mm/userfaultfd.rst
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@@ -63,36 +63,36 @@ the generic ioctl available.
The ``uffdio_api.features`` bitmask returned by the ``UFFDIO_API`` ioctl The ``uffdio_api.features`` bitmask returned by the ``UFFDIO_API`` ioctl
defines what memory types are supported by the ``userfaultfd`` and what defines what memory types are supported by the ``userfaultfd`` and what
events, except page fault notifications, may be generated. events, except page fault notifications, may be generated:
If the kernel supports registering ``userfaultfd`` ranges on hugetlbfs - The ``UFFD_FEATURE_EVENT_*`` flags indicate that various other events
virtual memory areas, ``UFFD_FEATURE_MISSING_HUGETLBFS`` will be set in other than page faults are supported. These events are described in more
``uffdio_api.features``. Similarly, ``UFFD_FEATURE_MISSING_SHMEM`` will be detail below in the `Non-cooperative userfaultfd`_ section.
set if the kernel supports registering ``userfaultfd`` ranges on shared
memory (covering all shmem APIs, i.e. tmpfs, ``IPCSHM``, ``/dev/zero``,
``MAP_SHARED``, ``memfd_create``, etc).
The userland application that wants to use ``userfaultfd`` with hugetlbfs - ``UFFD_FEATURE_MISSING_HUGETLBFS`` and ``UFFD_FEATURE_MISSING_SHMEM``
or shared memory need to set the corresponding flag in indicate that the kernel supports ``UFFDIO_REGISTER_MODE_MISSING``
``uffdio_api.features`` to enable those features. registrations for hugetlbfs and shared memory (covering all shmem APIs,
i.e. tmpfs, ``IPCSHM``, ``/dev/zero``, ``MAP_SHARED``, ``memfd_create``,
etc) virtual memory areas, respectively.
If the userland desires to receive notifications for events other than - ``UFFD_FEATURE_MINOR_HUGETLBFS`` indicates that the kernel supports
page faults, it has to verify that ``uffdio_api.features`` has appropriate ``UFFDIO_REGISTER_MODE_MINOR`` registration for hugetlbfs virtual memory
``UFFD_FEATURE_EVENT_*`` bits set. These events are described in more areas.
detail below in `Non-cooperative userfaultfd`_ section.
Once the ``userfaultfd`` has been enabled the ``UFFDIO_REGISTER`` ioctl should The userland application should set the feature flags it intends to use
be invoked (if present in the returned ``uffdio_api.ioctls`` bitmask) to when invoking the ``UFFDIO_API`` ioctl, to request that those features be
register a memory range in the ``userfaultfd`` by setting the enabled if supported.
Once the ``userfaultfd`` API has been enabled the ``UFFDIO_REGISTER``
ioctl should be invoked (if present in the returned ``uffdio_api.ioctls``
bitmask) to register a memory range in the ``userfaultfd`` by setting the
uffdio_register structure accordingly. The ``uffdio_register.mode`` uffdio_register structure accordingly. The ``uffdio_register.mode``
bitmask will specify to the kernel which kind of faults to track for bitmask will specify to the kernel which kind of faults to track for
the range (``UFFDIO_REGISTER_MODE_MISSING`` would track missing the range. The ``UFFDIO_REGISTER`` ioctl will return the
pages). The ``UFFDIO_REGISTER`` ioctl will return the
``uffdio_register.ioctls`` bitmask of ioctls that are suitable to resolve ``uffdio_register.ioctls`` bitmask of ioctls that are suitable to resolve
userfaults on the range registered. Not all ioctls will necessarily be userfaults on the range registered. Not all ioctls will necessarily be
supported for all memory types depending on the underlying virtual supported for all memory types (e.g. anonymous memory vs. shmem vs.
memory backend (anonymous memory vs tmpfs vs real filebacked hugetlbfs), or all types of intercepted faults.
mappings).
Userland can use the ``uffdio_register.ioctls`` to manage the virtual Userland can use the ``uffdio_register.ioctls`` to manage the virtual
address space in the background (to add or potentially also remove address space in the background (to add or potentially also remove
@@ -100,21 +100,46 @@ memory from the ``userfaultfd`` registered range). This means a userfault
could be triggering just before userland maps in the background the could be triggering just before userland maps in the background the
user-faulted page. user-faulted page.
The primary ioctl to resolve userfaults is ``UFFDIO_COPY``. That Resolving Userfaults
atomically copies a page into the userfault registered range and wakes --------------------
up the blocked userfaults
(unless ``uffdio_copy.mode & UFFDIO_COPY_MODE_DONTWAKE`` is set). There are three basic ways to resolve userfaults:
Other ioctl works similarly to ``UFFDIO_COPY``. They're atomic as in
guaranteeing that nothing can see an half copied page since it'll - ``UFFDIO_COPY`` atomically copies some existing page contents from
keep userfaulting until the copy has finished. userspace.
- ``UFFDIO_ZEROPAGE`` atomically zeros the new page.
- ``UFFDIO_CONTINUE`` maps an existing, previously-populated page.
These operations are atomic in the sense that they guarantee nothing can
see a half-populated page, since readers will keep userfaulting until the
operation has finished.
By default, these wake up userfaults blocked on the range in question.
They support a ``UFFDIO_*_MODE_DONTWAKE`` ``mode`` flag, which indicates
that waking will be done separately at some later time.
Which ioctl to choose depends on the kind of page fault, and what we'd
like to do to resolve it:
- For ``UFFDIO_REGISTER_MODE_MISSING`` faults, the fault needs to be
resolved by either providing a new page (``UFFDIO_COPY``), or mapping
the zero page (``UFFDIO_ZEROPAGE``). By default, the kernel would map
the zero page for a missing fault. With userfaultfd, userspace can
decide what content to provide before the faulting thread continues.
- For ``UFFDIO_REGISTER_MODE_MINOR`` faults, there is an existing page (in
the page cache). Userspace has the option of modifying the page's
contents before resolving the fault. Once the contents are correct
(modified or not), userspace asks the kernel to map the page and let the
faulting thread continue with ``UFFDIO_CONTINUE``.
Notes: Notes:
- If you requested ``UFFDIO_REGISTER_MODE_MISSING`` when registering then - You can tell which kind of fault occurred by examining
you must provide some kind of page in your thread after reading from ``pagefault.flags`` within the ``uffd_msg``, checking for the
the uffd. You must provide either ``UFFDIO_COPY`` or ``UFFDIO_ZEROPAGE``. ``UFFD_PAGEFAULT_FLAG_*`` flags.
The normal behavior of the OS automatically providing a zero page on
an anonymous mmaping is not in place.
- None of the page-delivering ioctls default to the range that you - None of the page-delivering ioctls default to the range that you
registered with. You must fill in all fields for the appropriate registered with. You must fill in all fields for the appropriate
@@ -122,9 +147,9 @@ Notes:
- You get the address of the access that triggered the missing page - You get the address of the access that triggered the missing page
event out of a struct uffd_msg that you read in the thread from the event out of a struct uffd_msg that you read in the thread from the
uffd. You can supply as many pages as you want with ``UFFDIO_COPY`` or uffd. You can supply as many pages as you want with these IOCTLs.
``UFFDIO_ZEROPAGE``. Keep in mind that unless you used DONTWAKE then Keep in mind that unless you used DONTWAKE then the first of any of
the first of any of those IOCTLs wakes up the faulting thread. those IOCTLs wakes up the faulting thread.
- Be sure to test for all errors including - Be sure to test for all errors including
(``pollfd[0].revents & POLLERR``). This can happen, e.g. when ranges (``pollfd[0].revents & POLLERR``). This can happen, e.g. when ranges

49
Documentation/admin-guide/reporting-issues.rst
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@@ -24,7 +24,8 @@ longterm series? One still supported? Then search the `LKML
you don't find any, install `the latest release from that series you don't find any, install `the latest release from that series
<https://kernel.org/>`_. If it still shows the issue, report it to the stable <https://kernel.org/>`_. If it still shows the issue, report it to the stable
mailing list (stable@vger.kernel.org) and CC the regressions list mailing list (stable@vger.kernel.org) and CC the regressions list
(regressions@lists.linux.dev). (regressions@lists.linux.dev); ideally also CC the maintainer and the mailing
list for the subsystem in question.
In all other cases try your best guess which kernel part might be causing the In all other cases try your best guess which kernel part might be causing the
issue. Check the :ref:`MAINTAINERS <maintainers>` file for how its developers issue. Check the :ref:`MAINTAINERS <maintainers>` file for how its developers
@@ -48,8 +49,9 @@ before the issue occurs.
If you are facing multiple issues with the Linux kernel at once, report each If you are facing multiple issues with the Linux kernel at once, report each
separately. While writing your report, include all information relevant to the separately. While writing your report, include all information relevant to the
issue, like the kernel and the distro used. In case of a regression, CC the issue, like the kernel and the distro used. In case of a regression, CC the
regressions mailing list (regressions@lists.linux.dev) to your report; also try regressions mailing list (regressions@lists.linux.dev) to your report. Also try
to include the commit-id of the change causing it, which a bisection can find. to pin-point the culprit with a bisection; if you succeed, include its
commit-id and CC everyone in the sign-off-by chain.
Once the report is out, answer any questions that come up and help where you Once the report is out, answer any questions that come up and help where you
can. That includes keeping the ball rolling by occasionally retesting with newer can. That includes keeping the ball rolling by occasionally retesting with newer
@@ -198,10 +200,11 @@ report them:
* Send a short problem report to the Linux stable mailing list * Send a short problem report to the Linux stable mailing list
(stable@vger.kernel.org) and CC the Linux regressions mailing list (stable@vger.kernel.org) and CC the Linux regressions mailing list
(regressions@lists.linux.dev). Roughly describe the issue and ideally (regressions@lists.linux.dev); if you suspect the cause in a particular
explain how to reproduce it. Mention the first version that shows the subsystem, CC its maintainer and its mailing list. Roughly describe the
problem and the last version that's working fine. Then wait for further issue and ideally explain how to reproduce it. Mention the first version
instructions. that shows the problem and the last version that's working fine. Then
wait for further instructions.
The reference section below explains each of these steps in more detail. The reference section below explains each of these steps in more detail.
@@ -768,7 +771,9 @@ regular internet search engine and add something like
the results to the archives at that URL. the results to the archives at that URL.
It's also wise to check the internet, LKML and maybe bugzilla.kernel.org again It's also wise to check the internet, LKML and maybe bugzilla.kernel.org again
at this point. at this point. If your report needs to be filed in a bug tracker, you may want
to check the mailing list archives for the subsystem as well, as someone might
have reported it only there.
For details how to search and what to do if you find matching reports see For details how to search and what to do if you find matching reports see
"Search for existing reports, first run" above. "Search for existing reports, first run" above.
@@ -1249,9 +1254,10 @@ and the oldest where the issue occurs (say 5.8-rc1).
When sending the report by mail, CC the Linux regressions mailing list When sending the report by mail, CC the Linux regressions mailing list
(regressions@lists.linux.dev). In case the report needs to be filed to some web (regressions@lists.linux.dev). In case the report needs to be filed to some web
tracker, proceed to do so; once filed, forward the report by mail to the tracker, proceed to do so. Once filed, forward the report by mail to the
regressions list. Make sure to inline the forwarded report, hence do not attach regressions list; CC the maintainer and the mailing list for the subsystem in
it. Also add a short note at the top where you mention the URL to the ticket. question. Make sure to inline the forwarded report, hence do not attach it.
Also add a short note at the top where you mention the URL to the ticket.
When mailing or forwarding the report, in case of a successful bisection add the When mailing or forwarding the report, in case of a successful bisection add the
author of the culprit to the recipients; also CC everyone in the signed-off-by author of the culprit to the recipients; also CC everyone in the signed-off-by
@@ -1536,17 +1542,20 @@ Report the regression
*Send a short problem report to the Linux stable mailing list *Send a short problem report to the Linux stable mailing list
(stable@vger.kernel.org) and CC the Linux regressions mailing list (stable@vger.kernel.org) and CC the Linux regressions mailing list
(regressions@lists.linux.dev). Roughly describe the issue and ideally (regressions@lists.linux.dev); if you suspect the cause in a particular
explain how to reproduce it. Mention the first version that shows the subsystem, CC its maintainer and its mailing list. Roughly describe the
problem and the last version that's working fine. Then wait for further issue and ideally explain how to reproduce it. Mention the first version
instructions.* that shows the problem and the last version that's working fine. Then
wait for further instructions.*
When reporting a regression that happens within a stable or longterm kernel When reporting a regression that happens within a stable or longterm kernel
line (say when updating from 5.10.4 to 5.10.5) a brief report is enough for line (say when updating from 5.10.4 to 5.10.5) a brief report is enough for
the start to get the issue reported quickly. Hence a rough description is all the start to get the issue reported quickly. Hence a rough description to the
it takes. stable and regressions mailing list is all it takes; but in case you suspect
the cause in a particular subsystem, CC its maintainers and its mailing list
as well, because that will speed things up.
But note, it helps developers a great deal if you can specify the exact version And note, it helps developers a great deal if you can specify the exact version
that introduced the problem. Hence if possible within a reasonable time frame, that introduced the problem. Hence if possible within a reasonable time frame,
try to find that version using vanilla kernels. Lets assume something broke when try to find that version using vanilla kernels. Lets assume something broke when
your distributor released a update from Linux kernel 5.10.5 to 5.10.8. Then as your distributor released a update from Linux kernel 5.10.5 to 5.10.8. Then as
@@ -1563,7 +1572,9 @@ pinpoint the exact change that causes the issue (which then can easily get
reverted to fix the issue quickly). Hence consider to do a proper bisection reverted to fix the issue quickly). Hence consider to do a proper bisection
right away if time permits. See the section 'Special care for regressions' and right away if time permits. See the section 'Special care for regressions' and
the document 'Documentation/admin-guide/bug-bisect.rst' for details how to the document 'Documentation/admin-guide/bug-bisect.rst' for details how to
perform one. perform one. In case of a successful bisection add the author of the culprit to
the recipients; also CC everyone in the signed-off-by chain, which you find at
the end of its commit message.
Reference for "Reporting issues only occurring in older kernel version lines" Reference for "Reporting issues only occurring in older kernel version lines"

33
Documentation/arm64/booting.rst
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@@ -277,9 +277,40 @@ Before jumping into the kernel, the following conditions must be met:
- SCR_EL3.FGTEn (bit 27) must be initialised to 0b1. - SCR_EL3.FGTEn (bit 27) must be initialised to 0b1.
For CPUs with Advanced SIMD and floating point support:
- If EL3 is present:
- CPTR_EL3.TFP (bit 10) must be initialised to 0b0.
- If EL2 is present and the kernel is entered at EL1:
- CPTR_EL2.TFP (bit 10) must be initialised to 0b0.
For CPUs with the Scalable Vector Extension (FEAT_SVE) present:
- if EL3 is present:
- CPTR_EL3.EZ (bit 8) must be initialised to 0b1.
- ZCR_EL3.LEN must be initialised to the same value for all CPUs the
kernel is executed on.
- If the kernel is entered at EL1 and EL2 is present:
- CPTR_EL2.TZ (bit 8) must be initialised to 0b0.
- CPTR_EL2.ZEN (bits 17:16) must be initialised to 0b11.
- ZCR_EL2.LEN must be initialised to the same value for all CPUs the
kernel will execute on.
The requirements described above for CPU mode, caches, MMUs, architected The requirements described above for CPU mode, caches, MMUs, architected
timers, coherency and system registers apply to all CPUs. All CPUs must timers, coherency and system registers apply to all CPUs. All CPUs must
enter the kernel in the same exception level. enter the kernel in the same exception level. Where the values documented
disable traps it is permissible for these traps to be enabled so long as
those traps are handled transparently by higher exception levels as though
the values documented were set.
The boot loader is expected to enter the kernel on each CPU in the The boot loader is expected to enter the kernel on each CPU in the
following manner: following manner:

2
Documentation/arm64/elf_hwcaps.rst
View File

@@ -74,7 +74,7 @@ HWCAP_ASIMD
HWCAP_EVTSTRM HWCAP_EVTSTRM
The generic timer is configured to generate events at a frequency of The generic timer is configured to generate events at a frequency of
approximately 100KHz. approximately 10KHz.
HWCAP_AES HWCAP_AES
Functionality implied by ID_AA64ISAR0_EL1.AES == 0b0001. Functionality implied by ID_AA64ISAR0_EL1.AES == 0b0001.

6
Documentation/arm64/tagged-address-abi.rst
View File

@@ -113,6 +113,12 @@ ABI relaxation:
- ``shmat()`` and ``shmdt()``. - ``shmat()`` and ``shmdt()``.
- ``brk()`` (since kernel v5.6).
- ``mmap()`` (since kernel v5.6).
- ``mremap()``, the ``new_address`` argument (since kernel v5.6).
Any attempt to use non-zero tagged pointers may result in an error code Any attempt to use non-zero tagged pointers may result in an error code
being returned, a (fatal) signal being raised, or other modes of being returned, a (fatal) signal being raised, or other modes of
failure. failure.

88
Documentation/core-api/dma-api.rst
View File

@@ -563,6 +563,16 @@ Free a region of memory previously allocated using dma_alloc_pages().
dev, size, dma_handle and dir must all be the same as those passed into dev, size, dma_handle and dir must all be the same as those passed into
dma_alloc_pages(). page must be the pointer returned by dma_alloc_pages(). dma_alloc_pages(). page must be the pointer returned by dma_alloc_pages().
::
int
dma_mmap_pages(struct device *dev, struct vm_area_struct *vma,
size_t size, struct page *page)
Map an allocation returned from dma_alloc_pages() into a user address space.
dev and size must be the same as those passed into dma_alloc_pages().
page must be the pointer returned by dma_alloc_pages().
:: ::
void * void *
@@ -584,6 +594,84 @@ dev, size, dma_handle and dir must all be the same as those passed into
dma_alloc_noncoherent(). cpu_addr must be the virtual address returned by dma_alloc_noncoherent(). cpu_addr must be the virtual address returned by
dma_alloc_noncoherent(). dma_alloc_noncoherent().
::
struct sg_table *
dma_alloc_noncontiguous(struct device *dev, size_t size,
enum dma_data_direction dir, gfp_t gfp,
unsigned long attrs);
This routine allocates <size> bytes of non-coherent and possibly non-contiguous
memory. It returns a pointer to struct sg_table that describes the allocated
and DMA mapped memory, or NULL if the allocation failed. The resulting memory
can be used for struct page mapped into a scatterlist are suitable for.
The return sg_table is guaranteed to have 1 single DMA mapped segment as
indicated by sgt->nents, but it might have multiple CPU side segments as
indicated by sgt->orig_nents.
The dir parameter specified if data is read and/or written by the device,
see dma_map_single() for details.
The gfp parameter allows the caller to specify the ``GFP_`` flags (see
kmalloc()) for the allocation, but rejects flags used to specify a memory
zone such as GFP_DMA or GFP_HIGHMEM.
The attrs argument must be either 0 or DMA_ATTR_ALLOC_SINGLE_PAGES.
Before giving the memory to the device, dma_sync_sgtable_for_device() needs
to be called, and before reading memory written by the device,
dma_sync_sgtable_for_cpu(), just like for streaming DMA mappings that are
reused.
::
void
dma_free_noncontiguous(struct device *dev, size_t size,
struct sg_table *sgt,
enum dma_data_direction dir)
Free memory previously allocated using dma_alloc_noncontiguous(). dev, size,
and dir must all be the same as those passed into dma_alloc_noncontiguous().
sgt must be the pointer returned by dma_alloc_noncontiguous().
::
void *
dma_vmap_noncontiguous(struct device *dev, size_t size,
struct sg_table *sgt)
Return a contiguous kernel mapping for an allocation returned from
dma_alloc_noncontiguous(). dev and size must be the same as those passed into
dma_alloc_noncontiguous(). sgt must be the pointer returned by
dma_alloc_noncontiguous().
Once a non-contiguous allocation is mapped using this function, the
flush_kernel_vmap_range() and invalidate_kernel_vmap_range() APIs must be used
to manage the coherency between the kernel mapping, the device and user space
mappings (if any).
::
void
dma_vunmap_noncontiguous(struct device *dev, void *vaddr)
Unmap a kernel mapping returned by dma_vmap_noncontiguous(). dev must be the
same the one passed into dma_alloc_noncontiguous(). vaddr must be the pointer
returned by dma_vmap_noncontiguous().
::
int
dma_mmap_noncontiguous(struct device *dev, struct vm_area_struct *vma,
size_t size, struct sg_table *sgt)
Map an allocation returned from dma_alloc_noncontiguous() into a user address
space. dev and size must be the same as those passed into
dma_alloc_noncontiguous(). sgt must be the pointer returned by
dma_alloc_noncontiguous().
:: ::
int int

22
Documentation/core-api/irq/irq-domain.rst
View File

@@ -42,10 +42,10 @@ irq_domain usage
================ ================
An interrupt controller driver creates and registers an irq_domain by An interrupt controller driver creates and registers an irq_domain by
calling one of the irq_domain_add_*() functions (each mapping method calling one of the irq_domain_add_*() or irq_domain_create_*() functions
has a different allocator function, more on that later). The function (each mapping method has a different allocator function, more on that later).
will return a pointer to the irq_domain on success. The caller must The function will return a pointer to the irq_domain on success. The caller
provide the allocator function with an irq_domain_ops structure. must provide the allocator function with an irq_domain_ops structure.
In most cases, the irq_domain will begin empty without any mappings In most cases, the irq_domain will begin empty without any mappings
between hwirq and IRQ numbers. Mappings are added to the irq_domain between hwirq and IRQ numbers. Mappings are added to the irq_domain
@@ -147,6 +147,7 @@ Legacy
irq_domain_add_simple() irq_domain_add_simple()
irq_domain_add_legacy() irq_domain_add_legacy()
irq_domain_add_legacy_isa() irq_domain_add_legacy_isa()
irq_domain_create_simple()
irq_domain_create_legacy() irq_domain_create_legacy()
The Legacy mapping is a special case for drivers that already have a The Legacy mapping is a special case for drivers that already have a
@@ -169,13 +170,13 @@ supported. For example, ISA controllers would use the legacy map for
mapping Linux IRQs 0-15 so that existing ISA drivers get the correct IRQ mapping Linux IRQs 0-15 so that existing ISA drivers get the correct IRQ
numbers. numbers.
Most users of legacy mappings should use irq_domain_add_simple() which Most users of legacy mappings should use irq_domain_add_simple() or
will use a legacy domain only if an IRQ range is supplied by the irq_domain_create_simple() which will use a legacy domain only if an IRQ range
system and will otherwise use a linear domain mapping. The semantics is supplied by the system and will otherwise use a linear domain mapping.
of this call are such that if an IRQ range is specified then The semantics of this call are such that if an IRQ range is specified then
descriptors will be allocated on-the-fly for it, and if no range is descriptors will be allocated on-the-fly for it, and if no range is
specified it will fall through to irq_domain_add_linear() which means specified it will fall through to irq_domain_add_linear() or
*no* irq descriptors will be allocated. irq_domain_create_linear() which means *no* irq descriptors will be allocated.
A typical use case for simple domains is where an irqchip provider A typical use case for simple domains is where an irqchip provider
is supporting both dynamic and static IRQ assignments. is supporting both dynamic and static IRQ assignments.
@@ -186,6 +187,7 @@ that the driver using the simple domain call irq_create_mapping()
before any irq_find_mapping() since the latter will actually work before any irq_find_mapping() since the latter will actually work
for the static IRQ assignment case. for the static IRQ assignment case.
irq_domain_add_simple() and irq_domain_create_simple() as well as
irq_domain_add_legacy() and irq_domain_create_legacy() are functionally irq_domain_add_legacy() and irq_domain_create_legacy() are functionally
equivalent, except for the first argument is different - the former equivalent, except for the first argument is different - the former
accepts an Open Firmware specific 'struct device_node', while the latter accepts an Open Firmware specific 'struct device_node', while the latter

26
Documentation/core-api/symbol-namespaces.rst
View File

@@ -43,14 +43,14 @@ exporting of kernel symbols to the kernel symbol table, variants of these are
available to export symbols into a certain namespace: EXPORT_SYMBOL_NS() and available to export symbols into a certain namespace: EXPORT_SYMBOL_NS() and
EXPORT_SYMBOL_NS_GPL(). They take one additional argument: the namespace. EXPORT_SYMBOL_NS_GPL(). They take one additional argument: the namespace.
Please note that due to macro expansion that argument needs to be a Please note that due to macro expansion that argument needs to be a
preprocessor symbol. E.g. to export the symbol `usb_stor_suspend` into the preprocessor symbol. E.g. to export the symbol ``usb_stor_suspend`` into the
namespace `USB_STORAGE`, use:: namespace ``USB_STORAGE``, use::
EXPORT_SYMBOL_NS(usb_stor_suspend, USB_STORAGE); EXPORT_SYMBOL_NS(usb_stor_suspend, USB_STORAGE);
The corresponding ksymtab entry struct `kernel_symbol` will have the member The corresponding ksymtab entry struct ``kernel_symbol`` will have the member
`namespace` set accordingly. A symbol that is exported without a namespace will ``namespace`` set accordingly. A symbol that is exported without a namespace will
refer to `NULL`. There is no default namespace if none is defined. `modpost` refer to ``NULL``. There is no default namespace if none is defined. ``modpost``
and kernel/module.c make use the namespace at build time or module load time, and kernel/module.c make use the namespace at build time or module load time,
respectively. respectively.
@@ -64,7 +64,7 @@ and EXPORT_SYMBOL_GPL() macro expansions that do not specify a namespace.
There are multiple ways of specifying this define and it depends on the There are multiple ways of specifying this define and it depends on the
subsystem and the maintainer's preference, which one to use. The first option subsystem and the maintainer's preference, which one to use. The first option
is to define the default namespace in the `Makefile` of the subsystem. E.g. to is to define the default namespace in the ``Makefile`` of the subsystem. E.g. to
export all symbols defined in usb-common into the namespace USB_COMMON, add a export all symbols defined in usb-common into the namespace USB_COMMON, add a
line like this to drivers/usb/common/Makefile:: line like this to drivers/usb/common/Makefile::
@@ -96,7 +96,7 @@ using a statement like::
MODULE_IMPORT_NS(USB_STORAGE); MODULE_IMPORT_NS(USB_STORAGE);
This will create a `modinfo` tag in the module for each imported namespace. This will create a ``modinfo`` tag in the module for each imported namespace.
This has the side effect, that the imported namespaces of a module can be This has the side effect, that the imported namespaces of a module can be
inspected with modinfo:: inspected with modinfo::
@@ -113,7 +113,7 @@ metadata definitions like MODULE_AUTHOR() or MODULE_LICENSE(). Refer to section
4. Loading Modules that use namespaced Symbols 4. Loading Modules that use namespaced Symbols
============================================== ==============================================
At module loading time (e.g. `insmod`), the kernel will check each symbol At module loading time (e.g. ``insmod``), the kernel will check each symbol
referenced from the module for its availability and whether the namespace it referenced from the module for its availability and whether the namespace it
might be exported to has been imported by the module. The default behaviour of might be exported to has been imported by the module. The default behaviour of
the kernel is to reject loading modules that don't specify sufficient imports. the kernel is to reject loading modules that don't specify sufficient imports.
@@ -138,19 +138,19 @@ missing imports. Fixing missing imports can be done with::
A typical scenario for module authors would be:: A typical scenario for module authors would be::
- write code that depends on a symbol from a not imported namespace - write code that depends on a symbol from a not imported namespace
- `make` - ``make``
- notice the warning of modpost telling about a missing import - notice the warning of modpost telling about a missing import
- run `make nsdeps` to add the import to the correct code location - run ``make nsdeps`` to add the import to the correct code location
For subsystem maintainers introducing a namespace, the steps are very similar. For subsystem maintainers introducing a namespace, the steps are very similar.
Again, `make nsdeps` will eventually add the missing namespace imports for Again, ``make nsdeps`` will eventually add the missing namespace imports for
in-tree modules:: in-tree modules::
- move or add symbols to a namespace (e.g. with EXPORT_SYMBOL_NS()) - move or add symbols to a namespace (e.g. with EXPORT_SYMBOL_NS())
- `make` (preferably with an allmodconfig to cover all in-kernel - ``make`` (preferably with an allmodconfig to cover all in-kernel
modules) modules)
- notice the warning of modpost telling about a missing import - notice the warning of modpost telling about a missing import
- run `make nsdeps` to add the import to the correct code location - run ``make nsdeps`` to add the import to the correct code location
You can also run nsdeps for external module builds. A typical usage is:: You can also run nsdeps for external module builds. A typical usage is::

2
Documentation/dev-tools/gdb-kernel-debugging.rst
View File

@@ -114,7 +114,7 @@ Examples of using the Linux-provided gdb helpers
[ 0.000000] BIOS-e820: [mem 0x000000000009fc00-0x000000000009ffff] reserved [ 0.000000] BIOS-e820: [mem 0x000000000009fc00-0x000000000009ffff] reserved
.... ....
- Examine fields of the current task struct:: - Examine fields of the current task struct(supported by x86 and arm64 only)::
(gdb) p $lx_current().pid (gdb) p $lx_current().pid
$1 = 4998 $1 = 4998

2
Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml
View File

@@ -109,7 +109,7 @@ required:
- resets - resets
- ddc - ddc
unevaluatedProperties: false additionalProperties: false
examples: examples:
- | - |

3
Documentation/devicetree/bindings/display/renesas,du.yaml
View File

@@ -51,6 +51,9 @@ properties:
resets: true resets: true
reset-names: true reset-names: true
power-domains:
maxItems: 1
ports: ports:
$ref: /schemas/graph.yaml#/properties/port $ref: /schemas/graph.yaml#/properties/port
description: | description: |

1
Documentation/devicetree/bindings/dma/qcom,gpi.yaml
View File

@@ -20,6 +20,7 @@ properties:
compatible: compatible:
enum: enum:
- qcom,sdm845-gpi-dma - qcom,sdm845-gpi-dma
- qcom,sm8150-gpi-dma
reg: reg:
maxItems: 1 maxItems: 1

77
Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml Normal file
View File

@@ -0,0 +1,77 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/fairchild,74hc595.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Generic 8-bit shift register
maintainers:
- Maxime Ripard <mripard@kernel.org>
properties:
compatible:
enum:
- fairchild,74hc595
- nxp,74lvc594
reg:
maxItems: 1
gpio-controller: true
'#gpio-cells':
description:
The second cell is only used to specify the GPIO polarity.
const: 2
registers-number:
description: Number of daisy-chained shift registers
enable-gpios:
description: GPIO connected to the OE (Output Enable) pin.
maxItems: 1
spi-max-frequency: true
patternProperties:
"^(hog-[0-9]+|.+-hog(-[0-9]+)?)$":
type: object
properties:
gpio-hog: true
gpios: true
output-high: true
output-low: true
line-name: true
required:
- gpio-hog
- gpios
additionalProperties: false
required:
- compatible
- reg
- gpio-controller
- '#gpio-cells'
- registers-number
additionalProperties: false
examples:
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
gpio5: gpio5@0 {
compatible = "fairchild,74hc595";
reg = <0>;
gpio-controller;
#gpio-cells = <2>;
registers-number = <4>;
spi-max-frequency = <100000>;
};
};

27
Documentation/devicetree/bindings/gpio/gpio-74x164.txt
View File

@@ -1,27 +0,0 @@
* Generic 8-bits shift register GPIO driver
Required properties:
- compatible: Should contain one of the following:
"fairchild,74hc595"
"nxp,74lvc594"
- reg : chip select number
- gpio-controller : Marks the device node as a gpio controller.
- #gpio-cells : Should be two. The first cell is the pin number and
the second cell is used to specify the gpio polarity:
0 = active high
1 = active low
- registers-number: Number of daisy-chained shift registers
Optional properties:
- enable-gpios: GPIO connected to the OE (Output Enable) pin.
Example:
gpio5: gpio5@0 {
compatible = "fairchild,74hc595";
reg = <0>;
gpio-controller;
#gpio-cells = <2>;
registers-number = <4>;
spi-max-frequency = <100000>;
};

78
Documentation/devicetree/bindings/gpio/realtek,otto-gpio.yaml Normal file
View File

@@ -0,0 +1,78 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/realtek,otto-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Realtek Otto GPIO controller
maintainers:
- Sander Vanheule <sander@svanheule.net>
- Bert Vermeulen <bert@biot.com>
description: |
Realtek's GPIO controller on their MIPS switch SoCs (Otto platform) consists
of two banks of 32 GPIOs. These GPIOs can generate edge-triggered interrupts.
Each bank's interrupts are cascased into one interrupt line on the parent
interrupt controller, if provided.
This binding allows defining a single bank in the devicetree. The interrupt
controller is not supported on the fallback compatible name, which only
allows for GPIO port use.
properties:
$nodename:
pattern: "^gpio@[0-9a-f]+$"
compatible:
items:
- enum:
- realtek,rtl8380-gpio
- realtek,rtl8390-gpio
- const: realtek,otto-gpio
reg:
maxItems: 1
"#gpio-cells":
const: 2
gpio-controller: true
ngpios:
minimum: 1
maximum: 32
interrupt-controller: true
"#interrupt-cells":
const: 2
interrupts:
maxItems: 1
required:
- compatible
- reg
- "#gpio-cells"
- gpio-controller
additionalProperties: false
dependencies:
interrupt-controller: [ interrupts ]
examples:
- |
gpio@3500 {
compatible = "realtek,rtl8380-gpio", "realtek,otto-gpio";
reg = <0x3500 0x1c>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <24>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&rtlintc>;
interrupts = <23>;
};
...

82
Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml Normal file
View File

@@ -0,0 +1,82 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/rockchip,gpio-bank.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip GPIO bank
maintainers:
- Heiko Stuebner <heiko@sntech.de>
properties:
compatible:
enum:
- rockchip,gpio-bank
- rockchip,rk3188-gpio-bank0
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
gpio-controller: true
"#gpio-cells":
const: 2
interrupt-controller: true
"#interrupt-cells":
const: 2
required:
- compatible
- reg
- interrupts
- clocks
- gpio-controller
- "#gpio-cells"
- interrupt-controller
- "#interrupt-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
pinctrl: pinctrl {
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio0: gpio@2000a000 {
compatible = "rockchip,rk3188-gpio-bank0";
reg = <0x2000a000 0x100>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates8 9>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio@2003c000 {
compatible = "rockchip,gpio-bank";
reg = <0x2003c000 0x100>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates8 10>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};

28
Documentation/devicetree/bindings/hwlock/sirf,hwspinlock.txt
View File

@@ -1,28 +0,0 @@
SIRF Hardware spinlock device Binding
-----------------------------------------------
Required properties :
- compatible : shall contain only one of the following:
"sirf,hwspinlock"
- reg : the register address of hwspinlock
- #hwlock-cells : hwlock users only use the hwlock id to represent a specific
hwlock, so the number of cells should be <1> here.
Please look at the generic hwlock binding for usage information for consumers,
"Documentation/devicetree/bindings/hwlock/hwlock.txt"
Example of hwlock provider:
hwlock {
compatible = "sirf,hwspinlock";
reg = <0x13240000 0x00010000>;
#hwlock-cells = <1>;
};
Example of hwlock users:
node {
...
hwlocks = <&hwlock 2>;
...
};

2
Documentation/devicetree/bindings/i3c/silvaco,i3c-master.yaml
View File

@@ -49,7 +49,7 @@ additionalProperties: true
examples: examples:
- | - |
i3c-master@a0000000 { i3c-master@a0000000 {
compatible = "silvaco,i3c-master"; compatible = "silvaco,i3c-master-v1";
clocks = <&zynqmp_clk 71>, <&fclk>, <&sclk>; clocks = <&zynqmp_clk 71>, <&fclk>, <&sclk>;
clock-names = "pclk", "fast_clk", "slow_clk"; clock-names = "pclk", "fast_clk", "slow_clk";
interrupt-parent = <&gic>; interrupt-parent = <&gic>;

32
Documentation/devicetree/bindings/input/atmel,maxtouch.yaml
View File

@@ -39,6 +39,13 @@ properties:
(active low). The line must be flagged with (active low). The line must be flagged with
GPIO_ACTIVE_LOW. GPIO_ACTIVE_LOW.
wake-gpios:
maxItems: 1
description:
Optional GPIO specifier for the touchscreen's wake pin
(active low). The line must be flagged with
GPIO_ACTIVE_LOW.
linux,gpio-keymap: linux,gpio-keymap:
$ref: /schemas/types.yaml#/definitions/uint32-array $ref: /schemas/types.yaml#/definitions/uint32-array
description: | description: |
@@ -53,6 +60,29 @@ properties:
or experiment to determine which bit corresponds to which input. Use or experiment to determine which bit corresponds to which input. Use
KEY_RESERVED for unused padding values. KEY_RESERVED for unused padding values.
atmel,wakeup-method:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
The WAKE line is an active-low input that is used to wake up the touch
controller from deep-sleep mode before communication with the controller
could be started. This optional feature used to minimize current
consumption when the controller is in deep sleep mode. This feature is
relevant only to some controller families, like mXT1386 controller for
example.
The WAKE pin can be connected in one of the following ways:
1) left permanently low
2) connected to the I2C-compatible SCL pin
3) connected to a GPIO pin on the host
enum:
- 0 # ATMEL_MXT_WAKEUP_NONE
- 1 # ATMEL_MXT_WAKEUP_I2C_SCL
- 2 # ATMEL_MXT_WAKEUP_GPIO
default: 0
wakeup-source:
type: boolean
required: required:
- compatible - compatible
- reg - reg
@@ -63,6 +93,7 @@ additionalProperties: false
examples: examples:
- | - |
#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/input/atmel-maxtouch.h>
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
i2c { i2c {
#address-cells = <1>; #address-cells = <1>;
@@ -75,6 +106,7 @@ examples:
reset-gpios = <&gpio 27 GPIO_ACTIVE_LOW>; reset-gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
vdda-supply = <&ab8500_ldo_aux2_reg>; vdda-supply = <&ab8500_ldo_aux2_reg>;
vdd-supply = <&ab8500_ldo_aux5_reg>; vdd-supply = <&ab8500_ldo_aux5_reg>;
atmel,wakeup-method = <ATMEL_MXT_WAKEUP_I2C_SCL>;
}; };
}; };

843
Documentation/devicetree/bindings/input/iqs626a.yaml Normal file
View File

@@ -0,0 +1,843 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/input/iqs626a.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Azoteq IQS626A Capacitive Touch Controller
maintainers:
- Jeff LaBundy <jeff@labundy.com>
description: |
The Azoteq IQS626A is a 14-channel capacitive touch controller that features
additional Hall-effect and inductive sensing capabilities.
Link to datasheet: https://www.azoteq.com/
allOf:
- $ref: touchscreen/touchscreen.yaml#
properties:
compatible:
const: azoteq,iqs626a
reg:
maxItems: 1
interrupts:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 0
azoteq,suspend-mode:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
default: 0
description: |
Specifies the power mode during suspend as follows:
0: Automatic (same as normal runtime, i.e. suspend/resume disabled)
1: Low power (all sensing at a reduced reporting rate)
2: Ultra-low power (ULP channel proximity sensing)
3: Halt (no sensing)
azoteq,clk-div:
type: boolean
description: Divides the device's core clock by a factor of 4.
azoteq,ulp-enable:
type: boolean
description:
Permits the device to automatically enter ultra-low-power mode from low-
power mode.
azoteq,ulp-update:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3, 4, 5, 6, 7]
default: 3
description: |
Specifies the rate at which the trackpad, generic and Hall channels are
updated during ultra-low-power mode as follows:
0: 8
1: 13
2: 28
3: 54
4: 89
5: 135
6: 190
7: 256
azoteq,ati-band-disable:
type: boolean
description: Disables the ATI band check.
azoteq,ati-lp-only:
type: boolean
description: Limits automatic ATI to low-power mode.
azoteq,gpio3-select:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3, 4, 5, 6, 7]
default: 1
description: |
Selects the channel or group of channels for which the GPIO3 pin
represents touch state as follows:
0: None
1: ULP channel
2: Trackpad
3: Trackpad
4: Generic channel 0
5: Generic channel 1
6: Generic channel 2
7: Hall channel
azoteq,reseed-select:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
default: 0
description: |
Specifies the event(s) that prompt the device to reseed (i.e. reset the
long-term average) of an associated channel as follows:
0: None
1: Proximity
2: Proximity or touch
3: Proximity, touch or deep touch
azoteq,thresh-extend:
type: boolean
description: Multiplies all touch and deep-touch thresholds by 4.
azoteq,tracking-enable:
type: boolean
description:
Enables all associated channels to track their respective reference
channels.
azoteq,reseed-offset:
type: boolean
description:
Applies an 8-count offset to all long-term averages upon either ATI or
reseed events.
azoteq,rate-np-ms:
minimum: 0
maximum: 255
default: 150
description: Specifies the report rate (in ms) during normal-power mode.
azoteq,rate-lp-ms:
minimum: 0
maximum: 255
default: 150
description: Specifies the report rate (in ms) during low-power mode.
azoteq,rate-ulp-ms:
multipleOf: 16
minimum: 0
maximum: 4080
default: 0
description: Specifies the report rate (in ms) during ultra-low-power mode.
azoteq,timeout-pwr-ms:
multipleOf: 512
minimum: 0
maximum: 130560
default: 2560
description:
Specifies the length of time (in ms) to wait for an event before moving
from normal-power mode to low-power mode, or (if 'azoteq,ulp-enable' is
present) from low-power mode to ultra-low-power mode.
azoteq,timeout-lta-ms:
multipleOf: 512
minimum: 0
maximum: 130560
default: 40960
description:
Specifies the length of time (in ms) to wait before resetting the long-
term average of all channels. Specify the maximum timeout to disable it
altogether.
touchscreen-inverted-x: true
touchscreen-inverted-y: true
touchscreen-swapped-x-y: true
patternProperties:
"^ulp-0|generic-[0-2]|hall$":
type: object
description:
Represents a single sensing channel. A channel is active if defined and
inactive otherwise.
properties:
azoteq,ati-exclude:
type: boolean
description:
Prevents the channel from participating in an ATI event that is
manually triggered during initialization.
azoteq,reseed-disable:
type: boolean
description:
Prevents the channel from being reseeded if the long-term average
timeout (defined in 'azoteq,timeout-lta') expires.
azoteq,meas-cap-decrease:
type: boolean
description:
Decreases the internal measurement capacitance from 60 pF to 15 pF.
azoteq,rx-inactive:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2]
default: 0
description: |
Specifies how inactive CRX pins are to be terminated as follows:
0: VSS
1: Floating
2: VREG (generic channels only)
azoteq,linearize:
type: boolean
description:
Enables linearization of the channel's counts (generic and Hall
channels) or inverts the polarity of the channel's proximity or
touch states (ULP channel).
azoteq,dual-direction:
type: boolean
description:
Specifies that the channel's long-term average is to freeze in the
presence of either increasing or decreasing counts, thereby permit-
ting events to be reported in either direction.
azoteq,filt-disable:
type: boolean
description: Disables raw count filtering for the channel.
azoteq,ati-mode:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
description: |
Specifies the channel's ATI mode as follows:
0: Disabled
1: Semi-partial
2: Partial
3: Full
The default value is a function of the channel and the device's reset
user interface (RUI); reference the datasheet for further information
about the available RUI options.
azoteq,ati-base:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [75, 100, 150, 200]
description:
Specifies the channel's ATI base. The default value is a function
of the channel and the device's RUI.
azoteq,ati-target:
$ref: /schemas/types.yaml#/definitions/uint32
multipleOf: 32
minimum: 0
maximum: 2016
description:
Specifies the channel's ATI target. The default value is a function
of the channel and the device's RUI.
azoteq,cct-increase:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 16
default: 0
description:
Specifies the degree to which the channel's charge cycle time is to
be increased, with 0 representing no increase. The maximum value is
limited to 4 in the case of the ULP channel, and the property is un-
available entirely in the case of the Hall channel.
azoteq,proj-bias:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
default: 0
description: |
Specifies the bias current applied during projected-capacitance
sensing as follows:
0: 2.5 uA
1: 5 uA
2: 10 uA
3: 20 uA
This property is unavailable in the case of the Hall channel.
azoteq,sense-freq:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
description: |
Specifies the channel's sensing frequency as follows (parenthesized
numbers represent the frequency if 'azoteq,clk-div' is present):
0: 4 MHz (1 MHz)
1: 2 MHz (500 kHz)
2: 1 MHz (250 kHz)
3: 500 kHz (125 kHz)
This property is unavailable in the case of the Hall channel. The
default value is a function of the channel and the device's RUI.
azoteq,ati-band-tighten:
type: boolean
description:
Tightens the ATI band from 1/8 to 1/16 of the desired target (ULP and
generic channels only).
azoteq,proj-enable:
type: boolean
description: Enables projected-capacitance sensing (ULP channel only).
azoteq,filt-str-np-cnt:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
default: 0
description:
Specifies the raw count filter strength during normal-power mode (ULP
and generic channels only).
azoteq,filt-str-lp-cnt:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
default: 0
description:
Specifies the raw count filter strength during low-power mode (ULP and
generic channels only).
azoteq,filt-str-np-lta:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
default: 0
description:
Specifies the long-term average filter strength during normal-power
mode (ULP and generic channels only).
azoteq,filt-str-lp-lta:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
default: 0
description:
Specifies the long-term average filter strength during low-power mode
(ULP and generic channels only).
azoteq,rx-enable:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 8
items:
minimum: 0
maximum: 7
description:
Specifies the CRX pin(s) associated with the channel.
This property is unavailable in the case of the Hall channel. The
default value is a function of the channel and the device's RUI.
azoteq,tx-enable:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 8
items:
minimum: 0
maximum: 7
description:
Specifies the TX pin(s) associated with the channel.
This property is unavailable in the case of the Hall channel. The
default value is a function of the channel and the device's RUI.
azoteq,local-cap-size:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3, 4]
default: 0
description: |
Specifies the capacitance to be added to the channel as follows:
0: 0 pF
1: 0.5 pF
2: 1.0 pF
3: 1.5 pF
4: 2.0 pF
This property is unavailable in the case of the ULP or Hall channels.
azoteq,sense-mode:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 8, 9, 12, 14, 15]
description: |
Specifies the channel's sensing mode as follows:
0: Self capacitance
1: Projected capacitance
8: Self inductance
9: Mutual inductance
12: External
14: Hall effect
15: Temperature
This property is unavailable in the case of the ULP or Hall channels.
The default value is a function of the channel and the device's RUI.
azoteq,tx-freq:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
default: 0
description: |
Specifies the inductive sensing excitation frequency as follows
(parenthesized numbers represent the frequency if 'azoteq,clk-div'
is present):
0: 16 MHz (4 MHz)
1: 8 MHz (2 MHz)
2: 4 MHz (1 MHz)
3: 2 MHz (500 kHz)
This property is unavailable in the case of the ULP or Hall channels.
azoteq,invert-enable:
type: boolean
description:
Inverts the polarity of the states reported for proximity, touch and
deep-touch events relative to their respective thresholds (generic
channels only).
azoteq,comp-disable:
type: boolean
description:
Disables compensation for the channel (generic channels only).
azoteq,static-enable:
type: boolean
description:
Enables the static front-end for the channel (generic channels only).
azoteq,assoc-select:
$ref: /schemas/types.yaml#/definitions/string-array
minItems: 1
maxItems: 6
items:
enum:
- ulp-0
- trackpad-3x2
- trackpad-3x3
- generic-0
- generic-1
- generic-2
- hall
description:
Specifies the associated channels for which the channel serves as a
reference channel. By default, no channels are selected. This prop-
erty is only available for the generic channels.
azoteq,assoc-weight:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 255
default: 0
description:
Specifies the channel's impact weight if it acts as an associated
channel (0 = 0% impact, 255 = 200% impact). This property is only
available for the generic channels.
patternProperties:
"^event-(prox|touch|deep)(-alt)?$":
type: object
description:
Represents a proximity, touch or deep-touch event reported by the
channel in response to a decrease in counts. Node names suffixed with
'-alt' instead correspond to an increase in counts.
By default, the long-term average tracks an increase in counts such
that only events corresponding to a decrease in counts are reported
(refer to the datasheet for more information).
Specify 'azoteq,dual-direction' to freeze the long-term average when
the counts increase or decrease such that events of either direction
can be reported. Alternatively, specify 'azoteq,invert-enable' to in-
vert the polarity of the states reported by the channel.
Complementary events (e.g. event-touch and event-touch-alt) can both
be present and specify different key or switch codes, but not differ-
ent thresholds or hysteresis (if applicable).
Proximity events are unavailable in the case of the Hall channel, and
deep-touch events are only available for the generic channels. Unless
otherwise specified, default values are a function of the channel and
the device's RUI.
properties:
azoteq,thresh:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 255
description: Specifies the threshold for the event.
azoteq,hyst:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 15
description:
Specifies the hysteresis for the event (touch and deep-touch
events only).
linux,code:
$ref: /schemas/types.yaml#/definitions/uint32
description: Numeric key or switch code associated with the event.
linux,input-type:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [1, 5]
description:
Specifies whether the event is to be interpreted as a key (1) or
a switch (5). By default, Hall-channel events are interpreted as
switches and all others are interpreted as keys.
dependencies:
linux,input-type: ["linux,code"]
additionalProperties: false
dependencies:
azoteq,assoc-weight: ["azoteq,assoc-select"]
additionalProperties: false
"^trackpad-3x[2-3]$":
type: object
description:
Represents all channels associated with the trackpad. The channels are
collectively active if the trackpad is defined and inactive otherwise.
properties:
azoteq,ati-exclude:
type: boolean
description:
Prevents the trackpad channels from participating in an ATI event
that is manually triggered during initialization.
azoteq,reseed-disable:
type: boolean
description:
Prevents the trackpad channels from being reseeded if the long-term
average timeout (defined in 'azoteq,timeout-lta') expires.
azoteq,meas-cap-decrease:
type: boolean
description:
Decreases the internal measurement capacitance from 60 pF to 15 pF.
azoteq,rx-inactive:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
default: 0
description: |
Specifies how inactive CRX pins are to be terminated as follows:
0: VSS
1: Floating
azoteq,linearize:
type: boolean
description: Inverts the polarity of the trackpad's touch state.
azoteq,dual-direction:
type: boolean
description:
Specifies that the trackpad's long-term averages are to freeze in
the presence of either increasing or decreasing counts, thereby
permitting events to be reported in either direction.
azoteq,filt-disable:
type: boolean
description: Disables raw count filtering for the trackpad channels.
azoteq,ati-mode:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
default: 0
description: |
Specifies the trackpad's ATI mode as follows:
0: Disabled
1: Semi-partial
2: Partial
3: Full
azoteq,ati-base:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 6
maxItems: 9
items:
minimum: 45
maximum: 300
default: [45, 45, 45, 45, 45, 45, 45, 45, 45]
description: Specifies each individual trackpad channel's ATI base.
azoteq,ati-target:
$ref: /schemas/types.yaml#/definitions/uint32
multipleOf: 32
minimum: 0
maximum: 2016
default: 0
description: Specifies the trackpad's ATI target.
azoteq,cct-increase:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 4
default: 0
description:
Specifies the degree to which the trackpad's charge cycle time is to
be increased, with 0 representing no increase.
azoteq,proj-bias:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
default: 0
description: |
Specifies the bias current applied during projected-capacitance
sensing as follows:
0: 2.5 uA
1: 5 uA
2: 10 uA
3: 20 uA
azoteq,sense-freq:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
default: 0
description: |
Specifies the trackpad's sensing frequency as follows (parenthesized
numbers represent the frequency if 'azoteq,clk-div' is present):
0: 4 MHz (1 MHz)
1: 2 MHz (500 kHz)
2: 1 MHz (250 kHz)
3: 500 kHz (125 kHz)
azoteq,ati-band-tighten:
type: boolean
description:
Tightens the ATI band from 1/8 to 1/16 of the desired target.
azoteq,thresh:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 6
maxItems: 9
items:
minimum: 0
maximum: 255
default: [0, 0, 0, 0, 0, 0, 0, 0, 0]
description:
Specifies each individual trackpad channel's touch threshold.
azoteq,hyst:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 15
default: 0
description: Specifies the trackpad's touch hysteresis.
azoteq,lta-update:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3, 4, 5, 6, 7]
default: 0
description: |
Specifies the update rate of the trackpad's long-term average during
ultra-low-power mode as follows:
0: 2
1: 4
2: 8
3: 16
4: 32
5: 64
6: 128
7: 255
azoteq,filt-str-trackpad:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
default: 0
description: Specifies the trackpad coordinate filter strength.
azoteq,filt-str-np-cnt:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
default: 0
description:
Specifies the raw count filter strength during normal-power mode.
azoteq,filt-str-lp-cnt:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
default: 0
description:
Specifies the raw count filter strength during low-power mode.
linux,keycodes:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 6
description: |
Specifies the numeric keycodes associated with each available gesture
in the following order (enter 0 for unused gestures):
0: Positive flick or swipe in X direction
1: Negative flick or swipe in X direction
2: Positive flick or swipe in Y direction
3: Negative flick or swipe in Y direction
4: Tap
5: Hold
azoteq,gesture-swipe:
type: boolean
description:
Directs the device to interpret axial gestures as a swipe (finger
remains on trackpad) instead of a flick (finger leaves trackpad).
azoteq,timeout-tap-ms:
multipleOf: 16
minimum: 0
maximum: 4080
default: 0
description:
Specifies the length of time (in ms) within which a trackpad touch
must be released in order to be interpreted as a tap.
azoteq,timeout-swipe-ms:
multipleOf: 16
minimum: 0
maximum: 4080
default: 0
description:
Specifies the length of time (in ms) within which an axial gesture
must be completed in order to be interpreted as a flick or swipe.
azoteq,thresh-swipe:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 255
default: 0
description:
Specifies the number of points across which an axial gesture must
travel in order to be interpreted as a flick or swipe.
dependencies:
azoteq,gesture-swipe: ["linux,keycodes"]
azoteq,timeout-tap-ms: ["linux,keycodes"]
azoteq,timeout-swipe-ms: ["linux,keycodes"]
azoteq,thresh-swipe: ["linux,keycodes"]
additionalProperties: false
required:
- compatible
- reg
- interrupts
- "#address-cells"
- "#size-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
iqs626a@44 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "azoteq,iqs626a";
reg = <0x44>;
interrupt-parent = <&gpio>;
interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
azoteq,rate-np-ms = <16>;
azoteq,rate-lp-ms = <160>;
azoteq,timeout-pwr-ms = <2560>;
azoteq,timeout-lta-ms = <32768>;
ulp-0 {
azoteq,meas-cap-decrease;
azoteq,ati-base = <75>;
azoteq,ati-target = <1024>;
azoteq,rx-enable = <2>, <3>, <4>,
<5>, <6>, <7>;
event-prox {
linux,code = <KEY_POWER>;
};
};
trackpad-3x3 {
azoteq,filt-str-np-cnt = <1>;
azoteq,filt-str-lp-cnt = <1>;
azoteq,hyst = <4>;
azoteq,thresh = <35>, <40>, <40>,
<38>, <33>, <38>,
<35>, <35>, <35>;
azoteq,ati-mode = <3>;
azoteq,ati-base = <195>, <195>, <195>,
<195>, <195>, <195>,
<195>, <195>, <195>;
azoteq,ati-target = <512>;
azoteq,proj-bias = <1>;
azoteq,sense-freq = <2>;
linux,keycodes = <KEY_VOLUMEUP>,
<KEY_VOLUMEDOWN>,
<KEY_NEXTSONG>,
<KEY_PREVIOUSSONG>,
<KEY_PLAYPAUSE>,
<KEY_STOPCD>;
azoteq,gesture-swipe;
azoteq,timeout-swipe-ms = <800>;
azoteq,timeout-tap-ms = <400>;
azoteq,thresh-swipe = <40>;
};
/*
* Preserve the default register settings for
* the temperature-tracking channel leveraged
* by reset user interface (RUI) 1.
*
* Scalar properties (e.g. ATI mode) are left
* untouched by simply omitting them; boolean
* properties must be specified explicitly as
* needed.
*/
generic-2 {
azoteq,reseed-disable;
azoteq,meas-cap-decrease;
azoteq,dual-direction;
azoteq,comp-disable;
azoteq,static-enable;
};
hall {
azoteq,reseed-disable;
azoteq,meas-cap-decrease;
event-touch {
linux,code = <SW_LID>;
};
};
};
};
...

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/input/touchscreen/azoteq,iqs5xx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Azoteq IQS550/572/525 Trackpad/Touchscreen Controller
maintainers:
- Jeff LaBundy <jeff@labundy.com>
description: |
The Azoteq IQS550, IQS572 and IQS525 trackpad and touchscreen controllers
employ projected-capacitance sensing and can track up to five independent
contacts.
Link to datasheet: https://www.azoteq.com/
allOf:
- $ref: touchscreen.yaml#
properties:
compatible:
enum:
- azoteq,iqs550
- azoteq,iqs572
- azoteq,iqs525
reg:
maxItems: 1
interrupts:
maxItems: 1
reset-gpios:
maxItems: 1
wakeup-source: true
touchscreen-size-x: true
touchscreen-size-y: true
touchscreen-inverted-x: true
touchscreen-inverted-y: true
touchscreen-swapped-x-y: true
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
touchscreen@74 {
compatible = "azoteq,iqs550";
reg = <0x74>;
interrupt-parent = <&gpio>;
interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
reset-gpios = <&gpio 22 (GPIO_ACTIVE_LOW |
GPIO_PUSH_PULL)>;
touchscreen-size-x = <800>;
touchscreen-size-y = <480>;
};
};
...

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/input/touchscreen/hycon,hy46xx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Hycon HY46XX series touchscreen controller bindings
description: |
There are 6 variants of the chip for various touch panel sizes and cover lens material
Glass: 0.3mm--4.0mm
PET/PMMA: 0.2mm--2.0mm
HY4613(B)-N048 < 6"
HY4614(B)-N068 7" .. 10.1"
HY4621-NS32 < 5"
HY4623-NS48 5.1" .. 7"
Glass: 0.3mm--8.0mm
PET/PMMA: 0.2mm--4.0mm
HY4633(B)-N048 < 6"
HY4635(B)-N048 < 7" .. 10.1"
maintainers:
- Giulio Benetti <giulio.benetti@benettiengineering.com>
allOf:
- $ref: touchscreen.yaml#
properties:
compatible:
enum:
- hycon,hy4613
- hycon,hy4614
- hycon,hy4621
- hycon,hy4623
- hycon,hy4633
- hycon,hy4635
reg:
maxItems: 1
interrupts:
maxItems: 1
reset-gpios:
maxItems: 1
vcc-supply: true
hycon,threshold:
description: Allows setting the sensitivity in the range from 0 to 255.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 255
hycon,glove-enable:
type: boolean
description: Allows enabling glove setting.
hycon,report-speed-hz:
description: Allows setting the report speed in Hertz.
minimum: 1
maximum: 255
hycon,noise-filter-enable:
type: boolean
description: Allows enabling power noise filter.
hycon,filter-data:
description: Allows setting how many samples throw before reporting touch
in the range from 0 to 5.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 5
hycon,gain:
description: Allows setting the sensitivity distance in the range from 0 to 5.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 5
hycon,edge-offset:
description: Allows setting the edge compensation in the range from 0 to 16.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 16
touchscreen-size-x: true
touchscreen-size-y: true
touchscreen-fuzz-x: true
touchscreen-fuzz-y: true
touchscreen-inverted-x: true
touchscreen-inverted-y: true
touchscreen-swapped-x-y: true
interrupt-controller: true
additionalProperties: false
required:
- compatible
- reg
- interrupts
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
touchscreen@1c {
compatible = "hycon,hy4633";
reg = <0x1c>;
interrupt-parent = <&gpio2>;
interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
};
};
...

73
Documentation/devicetree/bindings/input/touchscreen/ilitek_ts_i2c.yaml Normal file
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@@ -0,0 +1,73 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/input/touchscreen/ilitek_ts_i2c.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ilitek I2C Touchscreen Controller
maintainers:
- Dmitry Torokhov <dmitry.torokhov@gmail.com>
allOf:
- $ref: touchscreen.yaml#
properties:
compatible:
enum:
- ilitek,ili2130
- ilitek,ili2131
- ilitek,ili2132
- ilitek,ili2316
- ilitek,ili2322
- ilitek,ili2323
- ilitek,ili2326
- ilitek,ili2520
- ilitek,ili2521
reg:
const: 0x41
interrupts:
maxItems: 1
reset-gpios:
maxItems: 1
wakeup-source:
type: boolean
description: touchscreen can be used as a wakeup source.
touchscreen-size-x: true
touchscreen-size-y: true
touchscreen-inverted-x: true
touchscreen-inverted-y: true
touchscreen-swapped-x-y: true
additionalProperties: false
required:
- compatible
- reg
- interrupts
- reset-gpios
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
touchscreen@41 {
compatible = "ilitek,ili2520";
reg = <0x41>;
interrupt-parent = <&gpio1>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
touchscreen-inverted-y;
wakeup-source;
};
};

80
Documentation/devicetree/bindings/input/touchscreen/iqs5xx.txt
View File

@@ -1,80 +0,0 @@
Azoteq IQS550/572/525 Trackpad/Touchscreen Controller
Required properties:
- compatible : Must be equal to one of the following:
"azoteq,iqs550"
"azoteq,iqs572"
"azoteq,iqs525"
- reg : I2C slave address for the device.
- interrupts : GPIO to which the device's active-high RDY
output is connected (see [0]).
- reset-gpios : GPIO to which the device's active-low NRST
input is connected (see [1]).
Optional properties:
- touchscreen-min-x : See [2].
- touchscreen-min-y : See [2].
- touchscreen-size-x : See [2]. If this property is omitted, the
maximum x-coordinate is specified by the
device's "X Resolution" register.
- touchscreen-size-y : See [2]. If this property is omitted, the
maximum y-coordinate is specified by the
device's "Y Resolution" register.
- touchscreen-max-pressure : See [2]. Pressure is expressed as the sum of
the deltas across all channels impacted by a
touch event. A channel's delta is calculated
as its count value minus a reference, where
the count value is inversely proportional to
the channel's capacitance.
- touchscreen-fuzz-x : See [2].
- touchscreen-fuzz-y : See [2].
- touchscreen-fuzz-pressure : See [2].
- touchscreen-inverted-x : See [2]. Inversion is applied relative to that
which may already be specified by the device's
FLIP_X and FLIP_Y register fields.
- touchscreen-inverted-y : See [2]. Inversion is applied relative to that
which may already be specified by the device's
FLIP_X and FLIP_Y register fields.
- touchscreen-swapped-x-y : See [2]. Swapping is applied relative to that
which may already be specified by the device's
SWITCH_XY_AXIS register field.
[0]: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
[1]: Documentation/devicetree/bindings/gpio/gpio.txt
[2]: Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt
Example:
&i2c1 {
/* ... */
touchscreen@74 {
compatible = "azoteq,iqs550";
reg = <0x74>;
interrupt-parent = <&gpio>;
interrupts = <17 4>;
reset-gpios = <&gpio 27 1>;
touchscreen-size-x = <640>;
touchscreen-size-y = <480>;
touchscreen-max-pressure = <16000>;
};
/* ... */
};

87
Documentation/devicetree/bindings/input/touchscreen/melfas,mms114.yaml Normal file
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@@ -0,0 +1,87 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/input/touchscreen/melfas,mms114.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Melfas MMS114 family touchscreen controller bindings
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
allOf:
- $ref: touchscreen.yaml#
properties:
$nodename:
pattern: "^touchscreen(@.*)?$"
compatible:
items:
- enum:
- melfas,mms114
- melfas,mms134s
- melfas,mms136
- melfas,mms152
- melfas,mms345l
reg:
description: I2C address
clock-frequency:
description: I2C client clock frequency, defined for host
minimum: 100000
maximum: 400000
interrupts:
maxItems: 1
avdd-supply:
description: Analog power supply regulator on AVDD pin
vdd-supply:
description: Digital power supply regulator on VDD pin
touchscreen-size-x: true
touchscreen-size-y: true
touchscreen-fuzz-x: true
touchscreen-fuzz-y: true
touchscreen-fuzz-pressure: true
touchscreen-inverted-x: true
touchscreen-inverted-y: true
touchscreen-swapped-x-y: true
touchscreen-max-pressure: true
additionalProperties: false
required:
- compatible
- reg
- interrupts
- touchscreen-size-x
- touchscreen-size-y
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
touchscreen@48 {
compatible = "melfas,mms114";
reg = <0x48>;
interrupt-parent = <&gpio>;
interrupts = <39 IRQ_TYPE_EDGE_FALLING>;
avdd-supply = <&ldo1_reg>;
vdd-supply = <&ldo2_reg>;
touchscreen-size-x = <720>;
touchscreen-size-y = <1280>;
touchscreen-fuzz-x = <10>;
touchscreen-fuzz-y = <10>;
touchscreen-fuzz-pressure = <10>;
touchscreen-inverted-x;
touchscreen-inverted-y;
};
};
...

42
Documentation/devicetree/bindings/input/touchscreen/mms114.txt
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@@ -1,42 +0,0 @@
* MELFAS MMS114/MMS152/MMS345L touchscreen controller
Required properties:
- compatible: should be one of:
- "melfas,mms114"
- "melfas,mms152"
- "melfas,mms345l"
- reg: I2C address of the chip
- interrupts: interrupt to which the chip is connected
- touchscreen-size-x: See [1]
- touchscreen-size-y: See [1]
Optional properties:
- touchscreen-fuzz-x: See [1]
- touchscreen-fuzz-y: See [1]
- touchscreen-fuzz-pressure: See [1]
- touchscreen-inverted-x: See [1]
- touchscreen-inverted-y: See [1]
- touchscreen-swapped-x-y: See [1]
[1]: Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt
Example:
i2c@00000000 {
/* ... */
touchscreen@48 {
compatible = "melfas,mms114";
reg = <0x48>;
interrupts = <39 0>;
touchscreen-size-x = <720>;
touchscreen-size-y = <1280>;
touchscreen-fuzz-x = <10>;
touchscreen-fuzz-y = <10>;
touchscreen-fuzz-pressure = <10>;
touchscreen-inverted-x;
touchscreen-inverted-y;
};
/* ... */
};

69
Documentation/devicetree/bindings/input/touchscreen/mstar,msg2638.yaml Normal file
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@@ -0,0 +1,69 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/input/touchscreen/mstar,msg2638.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MStar msg2638 touchscreen controller Bindings
maintainers:
- Vincent Knecht <vincent.knecht@mailoo.org>
allOf:
- $ref: touchscreen.yaml#
properties:
compatible:
const: mstar,msg2638
reg:
const: 0x26
interrupts:
maxItems: 1
reset-gpios:
maxItems: 1
vdd-supply:
description: Power supply regulator for the chip
vddio-supply:
description: Power supply regulator for the I2C bus
touchscreen-size-x: true
touchscreen-size-y: true
additionalProperties: false
required:
- compatible
- reg
- interrupts
- reset-gpios
- touchscreen-size-x
- touchscreen-size-y
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
touchscreen@26 {
compatible = "mstar,msg2638";
reg = <0x26>;
interrupt-parent = <&msmgpio>;
interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&msmgpio 100 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&ts_int_reset_default>;
vdd-supply = <&pm8916_l17>;
vddio-supply = <&pm8916_l5>;
touchscreen-size-x = <2048>;
touchscreen-size-y = <2048>;
};
};
...

4
Documentation/devicetree/bindings/interrupt-controller/idt,32434-pic.yaml
View File

@@ -22,6 +22,9 @@ properties:
reg: reg:
maxItems: 1 maxItems: 1
interrupts:
maxItems: 1
interrupt-controller: true interrupt-controller: true
required: required:
@@ -29,6 +32,7 @@ required:
- compatible - compatible
- reg - reg
- interrupt-controller - interrupt-controller
- interrupts
additionalProperties: false additionalProperties: false

57
Documentation/devicetree/bindings/leds/leds-rt4505.yaml Normal file
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@@ -0,0 +1,57 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/leds/leds-rt4505.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Richtek RT4505 Single Channel LED Driver
maintainers:
- ChiYuan Huang <cy_huang@richtek.com>
description: |
The RT4505 is a flash LED driver that can support up to 375mA and 1.5A for
torch and flash mode, respectively.
The data sheet can be found at:
https://www.richtek.com/assets/product_file/RT4505/DS4505-02.pdf
properties:
compatible:
const: richtek,rt4505
reg:
description: I2C slave address of the controller.
maxItems: 1
led:
type: object
$ref: common.yaml#
required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/leds/common.h>
i2c0 {
#address-cells = <1>;
#size-cells = <0>;
led-controller@63 {
compatible = "richtek,rt4505";
reg = <0x63>;
rt4505_flash: led {
function = LED_FUNCTION_FLASH;
color = <LED_COLOR_ID_WHITE>;
led-max-microamp = <375000>;
flash-max-microamp = <1500000>;
flash-max-timeout-us = <800000>;
};
};
};

44
Documentation/devicetree/bindings/media/renesas,vin.yaml
View File

@@ -193,23 +193,35 @@ required:
- interrupts - interrupts
- clocks - clocks
- power-domains - power-domains
- resets
if: allOf:
properties: - if:
compatible: not:
contains: properties:
enum: compatible:
- renesas,vin-r8a7778 contains:
- renesas,vin-r8a7779 enum:
- renesas,rcar-gen2-vin - renesas,vin-r8a7778
then: - renesas,vin-r8a7779
required: then:
- port required:
else: - resets
required:
- renesas,id - if:
- ports properties:
compatible:
contains:
enum:
- renesas,vin-r8a7778
- renesas,vin-r8a7779
- renesas,rcar-gen2-vin
then:
required:
- port
else:
required:
- renesas,id
- ports
additionalProperties: false additionalProperties: false

38
Documentation/devicetree/bindings/mtd/tango-nand.txt
View File

@@ -1,38 +0,0 @@
Sigma Designs Tango4 NAND Flash Controller (NFC)
Required properties:
- compatible: "sigma,smp8758-nand"
- reg: address/size of nfc_reg, nfc_mem, and pbus_reg
- dmas: reference to the DMA channel used by the controller
- dma-names: "rxtx"
- clocks: reference to the system clock
- #address-cells: <1>
- #size-cells: <0>
Children nodes represent the available NAND chips.
See Documentation/devicetree/bindings/mtd/nand-controller.yaml for generic bindings.
Example:
nandc: nand-controller@2c000 {
compatible = "sigma,smp8758-nand";
reg = <0x2c000 0x30>, <0x2d000 0x800>, <0x20000 0x1000>;
dmas = <&dma0 3>;
dma-names = "rxtx";
clocks = <&clkgen SYS_CLK>;
#address-cells = <1>;
#size-cells = <0>;
nand@0 {
reg = <0>; /* CS0 */
nand-ecc-strength = <14>;
nand-ecc-step-size = <1024>;
};
nand@1 {
reg = <1>; /* CS1 */
nand-ecc-strength = <14>;
nand-ecc-step-size = <1024>;
};
};

2
Documentation/devicetree/bindings/net/renesas,etheravb.yaml
View File

@@ -51,12 +51,12 @@ properties:
clocks: clocks:
minItems: 1 minItems: 1
maxItems: 2
items: items:
- description: AVB functional clock - description: AVB functional clock
- description: Optional TXC reference clock - description: Optional TXC reference clock
clock-names: clock-names:
minItems: 1
items: items:
- const: fck - const: fck
- const: refclk - const: refclk

43
Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
View File

@@ -1,43 +0,0 @@
HiSilicon Hip05 and Hip06 PCIe host bridge DT description
HiSilicon PCIe host controller is based on the Synopsys DesignWare PCI core.
It shares common functions with the PCIe DesignWare core driver and inherits
common properties defined in
Documentation/devicetree/bindings/pci/designware-pcie.txt.
Additional properties are described here:
Required properties
- compatible: Should contain "hisilicon,hip05-pcie" or "hisilicon,hip06-pcie".
- reg: Should contain rc_dbi, config registers location and length.
- reg-names: Must include the following entries:
"rc_dbi": controller configuration registers;
"config": PCIe configuration space registers.
- msi-parent: Should be its_pcie which is an ITS receiving MSI interrupts.
- port-id: Should be 0, 1, 2 or 3.
Optional properties:
- status: Either "ok" or "disabled".
- dma-coherent: Present if DMA operations are coherent.
Hip05 Example (note that Hip06 is the same except compatible):
pcie@b0080000 {
compatible = "hisilicon,hip05-pcie", "snps,dw-pcie";
reg = <0 0xb0080000 0 0x10000>, <0x220 0x00000000 0 0x2000>;
reg-names = "rc_dbi", "config";
bus-range = <0 15>;
msi-parent = <&its_pcie>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
ranges = <0x82000000 0 0x00000000 0x220 0x00000000 0 0x10000000>;
num-lanes = <8>;
port-id = <1>;
#interrupt-cells = <1>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <0x0 0 0 1 &mbigen_pcie 1 10
0x0 0 0 2 &mbigen_pcie 2 11
0x0 0 0 3 &mbigen_pcie 3 12
0x0 0 0 4 &mbigen_pcie 4 13>;
};

181
Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml Normal file
View File

@@ -0,0 +1,181 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Gen3 PCIe controller on MediaTek SoCs
maintainers:
- Jianjun Wang <jianjun.wang@mediatek.com>
description: |+
PCIe Gen3 MAC controller for MediaTek SoCs, it supports Gen3 speed
and compatible with Gen2, Gen1 speed.
This PCIe controller supports up to 256 MSI vectors, the MSI hardware
block diagram is as follows:
+-----+
| GIC |
+-----+
^
|
port->irq
|
+-+-+-+-+-+-+-+-+
|0|1|2|3|4|5|6|7| (PCIe intc)
+-+-+-+-+-+-+-+-+
^ ^ ^
| | ... |
+-------+ +------+ +-----------+
| | |
+-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+
|0|1|...|30|31| |0|1|...|30|31| |0|1|...|30|31| (MSI sets)
+-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+
^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^
| | | | | | | | | | | | (MSI vectors)
| | | | | | | | | | | |
(MSI SET0) (MSI SET1) ... (MSI SET7)
With 256 MSI vectors supported, the MSI vectors are composed of 8 sets,
each set has its own address for MSI message, and supports 32 MSI vectors
to generate interrupt.
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
properties:
compatible:
const: mediatek,mt8192-pcie
reg:
maxItems: 1
reg-names:
items:
- const: pcie-mac
interrupts:
maxItems: 1
ranges:
minItems: 1
maxItems: 8
resets:
minItems: 1
maxItems: 2
reset-names:
minItems: 1
maxItems: 2
items:
- const: phy
- const: mac
clocks:
maxItems: 6
clock-names:
items:
- const: pl_250m
- const: tl_26m
- const: tl_96m
- const: tl_32k
- const: peri_26m
- const: top_133m
assigned-clocks:
maxItems: 1
assigned-clock-parents:
maxItems: 1
phys:
maxItems: 1
'#interrupt-cells':
const: 1
interrupt-controller:
description: Interrupt controller node for handling legacy PCI interrupts.
type: object
properties:
'#address-cells':
const: 0
'#interrupt-cells':
const: 1
interrupt-controller: true
required:
- '#address-cells'
- '#interrupt-cells'
- interrupt-controller
additionalProperties: false
required:
- compatible
- reg
- reg-names
- interrupts
- ranges
- clocks
- '#interrupt-cells'
- interrupt-controller
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
bus {
#address-cells = <2>;
#size-cells = <2>;
pcie: pcie@11230000 {
compatible = "mediatek,mt8192-pcie";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
reg = <0x00 0x11230000 0x00 0x4000>;
reg-names = "pcie-mac";
interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
bus-range = <0x00 0xff>;
ranges = <0x82000000 0x00 0x12000000 0x00
0x12000000 0x00 0x1000000>;
clocks = <&infracfg 44>,
<&infracfg 40>,
<&infracfg 43>,
<&infracfg 97>,
<&infracfg 99>,
<&infracfg 111>;
clock-names = "pl_250m", "tl_26m", "tl_96m",
"tl_32k", "peri_26m", "top_133m";
assigned-clocks = <&topckgen 50>;
assigned-clock-parents = <&topckgen 91>;
phys = <&pciephy>;
phy-names = "pcie-phy";
resets = <&infracfg_rst 2>,
<&infracfg_rst 3>;
reset-names = "phy", "mac";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &pcie_intc 0>,
<0 0 0 2 &pcie_intc 1>,
<0 0 0 3 &pcie_intc 2>,
<0 0 0 4 &pcie_intc 3>;
pcie_intc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
};
};
};

12
Documentation/devicetree/bindings/pci/rcar-pci-host.yaml
View File

@@ -17,6 +17,7 @@ allOf:
properties: properties:
compatible: compatible:
oneOf: oneOf:
- const: renesas,pcie-r8a7779 # R-Car H1
- items: - items:
- enum: - enum:
- renesas,pcie-r8a7742 # RZ/G1H - renesas,pcie-r8a7742 # RZ/G1H
@@ -74,7 +75,16 @@ required:
- clocks - clocks
- clock-names - clock-names
- power-domains - power-domains
- resets
if:
not:
properties:
compatible:
contains:
const: renesas,pcie-r8a7779
then:
required:
- resets
unevaluatedProperties: false unevaluatedProperties: false

113
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml Normal file
View File

@@ -0,0 +1,113 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/sifive,fu740-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SiFive FU740 PCIe host controller
description: |+
SiFive FU740 PCIe host controller is based on the Synopsys DesignWare
PCI core. It shares common features with the PCIe DesignWare core and
inherits common properties defined in
Documentation/devicetree/bindings/pci/designware-pcie.txt.
maintainers:
- Paul Walmsley <paul.walmsley@sifive.com>
- Greentime Hu <greentime.hu@sifive.com>
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
properties:
compatible:
const: sifive,fu740-pcie
reg:
maxItems: 3
reg-names:
items:
- const: dbi
- const: config
- const: mgmt
num-lanes:
const: 8
msi-parent: true
interrupt-names:
items:
- const: msi
- const: inta
- const: intb
- const: intc
- const: intd
resets:
description: A phandle to the PCIe power up reset line.
maxItems: 1
pwren-gpios:
description: Should specify the GPIO for controlling the PCI bus device power on.
maxItems: 1
reset-gpios:
maxItems: 1
required:
- dma-coherent
- num-lanes
- interrupts
- interrupt-names
- interrupt-parent
- interrupt-map-mask
- interrupt-map
- clock-names
- clocks
- resets
- pwren-gpios
- reset-gpios
unevaluatedProperties: false
examples:
- |
bus {
#address-cells = <2>;
#size-cells = <2>;
#include <dt-bindings/clock/sifive-fu740-prci.h>
pcie@e00000000 {
compatible = "sifive,fu740-pcie";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
reg = <0xe 0x00000000 0x0 0x80000000>,
<0xd 0xf0000000 0x0 0x10000000>,
<0x0 0x100d0000 0x0 0x1000>;
reg-names = "dbi", "config", "mgmt";
device_type = "pci";
dma-coherent;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000>, /* I/O */
<0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000>, /* mem */
<0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000>, /* mem */
<0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */
num-lanes = <0x8>;
interrupts = <56>, <57>, <58>, <59>, <60>, <61>, <62>, <63>, <64>;
interrupt-names = "msi", "inta", "intb", "intc", "intd";
interrupt-parent = <&plic0>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>,
<0x0 0x0 0x0 0x2 &plic0 58>,
<0x0 0x0 0x0 0x3 &plic0 59>,
<0x0 0x0 0x0 0x4 &plic0 60>;
clock-names = "pcie_aux";
clocks = <&prci PRCI_CLK_PCIE_AUX>;
resets = <&prci 4>;
pwren-gpios = <&gpio 5 0>;
reset-gpios = <&gpio 8 0>;
};
};

29
Documentation/devicetree/bindings/pci/tango-pcie.txt
View File

@@ -1,29 +0,0 @@
Sigma Designs Tango PCIe controller
Required properties:
- compatible: "sigma,smp8759-pcie"
- reg: address/size of PCI configuration space, address/size of register area
- bus-range: defined by size of PCI configuration space
- device_type: "pci"
- #size-cells: <2>
- #address-cells: <3>
- msi-controller
- ranges: translation from system to bus addresses
- interrupts: spec for misc interrupts, spec for MSI
Example:
pcie@2e000 {
compatible = "sigma,smp8759-pcie";
reg = <0x50000000 0x400000>, <0x2e000 0x100>;
bus-range = <0 3>;
device_type = "pci";
#size-cells = <2>;
#address-cells = <3>;
msi-controller;
ranges = <0x02000000 0x0 0x00400000 0x50400000 0x0 0x3c00000>;
interrupts =
<54 IRQ_TYPE_LEVEL_HIGH>, /* misc interrupts */
<55 IRQ_TYPE_LEVEL_HIGH>; /* MSI */
};

9
Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
View File

@@ -16,13 +16,15 @@ allOf:
properties: properties:
compatible: compatible:
oneOf: oneOf:
- const: ti,j721e-pcie-ep
- description: PCIe EP controller in AM64
items:
- const: ti,am64-pcie-ep
- const: ti,j721e-pcie-ep
- description: PCIe EP controller in J7200 - description: PCIe EP controller in J7200
items: items:
- const: ti,j7200-pcie-ep - const: ti,j7200-pcie-ep
- const: ti,j721e-pcie-ep - const: ti,j721e-pcie-ep
- description: PCIe EP controller in J721E
items:
- const: ti,j721e-pcie-ep
reg: reg:
maxItems: 4 maxItems: 4
@@ -66,7 +68,6 @@ required:
- power-domains - power-domains
- clocks - clocks
- clock-names - clock-names
- dma-coherent
- max-functions - max-functions
- phys - phys
- phy-names - phy-names

20
Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
View File

@@ -16,13 +16,15 @@ allOf:
properties: properties:
compatible: compatible:
oneOf: oneOf:
- const: ti,j721e-pcie-host
- description: PCIe controller in AM64
items:
- const: ti,am64-pcie-host
- const: ti,j721e-pcie-host
- description: PCIe controller in J7200 - description: PCIe controller in J7200
items: items:
- const: ti,j7200-pcie-host - const: ti,j7200-pcie-host
- const: ti,j721e-pcie-host - const: ti,j721e-pcie-host
- description: PCIe controller in J721E
items:
- const: ti,j721e-pcie-host
reg: reg:
maxItems: 4 maxItems: 4
@@ -46,12 +48,17 @@ properties:
maxItems: 1 maxItems: 1
clocks: clocks:
maxItems: 1 minItems: 1
description: clock-specifier to represent input to the PCIe maxItems: 2
description: |+
clock-specifier to represent input to the PCIe for 1 item.
2nd item if present represents reference clock to the connector.
clock-names: clock-names:
minItems: 1
items: items:
- const: fck - const: fck
- const: pcie_refclk
vendor-id: vendor-id:
const: 0x104c const: 0x104c
@@ -62,6 +69,8 @@ properties:
- const: 0xb00d - const: 0xb00d
- items: - items:
- const: 0xb00f - const: 0xb00f
- items:
- const: 0xb010
msi-map: true msi-map: true
@@ -78,7 +87,6 @@ required:
- vendor-id - vendor-id
- device-id - device-id
- msi-map - msi-map
- dma-coherent
- dma-ranges - dma-ranges
- ranges - ranges
- reset-gpios - reset-gpios

2
Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
View File

@@ -33,6 +33,8 @@ Required properties:
- #address-cells: specifies the number of cells needed to encode an - #address-cells: specifies the number of cells needed to encode an
address. The value must be 0. address. The value must be 0.
Optional properties:
- dma-coherent: present if DMA operations are coherent
Example: Example:
++++++++ ++++++++

58
Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
View File

@@ -51,23 +51,7 @@ Deprecated properties for iomux controller:
Use rockchip,grf and rockchip,pmu described above instead. Use rockchip,grf and rockchip,pmu described above instead.
Required properties for gpio sub nodes: Required properties for gpio sub nodes:
- compatible: "rockchip,gpio-bank" See rockchip,gpio-bank.yaml
- reg: register of the gpio bank (different than the iomux registerset)
- interrupts: base interrupt of the gpio bank in the interrupt controller
- clocks: clock that drives this bank
- gpio-controller: identifies the node as a gpio controller and pin bank.
- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
binding is used, the amount of cells must be specified as 2. See generic
GPIO binding documentation for description of particular cells.
- interrupt-controller: identifies the controller node as interrupt-parent.
- #interrupt-cells: the value of this property should be 2 and the interrupt
cells should use the standard two-cell scheme described in
bindings/interrupt-controller/interrupts.txt
Deprecated properties for gpio sub nodes:
- compatible: "rockchip,rk3188-gpio-bank0"
- reg: second element: separate pull register for rk3188 bank0, use
rockchip,pmu described above instead
Required properties for pin configuration node: Required properties for pin configuration node:
- rockchip,pins: 3 integers array, represents a group of pins mux and config - rockchip,pins: 3 integers array, represents a group of pins mux and config
@@ -128,43 +112,3 @@ uart2: serial@20064000 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&uart2_xfer>; pinctrl-0 = <&uart2_xfer>;
}; };
Example for rk3188:
pinctrl@20008000 {
compatible = "rockchip,rk3188-pinctrl";
rockchip,grf = <&grf>;
rockchip,pmu = <&pmu>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio0: gpio0@2000a000 {
compatible = "rockchip,rk3188-gpio-bank0";
reg = <0x2000a000 0x100>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates8 9>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio1@2003c000 {
compatible = "rockchip,gpio-bank";
reg = <0x2003c000 0x100>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates8 10>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
...
};

27
Documentation/devicetree/bindings/pwm/pwm-rockchip.txt
View File

@@ -1,27 +0,0 @@
Rockchip PWM controller
Required properties:
- compatible: should be "rockchip,<name>-pwm"
"rockchip,rk2928-pwm": found on RK29XX,RK3066 and RK3188 SoCs
"rockchip,rk3288-pwm": found on RK3288 SOC
"rockchip,rv1108-pwm", "rockchip,rk3288-pwm": found on RV1108 SoC
"rockchip,vop-pwm": found integrated in VOP on RK3288 SoC
- reg: physical base address and length of the controller's registers
- clocks: See ../clock/clock-bindings.txt
- For older hardware (rk2928, rk3066, rk3188, rk3228, rk3288, rk3399):
- There is one clock that's used both to derive the functional clock
for the device and as the bus clock.
- For newer hardware (rk3328 and future socs): specified by name
- "pwm": This is used to derive the functional clock.
- "pclk": This is the APB bus clock.
- #pwm-cells: must be 2 (rk2928) or 3 (rk3288). See pwm.yaml in this directory
for a description of the cell format.
Example:
pwm0: pwm@20030000 {
compatible = "rockchip,rk2928-pwm";
reg = <0x20030000 0x10>;
clocks = <&cru PCLK_PWM01>;
#pwm-cells = <2>;
};

100
Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml Normal file
View File

@@ -0,0 +1,100 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/pwm/pwm-rockchip.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip PWM controller
maintainers:
- Heiko Stuebner <heiko@sntech.de>
properties:
compatible:
oneOf:
- const: rockchip,rk2928-pwm
- const: rockchip,rk3288-pwm
- const: rockchip,rk3328-pwm
- const: rockchip,vop-pwm
- items:
- const: rockchip,rk3036-pwm
- const: rockchip,rk2928-pwm
- items:
- enum:
- rockchip,rk3368-pwm
- rockchip,rk3399-pwm
- rockchip,rv1108-pwm
- const: rockchip,rk3288-pwm
- items:
- enum:
- rockchip,px30-pwm
- rockchip,rk3308-pwm
- const: rockchip,rk3328-pwm
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
clock-names:
maxItems: 2
"#pwm-cells":
enum: [2, 3]
description:
Must be 2 (rk2928) or 3 (rk3288 and later).
See pwm.yaml for a description of the cell format.
required:
- compatible
- reg
- "#pwm-cells"
if:
properties:
compatible:
contains:
enum:
- rockchip,rk3328-pwm
- rockchip,rv1108-pwm
then:
properties:
clocks:
items:
- description: Used to derive the functional clock for the device.
- description: Used as the APB bus clock.
clock-names:
items:
- const: pwm
- const: pclk
required:
- clocks
- clock-names
else:
properties:
clocks:
maxItems: 1
description:
Used both to derive the functional clock
for the device and as the bus clock.
required:
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/rk3188-cru-common.h>
pwm0: pwm@20030000 {
compatible = "rockchip,rk2928-pwm";
reg = <0x20030000 0x10>;
clocks = <&cru PCLK_PWM01>;
#pwm-cells = <2>;
};

43
Documentation/devicetree/bindings/pwm/toshiba,pwm-visconti.yaml Normal file
View File

@@ -0,0 +1,43 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pwm/toshiba,pwm-visconti.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Toshiba Visconti PWM Controller
maintainers:
- Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
properties:
compatible:
items:
- const: toshiba,visconti-pwm
reg:
maxItems: 1
'#pwm-cells':
const: 2
required:
- compatible
- reg
- '#pwm-cells'
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
pwm: pwm@241c0000 {
compatible = "toshiba,visconti-pwm";
reg = <0 0x241c0000 0 0x1000>;
pinctrl-names = "default";
pinctrl-0 = <&pwm_mux>;
#pwm-cells = <2>;
};
};

90
Documentation/devicetree/bindings/remoteproc/fsl,imx-rproc.yaml Normal file
View File

@@ -0,0 +1,90 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/remoteproc/fsl,imx-rproc.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: NXP i.MX Co-Processor Bindings
description:
This binding provides support for ARM Cortex M4 Co-processor found on some NXP iMX SoCs.
maintainers:
- Peng Fan <peng.fan@nxp.com>
properties:
compatible:
enum:
- fsl,imx8mq-cm4
- fsl,imx8mm-cm4
- fsl,imx7d-cm4
- fsl,imx6sx-cm4
clocks:
maxItems: 1
syscon:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to syscon block which provide access to System Reset Controller
mbox-names:
items:
- const: tx
- const: rx
- const: rxdb
mboxes:
description:
This property is required only if the rpmsg/virtio functionality is used.
List of <&phandle type channel> - 1 channel for TX, 1 channel for RX, 1 channel for RXDB.
(see mailbox/fsl,mu.yaml)
minItems: 1
maxItems: 3
memory-region:
description:
If present, a phandle for a reserved memory area that used for vdev buffer,
resource table, vring region and others used by remote processor.
minItems: 1
maxItems: 32
required:
- compatible
- clocks
- syscon
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx7d-clock.h>
m4_reserved_sysmem1: cm4@80000000 {
reg = <0x80000000 0x80000>;
};
m4_reserved_sysmem2: cm4@81000000 {
reg = <0x81000000 0x80000>;
};
imx7d-cm4 {
compatible = "fsl,imx7d-cm4";
memory-region = <&m4_reserved_sysmem1>, <&m4_reserved_sysmem2>;
syscon = <&src>;
clocks = <&clks IMX7D_ARM_M4_ROOT_CLK>;
};
- |
#include <dt-bindings/clock/imx8mm-clock.h>
imx8mm-cm4 {
compatible = "fsl,imx8mm-cm4";
clocks = <&clk IMX8MM_CLK_M4_DIV>;
mbox-names = "tx", "rx", "rxdb";
mboxes = <&mu 0 1
&mu 1 1
&mu 3 1>;
memory-region = <&vdev0buffer>, <&vdev0vring0>, <&vdev0vring1>, <&rsc_table>;
syscon = <&src>;
};
...

33
Documentation/devicetree/bindings/remoteproc/imx-rproc.txt
View File

@@ -1,33 +0,0 @@
NXP iMX6SX/iMX7D Co-Processor Bindings
----------------------------------------
This binding provides support for ARM Cortex M4 Co-processor found on some
NXP iMX SoCs.
Required properties:
- compatible Should be one of:
"fsl,imx7d-cm4"
"fsl,imx6sx-cm4"
- clocks Clock for co-processor (See: ../clock/clock-bindings.txt)
- syscon Phandle to syscon block which provide access to
System Reset Controller
Optional properties:
- memory-region list of phandels to the reserved memory regions.
(See: ../reserved-memory/reserved-memory.txt)
Example:
m4_reserved_sysmem1: cm4@80000000 {
reg = <0x80000000 0x80000>;
};
m4_reserved_sysmem2: cm4@81000000 {
reg = <0x81000000 0x80000>;
};
imx7d-cm4 {
compatible = "fsl,imx7d-cm4";
memory-region = <&m4_reserved_sysmem1>, <&m4_reserved_sysmem2>;
syscon = <&src>;
clocks = <&clks IMX7D_ARM_M4_ROOT_CLK>;
};

4
Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt
View File

@@ -18,6 +18,7 @@ on the Qualcomm ADSP Hexagon core.
"qcom,sc7180-mpss-pas" "qcom,sc7180-mpss-pas"
"qcom,sdm845-adsp-pas" "qcom,sdm845-adsp-pas"
"qcom,sdm845-cdsp-pas" "qcom,sdm845-cdsp-pas"
"qcom,sdx55-mpss-pas"
"qcom,sm8150-adsp-pas" "qcom,sm8150-adsp-pas"
"qcom,sm8150-cdsp-pas" "qcom,sm8150-cdsp-pas"
"qcom,sm8150-mpss-pas" "qcom,sm8150-mpss-pas"
@@ -61,6 +62,7 @@ on the Qualcomm ADSP Hexagon core.
must be "wdog", "fatal", "ready", "handover", "stop-ack" must be "wdog", "fatal", "ready", "handover", "stop-ack"
qcom,qcs404-wcss-pas: qcom,qcs404-wcss-pas:
qcom,sc7180-mpss-pas: qcom,sc7180-mpss-pas:
qcom,sdx55-mpss-pas:
qcom,sm8150-mpss-pas: qcom,sm8150-mpss-pas:
qcom,sm8350-mpss-pas: qcom,sm8350-mpss-pas:
must be "wdog", "fatal", "ready", "handover", "stop-ack", must be "wdog", "fatal", "ready", "handover", "stop-ack",
@@ -128,6 +130,8 @@ on the Qualcomm ADSP Hexagon core.
qcom,sm8150-mpss-pas: qcom,sm8150-mpss-pas:
qcom,sm8350-mpss-pas: qcom,sm8350-mpss-pas:
must be "cx", "load_state", "mss" must be "cx", "load_state", "mss"
qcom,sdx55-mpss-pas:
must be "cx", "mss"
qcom,sm8250-adsp-pas: qcom,sm8250-adsp-pas:
qcom,sm8350-adsp-pas: qcom,sm8350-adsp-pas:
qcom,sm8150-slpi-pas: qcom,sm8150-slpi-pas:

15
Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
View File

@@ -9,6 +9,7 @@ on the Qualcomm Hexagon core.
Definition: must be one of: Definition: must be one of:
"qcom,q6v5-pil", "qcom,q6v5-pil",
"qcom,ipq8074-wcss-pil" "qcom,ipq8074-wcss-pil"
"qcom,qcs404-wcss-pil"
"qcom,msm8916-mss-pil", "qcom,msm8916-mss-pil",
"qcom,msm8974-mss-pil" "qcom,msm8974-mss-pil"
"qcom,msm8996-mss-pil" "qcom,msm8996-mss-pil"
@@ -39,6 +40,7 @@ on the Qualcomm Hexagon core.
string: string:
qcom,q6v5-pil: qcom,q6v5-pil:
qcom,ipq8074-wcss-pil: qcom,ipq8074-wcss-pil:
qcom,qcs404-wcss-pil:
qcom,msm8916-mss-pil: qcom,msm8916-mss-pil:
qcom,msm8974-mss-pil: qcom,msm8974-mss-pil:
must be "wdog", "fatal", "ready", "handover", "stop-ack" must be "wdog", "fatal", "ready", "handover", "stop-ack"
@@ -67,6 +69,11 @@ on the Qualcomm Hexagon core.
Definition: The clocks needed depend on the compatible string: Definition: The clocks needed depend on the compatible string:
qcom,ipq8074-wcss-pil: qcom,ipq8074-wcss-pil:
no clock names required no clock names required
qcom,qcs404-wcss-pil:
must be "xo", "gcc_abhs_cbcr", "gcc_abhs_cbcr",
"gcc_axim_cbcr", "lcc_ahbfabric_cbc", "tcsr_lcc_cbc",
"lcc_abhs_cbc", "lcc_tcm_slave_cbc", "lcc_abhm_cbc",
"lcc_axim_cbc", "lcc_bcr_sleep"
qcom,q6v5-pil: qcom,q6v5-pil:
qcom,msm8916-mss-pil: qcom,msm8916-mss-pil:
qcom,msm8974-mss-pil: qcom,msm8974-mss-pil:
@@ -132,6 +139,14 @@ For the compatible string below the following supplies are required:
Definition: reference to the regulators to be held on behalf of the Definition: reference to the regulators to be held on behalf of the
booting of the Hexagon core booting of the Hexagon core
For the compatible string below the following supplies are required:
"qcom,qcs404-wcss-pil"
- cx-supply:
Usage: required
Value type: <phandle>
Definition: reference to the regulators to be held on behalf of the
booting of the Hexagon core
For the compatible string below the following supplies are required: For the compatible string below the following supplies are required:
"qcom,msm8996-mss-pil" "qcom,msm8996-mss-pil"
- pll-supply: - pll-supply:

6
Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.txt
View File

@@ -34,6 +34,12 @@ on the Qualcomm WCNSS core.
Definition: should be "wdog", "fatal", optionally followed by "ready", Definition: should be "wdog", "fatal", optionally followed by "ready",
"handover", "stop-ack" "handover", "stop-ack"
- firmware-name:
Usage: optional
Value type: <string>
Definition: must list the relative firmware image path for the
WCNSS core. Defaults to "wcnss.mdt".
- vddmx-supply: (deprecated for qcom,pronto-v1/2-pil) - vddmx-supply: (deprecated for qcom,pronto-v1/2-pil)
- vddcx-supply: (deprecated for qcom,pronto-v1/2-pil) - vddcx-supply: (deprecated for qcom,pronto-v1/2-pil)
- vddpx-supply: - vddpx-supply:

11
Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml
View File

@@ -65,16 +65,23 @@ properties:
Unidirectional channel: Unidirectional channel:
- from local to remote, where ACK from the remote means that it is - from local to remote, where ACK from the remote means that it is
ready for shutdown ready for shutdown
- description: |
A channel (d) used by the local proc to notify the remote proc that it
has to stop interprocessor communnication.
Unidirectional channel:
- from local to remote, where ACK from the remote means that communnication
as been stopped on the remote side.
minItems: 1 minItems: 1
maxItems: 3 maxItems: 4
mbox-names: mbox-names:
items: items:
- const: vq0 - const: vq0
- const: vq1 - const: vq1
- const: shutdown - const: shutdown
- const: detach
minItems: 1 minItems: 1
maxItems: 3 maxItems: 4
memory-region: memory-region:
description: description:

27
Documentation/devicetree/bindings/riscv/microchip.yaml Normal file
View File

@@ -0,0 +1,27 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/riscv/microchip.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip PolarFire SoC-based boards device tree bindings
maintainers:
- Cyril Jean <Cyril.Jean@microchip.com>
- Lewis Hanly <lewis.hanly@microchip.com>
description:
Microchip PolarFire SoC-based boards
properties:
$nodename:
const: '/'
compatible:
items:
- enum:
- microchip,mpfs-icicle-kit
- const: microchip,mpfs
additionalProperties: true
...

62
Documentation/devicetree/bindings/rtc/qcom-pm8xxx-rtc.yaml Normal file
View File

@@ -0,0 +1,62 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/qcom-pm8xxx-rtc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm PM8xxx PMIC RTC device
maintainers:
- Satya Priya <skakit@codeaurora.org>
properties:
compatible:
enum:
- qcom,pm8058-rtc
- qcom,pm8921-rtc
- qcom,pm8941-rtc
- qcom,pm8018-rtc
- qcom,pmk8350-rtc
reg:
maxItems: 1
interrupts:
maxItems: 1
allow-set-time:
$ref: /schemas/types.yaml#/definitions/flag
description:
Indicates that the setting of RTC time is allowed by the host CPU.
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/spmi/spmi.h>
spmi_bus: spmi@c440000 {
reg = <0x0c440000 0x1100>;
#address-cells = <2>;
#size-cells = <0>;
pmicintc: pmic@0 {
reg = <0x0 SPMI_USID>;
compatible = "qcom,pm8921";
interrupts = <104 8>;
#interrupt-cells = <2>;
interrupt-controller;
#address-cells = <1>;
#size-cells = <0>;
pm8921_rtc: rtc@11d {
compatible = "qcom,pm8921-rtc";
reg = <0x11d>;
interrupts = <0x27 0>;
};
};
};
...

5
Documentation/devicetree/bindings/serial/8250.yaml
View File

@@ -99,11 +99,6 @@ properties:
- mediatek,mt7622-btif - mediatek,mt7622-btif
- mediatek,mt7623-btif - mediatek,mt7623-btif
- const: mediatek,mtk-btif - const: mediatek,mtk-btif
- items:
- enum:
- mediatek,mt7622-btif
- mediatek,mt7623-btif
- const: mediatek,mtk-btif
- items: - items:
- const: mrvl,mmp-uart - const: mrvl,mmp-uart
- const: intel,xscale-uart - const: intel,xscale-uart

37
Documentation/devicetree/bindings/thermal/brcm,ns-thermal.txt
View File

@@ -1,37 +0,0 @@
* Broadcom Northstar Thermal
This binding describes thermal sensor that is part of Northstar's DMU (Device
Management Unit).
Required properties:
- compatible : Must be "brcm,ns-thermal"
- reg : iomem address range of PVTMON registers
- #thermal-sensor-cells : Should be <0>
Example:
thermal: thermal@1800c2c0 {
compatible = "brcm,ns-thermal";
reg = <0x1800c2c0 0x10>;
#thermal-sensor-cells = <0>;
};
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <0>;
polling-delay = <1000>;
coefficients = <(-556) 418000>;
thermal-sensors = <&thermal>;
trips {
cpu-crit {
temperature = <125000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
};
};
};

60
Documentation/devicetree/bindings/thermal/brcm,ns-thermal.yaml Normal file
View File

@@ -0,0 +1,60 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/thermal/brcm,ns-thermal.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom Northstar Thermal
maintainers:
- Rafał Miłecki <rafal@milecki.pl>
description:
Thermal sensor that is part of Northstar's DMU (Device Management Unit).
allOf:
- $ref: thermal-sensor.yaml#
properties:
compatible:
const: brcm,ns-thermal
reg:
description: PVTMON registers range
maxItems: 1
"#thermal-sensor-cells":
const: 0
unevaluatedProperties: false
required:
- reg
examples:
- |
thermal: thermal@1800c2c0 {
compatible = "brcm,ns-thermal";
reg = <0x1800c2c0 0x10>;
#thermal-sensor-cells = <0>;
};
thermal-zones {
cpu-thermal {
polling-delay-passive = <0>;
polling-delay = <1000>;
coefficients = <(-556) 418000>;
thermal-sensors = <&thermal>;
trips {
cpu-crit {
temperature = <125000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
};
};
};

59
Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
View File

@@ -19,9 +19,15 @@ description: |
properties: properties:
compatible: compatible:
oneOf: oneOf:
- description: msm9860 TSENS based
items:
- enum:
- qcom,ipq8064-tsens
- description: v0.1 of TSENS - description: v0.1 of TSENS
items: items:
- enum: - enum:
- qcom,mdm9607-tsens
- qcom,msm8916-tsens - qcom,msm8916-tsens
- qcom,msm8939-tsens - qcom,msm8939-tsens
- qcom,msm8974-tsens - qcom,msm8974-tsens
@@ -43,6 +49,7 @@ properties:
- qcom,sdm845-tsens - qcom,sdm845-tsens
- qcom,sm8150-tsens - qcom,sm8150-tsens
- qcom,sm8250-tsens - qcom,sm8250-tsens
- qcom,sm8350-tsens
- const: qcom,tsens-v2 - const: qcom,tsens-v2
reg: reg:
@@ -73,7 +80,9 @@ properties:
maxItems: 2 maxItems: 2
items: items:
- const: calib - const: calib
- const: calib_sel - enum:
- calib_backup
- calib_sel
"#qcom,sensors": "#qcom,sensors":
description: description:
@@ -88,12 +97,21 @@ properties:
Number of cells required to uniquely identify the thermal sensors. Since Number of cells required to uniquely identify the thermal sensors. Since
we have multiple sensors this is set to 1 we have multiple sensors this is set to 1
required:
- compatible
- interrupts
- interrupt-names
- "#thermal-sensor-cells"
- "#qcom,sensors"
allOf: allOf:
- if: - if:
properties: properties:
compatible: compatible:
contains: contains:
enum: enum:
- qcom,ipq8064-tsens
- qcom,mdm9607-tsens
- qcom,msm8916-tsens - qcom,msm8916-tsens
- qcom,msm8974-tsens - qcom,msm8974-tsens
- qcom,msm8976-tsens - qcom,msm8976-tsens
@@ -114,17 +132,42 @@ allOf:
interrupt-names: interrupt-names:
minItems: 2 minItems: 2
required: - if:
- compatible properties:
- reg compatible:
- "#qcom,sensors" contains:
- interrupts enum:
- interrupt-names - qcom,tsens-v0_1
- "#thermal-sensor-cells" - qcom,tsens-v1
- qcom,tsens-v2
then:
required:
- reg
additionalProperties: false additionalProperties: false
examples: examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
// Example msm9860 based SoC (ipq8064):
gcc: clock-controller {
/* ... */
tsens: thermal-sensor {
compatible = "qcom,ipq8064-tsens";
nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
nvmem-cell-names = "calib", "calib_backup";
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow";
#qcom,sensors = <11>;
#thermal-sensor-cells = <1>;
};
};
- | - |
#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/arm-gic.h>
// Example 1 (legacy: for pre v1 IP): // Example 1 (legacy: for pre v1 IP):

43
Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.yaml
View File

@@ -28,14 +28,7 @@ properties:
- renesas,r8a77980-thermal # R-Car V3H - renesas,r8a77980-thermal # R-Car V3H
- renesas,r8a779a0-thermal # R-Car V3U - renesas,r8a779a0-thermal # R-Car V3U
reg: reg: true
minItems: 2
maxItems: 4
items:
- description: TSC1 registers
- description: TSC2 registers
- description: TSC3 registers
- description: TSC4 registers
interrupts: interrupts:
items: items:
@@ -71,8 +64,25 @@ if:
enum: enum:
- renesas,r8a779a0-thermal - renesas,r8a779a0-thermal
then: then:
properties:
reg:
minItems: 2
maxItems: 3
items:
- description: TSC1 registers
- description: TSC2 registers
- description: TSC3 registers
required: required:
- interrupts - interrupts
else:
properties:
reg:
items:
- description: TSC0 registers
- description: TSC1 registers
- description: TSC2 registers
- description: TSC3 registers
- description: TSC4 registers
additionalProperties: false additionalProperties: false
@@ -111,3 +121,20 @@ examples:
}; };
}; };
}; };
- |
#include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a779a0-sysc.h>
tsc_r8a779a0: thermal@e6190000 {
compatible = "renesas,r8a779a0-thermal";
reg = <0xe6190000 0x200>,
<0xe6198000 0x200>,
<0xe61a0000 0x200>,
<0xe61a8000 0x200>,
<0xe61b0000 0x200>;
clocks = <&cpg CPG_MOD 919>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 919>;
#thermal-sensor-cells = <1>;
};

3
Documentation/devicetree/bindings/thermal/thermal-sensor.yaml
View File

@@ -36,6 +36,9 @@ properties:
containing several internal sensors. containing several internal sensors.
enum: [0, 1] enum: [0, 1]
required:
- "#thermal-sensor-cells"
additionalProperties: true additionalProperties: true
examples: examples:

2
Documentation/devicetree/bindings/vendor-prefixes.yaml
View File

@@ -495,6 +495,8 @@ patternProperties:
description: Shenzhen Hugsun Technology Co. Ltd. description: Shenzhen Hugsun Technology Co. Ltd.
"^hwacom,.*": "^hwacom,.*":
description: HwaCom Systems Inc. description: HwaCom Systems Inc.
"^hycon,.*":
description: Hycon Technology Corp.
"^hydis,.*": "^hydis,.*":
description: Hydis Technologies description: Hydis Technologies
"^hyundai,.*": "^hyundai,.*":

2
Documentation/driver-api/gpio/consumer.rst
View File

@@ -12,7 +12,7 @@ Guidelines for GPIOs consumers
Drivers that can't work without standard GPIO calls should have Kconfig entries Drivers that can't work without standard GPIO calls should have Kconfig entries
that depend on GPIOLIB or select GPIOLIB. The functions that allow a driver to that depend on GPIOLIB or select GPIOLIB. The functions that allow a driver to
obtain and use GPIOs are available by including the following file: obtain and use GPIOs are available by including the following file::
#include <linux/gpio/consumer.h> #include <linux/gpio/consumer.h>

6
Documentation/driver-api/gpio/drivers-on-gpio.rst
View File

@@ -96,6 +96,12 @@ hardware descriptions such as device tree or ACPI:
way to pass the charging parameters from hardware descriptions such as the way to pass the charging parameters from hardware descriptions such as the
device tree. device tree.
- gpio-mux: drivers/mux/gpio.c is used for controlling a multiplexer using
n GPIO lines such that you can mux in 2^n different devices by activating
different GPIO lines. Often the GPIOs are on a SoC and the devices are
some SoC-external entities, such as different components on a PCB that
can be selectively enabled.
Apart from this there are special GPIO drivers in subsystems like MMC/SD to Apart from this there are special GPIO drivers in subsystems like MMC/SD to
read card detect and write protect GPIO lines, and in the TTY serial subsystem read card detect and write protect GPIO lines, and in the TTY serial subsystem
to emulate MCTRL (modem control) signals CTS/RTS by using two GPIO lines. The to emulate MCTRL (modem control) signals CTS/RTS by using two GPIO lines. The

6
Documentation/driver-api/pwm.rst
View File

@@ -55,7 +55,11 @@ several parameter at once. For example, if you see pwm_config() and
pwm_{enable,disable}() calls in the same function, this probably means you pwm_{enable,disable}() calls in the same function, this probably means you
should switch to pwm_apply_state(). should switch to pwm_apply_state().
The PWM user API also allows one to query the PWM state with pwm_get_state(). The PWM user API also allows one to query the PWM state that was passed to the
last invocation of pwm_apply_state() using pwm_get_state(). Note this is
different to what the driver has actually implemented if the request cannot be
satisfied exactly with the hardware in use. There is currently no way for
consumers to get the actually implemented settings.
In addition to the PWM state, the PWM API also exposes PWM arguments, which In addition to the PWM state, the PWM API also exposes PWM arguments, which
are the reference PWM config one should use on this PWM. are the reference PWM config one should use on this PWM.

12
Documentation/driver-api/thermal/sysfs-api.rst
View File

@@ -730,17 +730,7 @@ This function returns the thermal_instance corresponding to a given
{thermal_zone, cooling_device, trip_point} combination. Returns NULL {thermal_zone, cooling_device, trip_point} combination. Returns NULL
if such an instance does not exist. if such an instance does not exist.
4.3. thermal_notify_framework 4.3. thermal_cdev_update
-----------------------------
This function handles the trip events from sensor drivers. It starts
throttling the cooling devices according to the policy configured.
For CRITICAL and HOT trip points, this notifies the respective drivers,
and does actual throttling for other trip points i.e ACTIVE and PASSIVE.
The throttling policy is based on the configured platform data; if no
platform data is provided, this uses the step_wise throttling policy.
4.4. thermal_cdev_update
------------------------ ------------------------
This function serves as an arbitrator to set the state of a cooling This function serves as an arbitrator to set the state of a cooling

2
Documentation/driver-api/vfio.rst
View File

@@ -2,7 +2,7 @@
VFIO - "Virtual Function I/O" [1]_ VFIO - "Virtual Function I/O" [1]_
================================== ==================================
Many modern system now provide DMA and interrupt remapping facilities Many modern systems now provide DMA and interrupt remapping facilities
to help ensure I/O devices behave within the boundaries they've been to help ensure I/O devices behave within the boundaries they've been
allotted. This includes x86 hardware with AMD-Vi and Intel VT-d, allotted. This includes x86 hardware with AMD-Vi and Intel VT-d,
POWER systems with Partitionable Endpoints (PEs) and embedded PowerPC POWER systems with Partitionable Endpoints (PEs) and embedded PowerPC

14
Documentation/filesystems/f2fs.rst
View File

@@ -110,6 +110,12 @@ background_gc=%s Turn on/off cleaning operations, namely garbage
on synchronous garbage collection running in background. on synchronous garbage collection running in background.
Default value for this option is on. So garbage Default value for this option is on. So garbage
collection is on by default. collection is on by default.
gc_merge When background_gc is on, this option can be enabled to
let background GC thread to handle foreground GC requests,
it can eliminate the sluggish issue caused by slow foreground
GC operation when GC is triggered from a process with limited
I/O and CPU resources.
nogc_merge Disable GC merge feature.
disable_roll_forward Disable the roll-forward recovery routine disable_roll_forward Disable the roll-forward recovery routine
norecovery Disable the roll-forward recovery routine, mounted read- norecovery Disable the roll-forward recovery routine, mounted read-
only (i.e., -o ro,disable_roll_forward) only (i.e., -o ro,disable_roll_forward)
@@ -813,6 +819,14 @@ Compression implementation
* chattr +c file * chattr +c file
* chattr +c dir; touch dir/file * chattr +c dir; touch dir/file
* mount w/ -o compress_extension=ext; touch file.ext * mount w/ -o compress_extension=ext; touch file.ext
* mount w/ -o compress_extension=*; touch any_file
- At this point, compression feature doesn't expose compressed space to user
directly in order to guarantee potential data updates later to the space.
Instead, the main goal is to reduce data writes to flash disk as much as
possible, resulting in extending disk life time as well as relaxing IO
congestion. Alternatively, we've added ioctl interface to reclaim compressed
space and show it to user after putting the immutable bit.
Compress metadata layout:: Compress metadata layout::

6
Documentation/firmware-guide/acpi/gpio-properties.rst
View File

@@ -99,6 +99,12 @@ native::
} }
} }
Note, that historically ACPI has no means of the GPIO polarity and thus
the SPISerialBus() resource defines it on the per-chip basis. In order
to avoid a chain of negations, the GPIO polarity is considered being
Active High. Even for the cases when _DSD() is involved (see the example
above) the GPIO CS polarity must be defined Active High to avoid ambiguity.
Other supported properties Other supported properties
========================== ==========================

8
Documentation/input/devices/rotary-encoder.rst
View File

@@ -107,13 +107,17 @@ example below:
}, },
}; };
static const struct property_entry rotary_encoder_properties[] __initconst = { static const struct property_entry rotary_encoder_properties[] = {
PROPERTY_ENTRY_U32("rotary-encoder,steps-per-period", 24), PROPERTY_ENTRY_U32("rotary-encoder,steps-per-period", 24),
PROPERTY_ENTRY_U32("linux,axis", ABS_X), PROPERTY_ENTRY_U32("linux,axis", ABS_X),
PROPERTY_ENTRY_U32("rotary-encoder,relative_axis", 0), PROPERTY_ENTRY_U32("rotary-encoder,relative_axis", 0),
{ }, { },
}; };
static const struct software_node rotary_encoder_node = {
.properties = rotary_encoder_properties,
};
static struct platform_device rotary_encoder_device = { static struct platform_device rotary_encoder_device = {
.name = "rotary-encoder", .name = "rotary-encoder",
.id = 0, .id = 0,
@@ -122,7 +126,7 @@ example below:
... ...
gpiod_add_lookup_table(&rotary_encoder_gpios); gpiod_add_lookup_table(&rotary_encoder_gpios);
device_add_properties(&rotary_encoder_device, rotary_encoder_properties); device_add_software_node(&rotary_encoder_device.dev, &rotary_encoder_node);
platform_device_register(&rotary_encoder_device); platform_device_register(&rotary_encoder_device);
... ...

14
Documentation/input/joydev/joystick-api.rst
View File

@@ -71,7 +71,7 @@ The possible values of ``type`` are::
#define JS_EVENT_INIT 0x80 /* initial state of device */ #define JS_EVENT_INIT 0x80 /* initial state of device */
As mentioned above, the driver will issue synthetic JS_EVENT_INIT ORed As mentioned above, the driver will issue synthetic JS_EVENT_INIT ORed
events on open. That is, if it's issuing a INIT BUTTON event, the events on open. That is, if it's issuing an INIT BUTTON event, the
current type value will be:: current type value will be::
int type = JS_EVENT_BUTTON | JS_EVENT_INIT; /* 0x81 */ int type = JS_EVENT_BUTTON | JS_EVENT_INIT; /* 0x81 */
@@ -100,8 +100,8 @@ is, you have both an axis 0 and a button 0). Generally,
=============== ======= =============== =======
Hats vary from one joystick type to another. Some can be moved in 8 Hats vary from one joystick type to another. Some can be moved in 8
directions, some only in 4, The driver, however, always reports a hat as two directions, some only in 4. The driver, however, always reports a hat as two
independent axis, even if the hardware doesn't allow independent movement. independent axes, even if the hardware doesn't allow independent movement.
js_event.value js_event.value
@@ -188,10 +188,10 @@ One reason for emptying the queue is that if it gets full you'll start
missing events since the queue is finite, and older events will get missing events since the queue is finite, and older events will get
overwritten. overwritten.
The other reason is that you want to know all what happened, and not The other reason is that you want to know all that happened, and not
delay the processing till later. delay the processing till later.
Why can get the queue full? Because you don't empty the queue as Why can the queue get full? Because you don't empty the queue as
mentioned, or because too much time elapses from one read to another mentioned, or because too much time elapses from one read to another
and too many events to store in the queue get generated. Note that and too many events to store in the queue get generated. Note that
high system load may contribute to space those reads even more. high system load may contribute to space those reads even more.
@@ -277,7 +277,7 @@ to be in the stable part of the API, and therefore may change without
warning in following releases of the driver. warning in following releases of the driver.
Both JSIOCSCORR and JSIOCGCORR expect &js_corr to be able to hold Both JSIOCSCORR and JSIOCGCORR expect &js_corr to be able to hold
information for all axis. That is, struct js_corr corr[MAX_AXIS]; information for all axes. That is, struct js_corr corr[MAX_AXIS];
struct js_corr is defined as:: struct js_corr is defined as::
@@ -328,7 +328,7 @@ To test the state of the buttons,
second_button_state = js.buttons & 2; second_button_state = js.buttons & 2;
The axis values do not have a defined range in the original 0.x driver, The axis values do not have a defined range in the original 0.x driver,
except for that the values are non-negative. The 1.2.8+ drivers use a except that the values are non-negative. The 1.2.8+ drivers use a
fixed range for reporting the values, 1 being the minimum, 128 the fixed range for reporting the values, 1 being the minimum, 128 the
center, and 255 maximum value. center, and 255 maximum value.

26
Documentation/input/joydev/joystick.rst
View File

@@ -133,15 +133,15 @@ And add a line to your rc script executing that file::
This way, after the next reboot your joystick will remain calibrated. You This way, after the next reboot your joystick will remain calibrated. You
can also add the ``jscal -p`` line to your shutdown script. can also add the ``jscal -p`` line to your shutdown script.
HW specific driver information Hardware-specific driver information
============================== ====================================
In this section each of the separate hardware specific drivers is described. In this section each of the separate hardware specific drivers is described.
Analog joysticks Analog joysticks
---------------- ----------------
The analog.c uses the standard analog inputs of the gameport, and thus The analog.c driver uses the standard analog inputs of the gameport, and thus
supports all standard joysticks and gamepads. It uses a very advanced supports all standard joysticks and gamepads. It uses a very advanced
routine for this, allowing for data precision that can't be found on any routine for this, allowing for data precision that can't be found on any
other system. other system.
@@ -266,7 +266,7 @@ to:
* Logitech WingMan Extreme Digital 3D * Logitech WingMan Extreme Digital 3D
ADI devices are autodetected, and the driver supports up to two (any ADI devices are autodetected, and the driver supports up to two (any
combination of) devices on a single gameport, using an Y-cable or chained combination of) devices on a single gameport, using a Y-cable or chained
together. together.
Logitech WingMan Joystick, Logitech WingMan Attack, Logitech WingMan Logitech WingMan Joystick, Logitech WingMan Attack, Logitech WingMan
@@ -288,7 +288,7 @@ supports:
* Gravis Xterminator DualControl * Gravis Xterminator DualControl
All these devices are autodetected, and you can even use any combination All these devices are autodetected, and you can even use any combination
of up to two of these pads either chained together or using an Y-cable on a of up to two of these pads either chained together or using a Y-cable on a
single gameport. single gameport.
GrIP MultiPort isn't supported yet. Gravis Stinger is a serial device and is GrIP MultiPort isn't supported yet. Gravis Stinger is a serial device and is
@@ -311,7 +311,7 @@ allow connecting analog joysticks to them, you'll need to load the analog
driver as well to handle the attached joysticks. driver as well to handle the attached joysticks.
The trackball should work with USB mousedev module as a normal mouse. See The trackball should work with USB mousedev module as a normal mouse. See
the USB documentation for how to setup an USB mouse. the USB documentation for how to setup a USB mouse.
ThrustMaster DirectConnect (BSP) ThrustMaster DirectConnect (BSP)
-------------------------------- --------------------------------
@@ -332,7 +332,7 @@ If you have one of these, contact me.
TMDC devices are autodetected, and thus no parameters to the module TMDC devices are autodetected, and thus no parameters to the module
are needed. Up to two TMDC devices can be connected to one gameport, using are needed. Up to two TMDC devices can be connected to one gameport, using
an Y-cable. a Y-cable.
Creative Labs Blaster Creative Labs Blaster
--------------------- ---------------------
@@ -342,7 +342,7 @@ the:
* Creative Blaster GamePad Cobra * Creative Blaster GamePad Cobra
Up to two of these can be used on a single gameport, using an Y-cable. Up to two of these can be used on a single gameport, using a Y-cable.
Genius Digital joysticks Genius Digital joysticks
------------------------ ------------------------
@@ -381,7 +381,7 @@ card, 16 in case you have two in your system.
Trident 4DWave / Aureal Vortex Trident 4DWave / Aureal Vortex
------------------------------ ------------------------------
Soundcards with a Trident 4DWave DX/NX or Aureal Vortex/Vortex2 chipsets Soundcards with a Trident 4DWave DX/NX or Aureal Vortex/Vortex2 chipset
provide an "Enhanced Game Port" mode where the soundcard handles polling the provide an "Enhanced Game Port" mode where the soundcard handles polling the
joystick. This mode is supported by the pcigame.c module. Once loaded the joystick. This mode is supported by the pcigame.c module. Once loaded the
analog driver can use the enhanced features of these gameports.. analog driver can use the enhanced features of these gameports..
@@ -454,7 +454,7 @@ Devices currently supported by spaceball.c are:
* SpaceTec SpaceBall 4000 FLX * SpaceTec SpaceBall 4000 FLX
In addition to having the spaceorb/spaceball and serport modules in the In addition to having the spaceorb/spaceball and serport modules in the
kernel, you also need to attach a serial port to it. to do that, run the kernel, you also need to attach a serial port to it. To do that, run the
inputattach program:: inputattach program::
inputattach --spaceorb /dev/tts/x & inputattach --spaceorb /dev/tts/x &
@@ -466,7 +466,7 @@ or::
where /dev/tts/x is the serial port which the device is connected to. After where /dev/tts/x is the serial port which the device is connected to. After
doing this, the device will be reported and will start working. doing this, the device will be reported and will start working.
There is one caveat with the SpaceOrb. The button #6, the on the bottom There is one caveat with the SpaceOrb. The button #6, the one on the bottom
side of the orb, although reported as an ordinary button, causes internal side of the orb, although reported as an ordinary button, causes internal
recentering of the spaceorb, moving the zero point to the position in which recentering of the spaceorb, moving the zero point to the position in which
the ball is at the moment of pressing the button. So, think first before the ball is at the moment of pressing the button. So, think first before
@@ -500,7 +500,7 @@ joy-magellan module. It currently supports only the:
* Magellan 3D * Magellan 3D
* Space Mouse * Space Mouse
models, the additional buttons on the 'Plus' versions are not supported yet. models; the additional buttons on the 'Plus' versions are not supported yet.
To use it, you need to attach the serial port to the driver using the:: To use it, you need to attach the serial port to the driver using the::
@@ -575,7 +575,7 @@ FAQ
:A: The device files don't exist. Create them (see section 2.2). :A: The device files don't exist. Create them (see section 2.2).
:Q: Is it possible to connect my old Atari/Commodore/Amiga/console joystick :Q: Is it possible to connect my old Atari/Commodore/Amiga/console joystick
or pad that uses a 9-pin D-type cannon connector to the serial port of my or pad that uses a 9-pin D-type Cannon connector to the serial port of my
PC? PC?
:A: Yes, it is possible, but it'll burn your serial port or the pad. It :A: Yes, it is possible, but it'll burn your serial port or the pad. It
won't work, of course. won't work, of course.

1
Documentation/process/changes.rst
View File

@@ -48,7 +48,6 @@ quota-tools 3.09 quota -V
PPP 2.4.0 pppd --version PPP 2.4.0 pppd --version
nfs-utils 1.0.5 showmount --version nfs-utils 1.0.5 showmount --version
procps 3.2.0 ps --version procps 3.2.0 ps --version
oprofile 0.9 oprofiled --version
udev 081 udevd --version udev 081 udevd --version
grub 0.93 grub --version || grub-install --version grub 0.93 grub --version || grub-install --version
mcelog 0.6 mcelog --version mcelog 0.6 mcelog --version

1
Documentation/riscv/index.rst
View File

@@ -6,6 +6,7 @@ RISC-V architecture
:maxdepth: 1 :maxdepth: 1
boot-image-header boot-image-header
vm-layout
pmu pmu
patch-acceptance patch-acceptance

63
Documentation/riscv/vm-layout.rst Normal file
View File

@@ -0,0 +1,63 @@
.. SPDX-License-Identifier: GPL-2.0
=====================================
Virtual Memory Layout on RISC-V Linux
=====================================
:Author: Alexandre Ghiti <alex@ghiti.fr>
:Date: 12 February 2021
This document describes the virtual memory layout used by the RISC-V Linux
Kernel.
RISC-V Linux Kernel 32bit
=========================
RISC-V Linux Kernel SV32
------------------------
TODO
RISC-V Linux Kernel 64bit
=========================
The RISC-V privileged architecture document states that the 64bit addresses
"must have bits 63–48 all equal to bit 47, or else a page-fault exception will
occur.": that splits the virtual address space into 2 halves separated by a very
big hole, the lower half is where the userspace resides, the upper half is where
the RISC-V Linux Kernel resides.
RISC-V Linux Kernel SV39
------------------------
::
========================================================================================================================
Start addr | Offset | End addr | Size | VM area description
========================================================================================================================
| | | |
0000000000000000 | 0 | 0000003fffffffff | 256 GB | user-space virtual memory, different per mm
__________________|____________|__________________|_________|___________________________________________________________
| | | |
0000004000000000 | +256 GB | ffffffbfffffffff | ~16M TB | ... huge, almost 64 bits wide hole of non-canonical
| | | | virtual memory addresses up to the -256 GB
| | | | starting offset of kernel mappings.
__________________|____________|__________________|_________|___________________________________________________________
|
| Kernel-space virtual memory, shared between all processes:
____________________________________________________________|___________________________________________________________
| | | |
ffffffc000000000 | -256 GB | ffffffc7ffffffff | 32 GB | kasan
ffffffcefee00000 | -196 GB | ffffffcefeffffff | 2 MB | fixmap
ffffffceff000000 | -196 GB | ffffffceffffffff | 16 MB | PCI io
ffffffcf00000000 | -196 GB | ffffffcfffffffff | 4 GB | vmemmap
ffffffd000000000 | -192 GB | ffffffdfffffffff | 64 GB | vmalloc/ioremap space
ffffffe000000000 | -128 GB | ffffffff7fffffff | 124 GB | direct mapping of all physical memory
__________________|____________|__________________|_________|____________________________________________________________
|
|
____________________________________________________________|____________________________________________________________
| | | |
ffffffff00000000 | -4 GB | ffffffff7fffffff | 2 GB | modules
ffffffff80000000 | -2 GB | ffffffffffffffff | 2 GB | kernel, BPF
__________________|____________|__________________|_________|____________________________________________________________

1
Documentation/translations/it_IT/process/changes.rst
View File

@@ -51,7 +51,6 @@ quota-tools 3.09 quota -V
PPP 2.4.0 pppd --version PPP 2.4.0 pppd --version
nfs-utils 1.0.5 showmount --version nfs-utils 1.0.5 showmount --version
procps 3.2.0 ps --version procps 3.2.0 ps --version
oprofile 0.9 oprofiled --version
udev 081 udevd --version udev 081 udevd --version
grub 0.93 grub --version || grub-install --version grub 0.93 grub --version || grub-install --version
mcelog 0.6 mcelog --version mcelog 0.6 mcelog --version

172
Documentation/translations/zh_CN/index.rst
View File

@@ -1,36 +1,184 @@
.. SPDX-License-Identifier: GPL-2.0
.. raw:: latex .. raw:: latex
\renewcommand\thesection* \renewcommand\thesection*
\renewcommand\thesubsection* \renewcommand\thesubsection*
.. _linux_doc_zh:
中文翻译 中文翻译
======== ========
这些手册包含有关如何开发内核的整体信息。内核社区非常庞大，一年下来有数千名开发
人员做出贡献。 与任何大型社区一样，知道如何完成任务将使得更改合并的过程变得更
加容易。
翻译计划: .. note::
内核中文文档欢迎任何翻译投稿，特别是关于内核用户和管理员指南部分。
**翻译计划:**
内核中文文档欢迎任何翻译投稿，特别是关于内核用户和管理员指南部分。
许可证文档
----------
下面的文档介绍了Linux内核源代码的许可证（GPLv2）、如何在源代码树中正确标记
单个文件的许可证、以及指向完整许可证文本的链接。
* Documentation/translations/zh_CN/process/license-rules.rst
用户文档
--------
下面的手册是为内核用户编写的——即那些试图让它在给定系统上以最佳方式工作的
用户。
.. toctree:: .. toctree::
:maxdepth: 2 :maxdepth: 2
admin-guide/index admin-guide/index
TODOList:
* kbuild/index
固件相关文档
------------
下列文档描述了内核需要的平台固件相关信息。
TODOList:
* firmware-guide/index
* devicetree/index
应用程序开发人员文档
--------------------
用户空间API手册涵盖了描述应用程序开发人员可见内核接口方面的文档。
TODOlist:
* userspace-api/index
内核开发简介
------------
这些手册包含有关如何开发内核的整体信息。内核社区非常庞大，一年下来有数千名
开发人员做出贡献。与任何大型社区一样，知道如何完成任务将使得更改合并的过程
变得更加容易。
.. toctree::
:maxdepth: 2
process/index process/index
dev-tools/index dev-tools/index
doc-guide/index doc-guide/index
kernel-hacking/index kernel-hacking/index
filesystems/index
arm64/index TODOList:
sound/index
cpu-freq/index * trace/index
mips/index * maintainer/index
iio/index * fault-injection/index
riscv/index * livepatch/index
* rust/index
内核API文档
-----------
以下手册从内核开发人员的角度详细介绍了特定的内核子系统是如何工作的。这里的
大部分信息都是直接从内核源代码获取的，并根据需要添加补充材料（或者至少是在
我们设法添加的时候——可能不是所有的都是有需要的）。
.. toctree::
:maxdepth: 2
core-api/index core-api/index
cpu-freq/index
iio/index
sound/index
filesystems/index
TODOList:
* driver-api/index
* locking/index
* accounting/index
* block/index
* cdrom/index
* ide/index
* fb/index
* fpga/index
* hid/index
* i2c/index
* isdn/index
* infiniband/index
* leds/index
* netlabel/index
* networking/index
* pcmcia/index
* power/index
* target/index
* timers/index
* spi/index
* w1/index
* watchdog/index
* virt/index
* input/index
* hwmon/index
* gpu/index
* security/index
* crypto/index
* vm/index
* bpf/index
* usb/index
* PCI/index
* scsi/index
* misc-devices/index
* scheduler/index
* mhi/index
体系结构无关文档
----------------
TODOList:
* asm-annotations
特定体系结构文档
----------------
.. toctree::
:maxdepth: 2
mips/index
arm64/index
riscv/index
openrisc/index openrisc/index
TODOList:
* arm/index
* ia64/index
* m68k/index
* nios2/index
* parisc/index
* powerpc/index
* s390/index
* sh/index
* sparc/index
* x86/index
* xtensa/index
其他文档
--------
有几份未排序的文档似乎不适合放在文档的其他部分，或者可能需要进行一些调整和/或
转换为reStructureText格式，也有可能太旧。
TODOList:
* staging/index
* watch_queue
目录和表格 目录和表格
---------- ----------

4
Documentation/x86/x86_64/5level-paging.rst
View File

@@ -6,9 +6,9 @@
Overview Overview
======== ========
Original x86-64 was limited by 4-level paing to 256 TiB of virtual address Original x86-64 was limited by 4-level paging to 256 TiB of virtual address
space and 64 TiB of physical address space. We are already bumping into space and 64 TiB of physical address space. We are already bumping into
this limit: some vendors offers servers with 64 TiB of memory today. this limit: some vendors offer servers with 64 TiB of memory today.
To overcome the limitation upcoming hardware will introduce support for To overcome the limitation upcoming hardware will introduce support for
5-level paging. It is a straight-forward extension of the current page 5-level paging. It is a straight-forward extension of the current page

43
MAINTAINERS
View File

@@ -3207,6 +3207,22 @@ F: Documentation/filesystems/bfs.rst
F: fs/bfs/ F: fs/bfs/
F: include/uapi/linux/bfs_fs.h F: include/uapi/linux/bfs_fs.h
BITMAP API
M: Yury Norov <yury.norov@gmail.com>
R: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
R: Rasmus Villemoes <linux@rasmusvillemoes.dk>
S: Maintained
F: include/asm-generic/bitops/find.h
F: include/linux/bitmap.h
F: lib/bitmap.c
F: lib/find_bit.c
F: lib/find_bit_benchmark.c
F: lib/test_bitmap.c
F: tools/include/asm-generic/bitops/find.h
F: tools/include/linux/bitmap.h
F: tools/lib/bitmap.c
F: tools/lib/find_bit.c
BLINKM RGB LED DRIVER BLINKM RGB LED DRIVER
M: Jan-Simon Moeller <jansimon.moeller@gmx.de> M: Jan-Simon Moeller <jansimon.moeller@gmx.de>
S: Maintained S: Maintained
@@ -8388,6 +8404,13 @@ S: Maintained
F: mm/hwpoison-inject.c F: mm/hwpoison-inject.c
F: mm/memory-failure.c F: mm/memory-failure.c
HYCON HY46XX TOUCHSCREEN SUPPORT
M: Giulio Benetti <giulio.benetti@benettiengineering.com>
L: linux-input@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/input/touchscreen/hycon,hy46xx.yaml
F: drivers/input/touchscreen/hycon-hy46xx.c
HYGON PROCESSOR SUPPORT HYGON PROCESSOR SUPPORT
M: Pu Wen <puwen@hygon.cn> M: Pu Wen <puwen@hygon.cn>
L: linux-kernel@vger.kernel.org L: linux-kernel@vger.kernel.org
@@ -9529,6 +9552,7 @@ F: fs/io-wq.h
F: fs/io_uring.c F: fs/io_uring.c
F: include/linux/io_uring.h F: include/linux/io_uring.h
F: include/uapi/linux/io_uring.h F: include/uapi/linux/io_uring.h
F: tools/io_uring/
IPMI SUBSYSTEM IPMI SUBSYSTEM
M: Corey Minyard <minyard@acm.org> M: Corey Minyard <minyard@acm.org>
@@ -10170,6 +10194,12 @@ S: Maintained
F: Documentation/devicetree/bindings/leds/backlight/kinetic,ktd253.yaml F: Documentation/devicetree/bindings/leds/backlight/kinetic,ktd253.yaml
F: drivers/video/backlight/ktd253-backlight.c F: drivers/video/backlight/ktd253-backlight.c
KTEST
M: Steven Rostedt <rostedt@goodmis.org>
M: John Hawley <warthog9@eaglescrag.net>
S: Maintained
F: tools/testing/ktest
L3MDEV L3MDEV
M: David Ahern <dsahern@kernel.org> M: David Ahern <dsahern@kernel.org>
L: netdev@vger.kernel.org L: netdev@vger.kernel.org
@@ -13977,6 +14007,14 @@ S: Maintained
F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
F: drivers/pci/controller/dwc/*imx6* F: drivers/pci/controller/dwc/*imx6*
PCI DRIVER FOR FU740
M: Paul Walmsley <paul.walmsley@sifive.com>
M: Greentime Hu <greentime.hu@sifive.com>
L: linux-pci@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml
F: drivers/pci/controller/dwc/pcie-fu740.c
PCI DRIVER FOR INTEL VOLUME MANAGEMENT DEVICE (VMD) PCI DRIVER FOR INTEL VOLUME MANAGEMENT DEVICE (VMD)
M: Jonathan Derrick <jonathan.derrick@intel.com> M: Jonathan Derrick <jonathan.derrick@intel.com>
L: linux-pci@vger.kernel.org L: linux-pci@vger.kernel.org
@@ -14184,7 +14222,6 @@ PCIE DRIVER FOR HISILICON
M: Zhou Wang <wangzhou1@hisilicon.com> M: Zhou Wang <wangzhou1@hisilicon.com>
L: linux-pci@vger.kernel.org L: linux-pci@vger.kernel.org
S: Maintained S: Maintained
F: Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
F: drivers/pci/controller/dwc/pcie-hisi.c F: drivers/pci/controller/dwc/pcie-hisi.c
PCIE DRIVER FOR HISILICON KIRIN PCIE DRIVER FOR HISILICON KIRIN
@@ -14204,6 +14241,7 @@ F: drivers/pci/controller/dwc/pcie-histb.c
PCIE DRIVER FOR MEDIATEK PCIE DRIVER FOR MEDIATEK
M: Ryder Lee <ryder.lee@mediatek.com> M: Ryder Lee <ryder.lee@mediatek.com>
M: Jianjun Wang <jianjun.wang@mediatek.com>
L: linux-pci@vger.kernel.org L: linux-pci@vger.kernel.org
L: linux-mediatek@lists.infradead.org L: linux-mediatek@lists.infradead.org
S: Supported S: Supported
@@ -15191,6 +15229,7 @@ F: include/linux/if_rmnet.h
QUALCOMM TSENS THERMAL DRIVER QUALCOMM TSENS THERMAL DRIVER
M: Amit Kucheria <amitk@kernel.org> M: Amit Kucheria <amitk@kernel.org>
M: Thara Gopinath <thara.gopinath@linaro.org>
L: linux-pm@vger.kernel.org L: linux-pm@vger.kernel.org
L: linux-arm-msm@vger.kernel.org L: linux-arm-msm@vger.kernel.org
S: Maintained S: Maintained
@@ -18095,7 +18134,7 @@ THERMAL/CPU_COOLING
M: Amit Daniel Kachhap <amit.kachhap@gmail.com> M: Amit Daniel Kachhap <amit.kachhap@gmail.com>
M: Daniel Lezcano <daniel.lezcano@linaro.org> M: Daniel Lezcano <daniel.lezcano@linaro.org>
M: Viresh Kumar <viresh.kumar@linaro.org> M: Viresh Kumar <viresh.kumar@linaro.org>
M: Javi Merino <javi.merino@kernel.org> R: Lukasz Luba <lukasz.luba@arm.com>
L: linux-pm@vger.kernel.org L: linux-pm@vger.kernel.org
S: Supported S: Supported
F: Documentation/driver-api/thermal/cpu-cooling-api.rst F: Documentation/driver-api/thermal/cpu-cooling-api.rst

5
arch/alpha/include/asm/io.h
View File

@@ -602,11 +602,6 @@ extern void outsl (unsigned long port, const void *src, unsigned long count);
*/ */
#define xlate_dev_mem_ptr(p) __va(p) #define xlate_dev_mem_ptr(p) __va(p)
/*
* Convert a virtual cached pointer to an uncached pointer
*/
#define xlate_dev_kmem_ptr(p) p
#endif /* __KERNEL__ */ #endif /* __KERNEL__ */
#endif /* __ALPHA_IO_H */ #endif /* __ALPHA_IO_H */

4
arch/alpha/kernel/pc873xx.c
View File

@@ -13,12 +13,12 @@ static char *pc873xx_names[] = {
static unsigned int base, model; static unsigned int base, model;
unsigned int __init pc873xx_get_base() unsigned int __init pc873xx_get_base(void)
{ {
return base; return base;
} }
char *__init pc873xx_get_model() char *__init pc873xx_get_model(void)
{ {
return pc873xx_names[model]; return pc873xx_names[model];
} }

1
arch/alpha/lib/csum_partial_copy.c
View File

@@ -13,6 +13,7 @@
#include <linux/types.h> #include <linux/types.h>
#include <linux/string.h> #include <linux/string.h>
#include <linux/uaccess.h> #include <linux/uaccess.h>
#include <net/checksum.h>
#define ldq_u(x,y) \ #define ldq_u(x,y) \

9
arch/arc/Kconfig
View File

@@ -6,6 +6,7 @@
config ARC config ARC
def_bool y def_bool y
select ARC_TIMERS select ARC_TIMERS
select ARCH_HAS_CACHE_LINE_SIZE
select ARCH_HAS_DEBUG_VM_PGTABLE select ARCH_HAS_DEBUG_VM_PGTABLE
select ARCH_HAS_DMA_PREP_COHERENT select ARCH_HAS_DMA_PREP_COHERENT
select ARCH_HAS_PTE_SPECIAL select ARCH_HAS_PTE_SPECIAL
@@ -28,6 +29,7 @@ config ARC
select GENERIC_SMP_IDLE_THREAD select GENERIC_SMP_IDLE_THREAD
select HAVE_ARCH_KGDB select HAVE_ARCH_KGDB
select HAVE_ARCH_TRACEHOOK select HAVE_ARCH_TRACEHOOK
select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARC_MMU_V4
select HAVE_DEBUG_STACKOVERFLOW select HAVE_DEBUG_STACKOVERFLOW
select HAVE_DEBUG_KMEMLEAK select HAVE_DEBUG_KMEMLEAK
select HAVE_FUTEX_CMPXCHG if FUTEX select HAVE_FUTEX_CMPXCHG if FUTEX
@@ -48,9 +50,6 @@ config ARC
select HAVE_ARCH_JUMP_LABEL if ISA_ARCV2 && !CPU_ENDIAN_BE32 select HAVE_ARCH_JUMP_LABEL if ISA_ARCV2 && !CPU_ENDIAN_BE32
select SET_FS select SET_FS
config ARCH_HAS_CACHE_LINE_SIZE
def_bool y
config TRACE_IRQFLAGS_SUPPORT config TRACE_IRQFLAGS_SUPPORT
def_bool y def_bool y
@@ -86,10 +85,6 @@ config STACKTRACE_SUPPORT
def_bool y def_bool y
select STACKTRACE select STACKTRACE
config HAVE_ARCH_TRANSPARENT_HUGEPAGE
def_bool y
depends on ARC_MMU_V4
menu "ARC Architecture Configuration" menu "ARC Architecture Configuration"
menu "ARC Platform/SoC/Board" menu "ARC Platform/SoC/Board"

10
arch/arm/Kconfig
View File

@@ -31,6 +31,7 @@ config ARM
select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
select ARCH_SUPPORTS_ATOMIC_RMW select ARCH_SUPPORTS_ATOMIC_RMW
select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE
select ARCH_USE_BUILTIN_BSWAP select ARCH_USE_BUILTIN_BSWAP
select ARCH_USE_CMPXCHG_LOCKREF select ARCH_USE_CMPXCHG_LOCKREF
select ARCH_USE_MEMTEST select ARCH_USE_MEMTEST
@@ -77,6 +78,7 @@ config ARM
select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
select HAVE_ARCH_THREAD_STRUCT_WHITELIST select HAVE_ARCH_THREAD_STRUCT_WHITELIST
select HAVE_ARCH_TRACEHOOK select HAVE_ARCH_TRACEHOOK
select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE
select HAVE_ARM_SMCCC if CPU_V7 select HAVE_ARM_SMCCC if CPU_V7
select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
select HAVE_CONTEXT_TRACKING select HAVE_CONTEXT_TRACKING
@@ -1511,14 +1513,6 @@ config HW_PERF_EVENTS
def_bool y def_bool y
depends on ARM_PMU depends on ARM_PMU
config SYS_SUPPORTS_HUGETLBFS
def_bool y
depends on ARM_LPAE
config HAVE_ARCH_TRANSPARENT_HUGEPAGE
def_bool y
depends on ARM_LPAE
config ARCH_WANT_GENERAL_HUGETLB config ARCH_WANT_GENERAL_HUGETLB
def_bool y def_bool y

4
arch/arm/boot/compressed/Makefile
View File

@@ -118,8 +118,8 @@ asflags-y := -DZIMAGE
# Supply kernel BSS size to the decompressor via a linker symbol. # Supply kernel BSS size to the decompressor via a linker symbol.
KBSS_SZ = $(shell echo $$(($$($(NM) $(obj)/../../../../vmlinux | \ KBSS_SZ = $(shell echo $$(($$($(NM) $(obj)/../../../../vmlinux | \
sed -n -e 's/^\([^ ]*\) [AB] __bss_start$$/-0x\1/p' \ sed -n -e 's/^\([^ ]*\) [ABD] __bss_start$$/-0x\1/p' \
-e 's/^\([^ ]*\) [AB] __bss_stop$$/+0x\1/p') )) ) -e 's/^\([^ ]*\) [ABD] __bss_stop$$/+0x\1/p') )) )
LDFLAGS_vmlinux = --defsym _kernel_bss_size=$(KBSS_SZ) LDFLAGS_vmlinux = --defsym _kernel_bss_size=$(KBSS_SZ)
# Supply ZRELADDR to the decompressor via a linker symbol. # Supply ZRELADDR to the decompressor via a linker symbol.
ifneq ($(CONFIG_AUTO_ZRELADDR),y) ifneq ($(CONFIG_AUTO_ZRELADDR),y)

4
arch/arm/boot/dts/rk3036.dtsi
View File

@@ -355,7 +355,6 @@
reg = <0x20050000 0x10>; reg = <0x20050000 0x10>;
#pwm-cells = <3>; #pwm-cells = <3>;
clocks = <&cru PCLK_PWM>; clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pwm0_pin>; pinctrl-0 = <&pwm0_pin>;
status = "disabled"; status = "disabled";
@@ -366,7 +365,6 @@
reg = <0x20050010 0x10>; reg = <0x20050010 0x10>;
#pwm-cells = <3>; #pwm-cells = <3>;
clocks = <&cru PCLK_PWM>; clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pwm1_pin>; pinctrl-0 = <&pwm1_pin>;
status = "disabled"; status = "disabled";
@@ -377,7 +375,6 @@
reg = <0x20050020 0x10>; reg = <0x20050020 0x10>;
#pwm-cells = <3>; #pwm-cells = <3>;
clocks = <&cru PCLK_PWM>; clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pwm2_pin>; pinctrl-0 = <&pwm2_pin>;
status = "disabled"; status = "disabled";
@@ -388,7 +385,6 @@
reg = <0x20050030 0x10>; reg = <0x20050030 0x10>;
#pwm-cells = <2>; #pwm-cells = <2>;
clocks = <&cru PCLK_PWM>; clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pwm3_pin>; pinctrl-0 = <&pwm3_pin>;
status = "disabled"; status = "disabled";

4
arch/arm/boot/dts/rk3288.dtsi
View File

@@ -679,7 +679,6 @@
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pwm0_pin>; pinctrl-0 = <&pwm0_pin>;
clocks = <&cru PCLK_RKPWM>; clocks = <&cru PCLK_RKPWM>;
clock-names = "pwm";
status = "disabled"; status = "disabled";
}; };
@@ -690,7 +689,6 @@
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pwm1_pin>; pinctrl-0 = <&pwm1_pin>;
clocks = <&cru PCLK_RKPWM>; clocks = <&cru PCLK_RKPWM>;
clock-names = "pwm";
status = "disabled"; status = "disabled";
}; };
@@ -701,7 +699,6 @@
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pwm2_pin>; pinctrl-0 = <&pwm2_pin>;
clocks = <&cru PCLK_RKPWM>; clocks = <&cru PCLK_RKPWM>;
clock-names = "pwm";
status = "disabled"; status = "disabled";
}; };
@@ -712,7 +709,6 @@
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pwm3_pin>; pinctrl-0 = <&pwm3_pin>;
clocks = <&cru PCLK_RKPWM>; clocks = <&cru PCLK_RKPWM>;
clock-names = "pwm";
status = "disabled"; status = "disabled";
}; };

1
arch/arm/configs/dove_defconfig
View File

@@ -63,7 +63,6 @@ CONFIG_INPUT_EVDEV=y
# CONFIG_MOUSE_PS2 is not set # CONFIG_MOUSE_PS2 is not set
# CONFIG_SERIO is not set # CONFIG_SERIO is not set
CONFIG_LEGACY_PTY_COUNT=16 CONFIG_LEGACY_PTY_COUNT=16
# CONFIG_DEVKMEM is not set
CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_RUNTIME_UARTS=2 CONFIG_SERIAL_8250_RUNTIME_UARTS=2

1
arch/arm/configs/footbridge_defconfig
View File

@@ -7,7 +7,6 @@ CONFIG_EXPERT=y
CONFIG_MODULES=y CONFIG_MODULES=y
CONFIG_ARCH_FOOTBRIDGE=y CONFIG_ARCH_FOOTBRIDGE=y
CONFIG_ARCH_CATS=y CONFIG_ARCH_CATS=y
CONFIG_ARCH_PERSONAL_SERVER=y
CONFIG_ARCH_EBSA285_HOST=y CONFIG_ARCH_EBSA285_HOST=y
CONFIG_ARCH_NETWINDER=y CONFIG_ARCH_NETWINDER=y
CONFIG_LEDS=y CONFIG_LEDS=y

1
arch/arm/configs/magician_defconfig
View File

@@ -72,7 +72,6 @@ CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_INPUT_MISC=y CONFIG_INPUT_MISC=y
CONFIG_INPUT_UINPUT=m CONFIG_INPUT_UINPUT=m
# CONFIG_SERIO is not set # CONFIG_SERIO is not set
# CONFIG_DEVKMEM is not set
CONFIG_SERIAL_PXA=y CONFIG_SERIAL_PXA=y
# CONFIG_LEGACY_PTYS is not set # CONFIG_LEGACY_PTYS is not set
# CONFIG_HW_RANDOM is not set # CONFIG_HW_RANDOM is not set

1
arch/arm/configs/moxart_defconfig
View File

@@ -79,7 +79,6 @@ CONFIG_INPUT_EVBUG=y
# CONFIG_SERIO is not set # CONFIG_SERIO is not set
# CONFIG_VT is not set # CONFIG_VT is not set
# CONFIG_LEGACY_PTYS is not set # CONFIG_LEGACY_PTYS is not set
# CONFIG_DEVKMEM is not set
CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=1 CONFIG_SERIAL_8250_NR_UARTS=1

1
arch/arm/configs/mps2_defconfig
View File

@@ -69,7 +69,6 @@ CONFIG_SMSC911X=y
# CONFIG_VT is not set # CONFIG_VT is not set
# CONFIG_LEGACY_PTYS is not set # CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_NONSTANDARD=y CONFIG_SERIAL_NONSTANDARD=y
# CONFIG_DEVKMEM is not set
CONFIG_SERIAL_MPS2_UART_CONSOLE=y CONFIG_SERIAL_MPS2_UART_CONSOLE=y
CONFIG_SERIAL_MPS2_UART=y CONFIG_SERIAL_MPS2_UART=y
# CONFIG_HW_RANDOM is not set # CONFIG_HW_RANDOM is not set

1
arch/arm/configs/mvebu_v5_defconfig
View File

@@ -100,7 +100,6 @@ CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_GPIO=y CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set # CONFIG_INPUT_MOUSE is not set
CONFIG_LEGACY_PTY_COUNT=16 CONFIG_LEGACY_PTY_COUNT=16
# CONFIG_DEVKMEM is not set
CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_RUNTIME_UARTS=2 CONFIG_SERIAL_8250_RUNTIME_UARTS=2

1
arch/arm/configs/xcep_defconfig
View File

@@ -53,7 +53,6 @@ CONFIG_NET_ETHERNET=y
# CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set # CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set # CONFIG_SERIO is not set
# CONFIG_DEVKMEM is not set
CONFIG_SERIAL_PXA=y CONFIG_SERIAL_PXA=y
CONFIG_SERIAL_PXA_CONSOLE=y CONFIG_SERIAL_PXA_CONSOLE=y
# CONFIG_LEGACY_PTYS is not set # CONFIG_LEGACY_PTYS is not set

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