PCI: tegra194: Extend Endpoint mode support
Since only Controller-5 can be used in the Endpoint mode in P2972-0000 platform, support is available only for Controller-5. Extend that support by enabling the Endpoint mode capable controller during initialization which otherwise is not required if it is only Controller-5. Link: https://lore.kernel.org/r/20220721142052.25971-16-vidyas@nvidia.com Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
This commit is contained in:
parent
e05fd6ae77
commit
f899983f71
@ -1650,6 +1650,13 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
|
||||
return;
|
||||
}
|
||||
|
||||
ret = tegra_pcie_bpmp_set_ctrl_state(pcie, true);
|
||||
if (ret) {
|
||||
dev_err(pcie->dev, "Failed to enable controller %u: %d\n",
|
||||
pcie->cid, ret);
|
||||
goto fail_set_ctrl_state;
|
||||
}
|
||||
|
||||
ret = tegra_pcie_bpmp_set_pll_state(pcie, true);
|
||||
if (ret) {
|
||||
dev_err(dev, "Failed to init UPHY for PCIe EP: %d\n", ret);
|
||||
@ -1798,6 +1805,8 @@ fail_core_apb_rst:
|
||||
fail_core_clk_enable:
|
||||
tegra_pcie_bpmp_set_pll_state(pcie, false);
|
||||
fail_pll_init:
|
||||
tegra_pcie_bpmp_set_ctrl_state(pcie, false);
|
||||
fail_set_ctrl_state:
|
||||
pm_runtime_put_sync(dev);
|
||||
}
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user