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iwlagn: scd memory boundary

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Assign memory boundary for SCD context, tx status and translation table

Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>
This commit is contained in:
Wey-Yi Guy 2011-06-28 08:01:12 -07:00
parent 02aca585f5
commit f86af7ba82
2 changed files with 19 additions and 8 deletions
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8
drivers/net/wireless/iwlwifi/iwl-agn-ucode.c
View File

@ -386,11 +386,13 @@ static int iwlagn_alive_notify(struct iwl_priv *priv)
spin_lock_irqsave(&priv->lock, flags); spin_lock_irqsave(&priv->lock, flags);
priv->scd_base_addr = iwl_read_prph(priv, IWLAGN_SCD_SRAM_BASE_ADDR); priv->scd_base_addr = iwl_read_prph(priv, IWLAGN_SCD_SRAM_BASE_ADDR);
a = priv->scd_base_addr + IWLAGN_SCD_CONTEXT_DATA_OFFSET; a = priv->scd_base_addr + IWLAGN_SCD_CONTEXT_MEM_LOWER_BOUND;
for (; a < priv->scd_base_addr + IWLAGN_SCD_TX_STTS_BITMAP_OFFSET; /* reset conext data memory */
for (; a < priv->scd_base_addr + IWLAGN_SCD_CONTEXT_MEM_UPPER_BOUND;
a += 4) a += 4)
iwl_write_targ_mem(priv, a, 0); iwl_write_targ_mem(priv, a, 0);
for (; a < priv->scd_base_addr + IWLAGN_SCD_TRANSLATE_TBL_OFFSET; /* reset tx status memory */
for (; a < priv->scd_base_addr + IWLAGN_SCD_TX_STTS_MEM_UPPER_BOUND;
a += 4) a += 4)
iwl_write_targ_mem(priv, a, 0); iwl_write_targ_mem(priv, a, 0);
for (; a < priv->scd_base_addr + for (; a < priv->scd_base_addr +

19
drivers/net/wireless/iwlwifi/iwl-prph.h
View File

@ -168,6 +168,7 @@
* the scheduler (especially for queue #4/#9, the command queue, otherwise * the scheduler (especially for queue #4/#9, the command queue, otherwise
* the driver can't issue commands!): * the driver can't issue commands!):
*/ */
#define SCD_MEM_LOWER_BOUND (0x0000)
/** /**
* Max Tx window size is the max number of contiguous TFDs that the scheduler * Max Tx window size is the max number of contiguous TFDs that the scheduler
@ -197,15 +198,23 @@
#define IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) #define IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16)
#define IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) #define IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000)
#define IWLAGN_SCD_CONTEXT_DATA_OFFSET (0x600) /* Context Data */
#define IWLAGN_SCD_TX_STTS_BITMAP_OFFSET (0x7B1) #define IWLAGN_SCD_CONTEXT_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x600)
#define IWLAGN_SCD_TRANSLATE_TBL_OFFSET (0x7E0) #define IWLAGN_SCD_CONTEXT_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x6A0)
/* Tx status */
#define IWLAGN_SCD_TX_STTS_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x6A0)
#define IWLAGN_SCD_TX_STTS_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x7E0)
/* Translation Data */
#define IWLAGN_SCD_TRANS_TBL_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x7E0)
#define IWLAGN_SCD_TRANS_TBL_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x808)
#define IWLAGN_SCD_CONTEXT_QUEUE_OFFSET(x)\ #define IWLAGN_SCD_CONTEXT_QUEUE_OFFSET(x)\
(IWLAGN_SCD_CONTEXT_DATA_OFFSET + ((x) * 8)) (IWLAGN_SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8))
#define IWLAGN_SCD_TRANSLATE_TBL_OFFSET_QUEUE(x) \ #define IWLAGN_SCD_TRANSLATE_TBL_OFFSET_QUEUE(x) \
((IWLAGN_SCD_TRANSLATE_TBL_OFFSET + ((x) * 2)) & 0xfffc) ((IWLAGN_SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc)
#define IWLAGN_SCD_QUEUECHAIN_SEL_ALL(priv) \ #define IWLAGN_SCD_QUEUECHAIN_SEL_ALL(priv) \
(((1<<(priv)->hw_params.max_txq_num) - 1) &\ (((1<<(priv)->hw_params.max_txq_num) - 1) &\