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drm/amd/display: Check for flip pending before locking pipes

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[Why]
When running games or benchmarking with v-sync disabled, disabling
a plane (which is v-sync) can cause underflow. This is caused by
flips pending before pipe locking being applied after locks are
released and pipes could have been re-arranged or disconnected. This
could potentially apply a flip on incorrect pipe. Also, previous logic
of always locking pipes was unnecessary.

[How]
Only lock the pipes when there is a pipe being disabled to increase
efficiency. Before the pipes are locked, check that any pending flips
are cleared to ensure the flips are applied to the correct pipe.

Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Acked-by: Eryk Brol <eryk.brol@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Aric Cyr
2020-09-18 11:45:04 -04:00
committed by Alex Deucher
parent 6fbd1e1710
commit f7fb81a18f
4 changed files with 89 additions and 84 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
drivers/gpu/drm/amd/display/dc/core/dc.c
View File

@@ -2383,7 +2383,6 @@ static void commit_planes_for_stream(struct dc *dc,
enum surface_update_type update_type,
struct dc_state *context)
{
bool mpcc_disconnected = false;
int i, j;
struct pipe_ctx *top_pipe_to_program = NULL;
@@ -2414,14 +2413,8 @@ static void commit_planes_for_stream(struct dc *dc,
context_clock_trace(dc, context);
}
if (update_type != UPDATE_TYPE_FAST && dc->hwss.interdependent_update_lock &&
dc->hwss.disconnect_pipes && dc->hwss.wait_for_pending_cleared){
dc->hwss.interdependent_update_lock(dc, context, true);
mpcc_disconnected = dc->hwss.disconnect_pipes(dc, context);
dc->hwss.interdependent_update_lock(dc, context, false);
if (mpcc_disconnected)
dc->hwss.wait_for_pending_cleared(dc, context);
}
if (update_type != UPDATE_TYPE_FAST && dc->hwss.interdependent_update_lock && dc->hwss.wait_for_pending_cleared)
dc->hwss.disconnect_pipes(dc, context);
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

26
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
View File

@@ -2761,17 +2761,19 @@ static struct pipe_ctx *dcn10_find_top_pipe_for_stream(
return NULL;
}
bool dcn10_disconnect_pipes(
void dcn10_disconnect_pipes(
struct dc *dc,
struct dc_state *context)
{
bool disconnect_pipes[MAX_PIPES] = {0};
bool found_pipe = false;
int i, j;
struct dce_hwseq *hws = dc->hwseq;
struct dc_state *old_ctx = dc->current_state;
bool mpcc_disconnected = false;
bool plane_disabled = false;
struct pipe_ctx *old_pipe;
struct pipe_ctx *new_pipe;
DC_LOGGER_INIT(dc->ctx->logger);
/* Set pipe update flags and lock pipes */
@@ -2819,18 +2821,21 @@ bool dcn10_disconnect_pipes(
}
}
plane_disabled = true;
// Disconnect if the top pipe lost it's pipe split
if (found_pipe && !context->res_ctx.pipe_ctx[j].bottom_pipe) {
hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);
mpcc_disconnected = true;
disconnect_pipes[i] = true;
}
}
found_pipe = false;
}
}
if (mpcc_disconnected) {
if (plane_disabled) {
dc->hwss.wait_for_pending_cleared(dc, context);
dc->hwss.interdependent_update_lock(dc, context, true);
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
@@ -2840,6 +2845,11 @@ bool dcn10_disconnect_pipes(
if (!pipe_ctx || !plane_state || !pipe_ctx->stream)
continue;
if (disconnect_pipes[i]) {
hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);
}
// Only update scaler and viewport here if we lose a pipe split.
// This is to prevent half the screen from being black when we
// unlock after disconnecting MPCC.
@@ -2873,8 +2883,10 @@ bool dcn10_disconnect_pipes(
}
}
}
dc->hwss.interdependent_update_lock(dc, context, false);
dc->hwss.wait_for_pending_cleared(dc, context);
}
return mpcc_disconnected;
}
void dcn10_wait_for_pending_cleared(struct dc *dc,

2
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
View File

@@ -194,7 +194,7 @@ void dcn10_get_surface_visual_confirm_color(
void dcn10_get_hdr_visual_confirm_color(
struct pipe_ctx *pipe_ctx,
struct tg_color *color);
bool dcn10_disconnect_pipes(
void dcn10_disconnect_pipes(
struct dc *dc,
struct dc_state *context);

2
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
View File

@@ -67,7 +67,7 @@ struct hw_sequencer_funcs {
int num_planes, struct dc_state *context);
void (*program_front_end_for_ctx)(struct dc *dc,
struct dc_state *context);
bool (*disconnect_pipes)(struct dc *dc,
void (*disconnect_pipes)(struct dc *dc,
struct dc_state *context);
void (*wait_for_pending_cleared)(struct dc *dc,
struct dc_state *context);