perf tools fixes for v5.19: 4th batch
- Fix SIGSEGV when processing syscall args in perf.data files in 'perf trace'.
- Sync kvm, msr-index and cpufeatures headers with the kernel sources.
- Fix 'convert perf time to TSC' 'perf test':
- No need to open events twice.
- Fix finding correct event on hybrid systems.
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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Merge tag 'perf-tools-fixes-for-v5.19-2022-07-17' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux
Pull perf tools fixes from Arnaldo Carvalho de Melo:
- Fix SIGSEGV when processing syscall args in perf.data files in 'perf
trace'
- Sync kvm, msr-index and cpufeatures headers with the kernel sources
- Fix 'convert perf time to TSC' 'perf test':
- No need to open events twice
- Fix finding correct event on hybrid systems
* tag 'perf-tools-fixes-for-v5.19-2022-07-17' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux:
perf trace: Fix SIGSEGV when processing syscall args
perf tests: Fix Convert perf time to TSC test for hybrid
perf tests: Stop Convert perf time to TSC test opening events twice
tools arch x86: Sync the msr-index.h copy with the kernel sources
tools headers cpufeatures: Sync with the kernel sources
tools headers UAPI: Sync linux/kvm.h with the kernel sources
This commit is contained in:
Linus Torvalds
commit
f7f4da303d
@ -203,8 +203,8 @@
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#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */
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#define X86_FEATURE_XCOMPACTED ( 7*32+10) /* "" Use compacted XSTATE (XSAVES or XSAVEC) */
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#define X86_FEATURE_PTI ( 7*32+11) /* Kernel Page Table Isolation enabled */
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#define X86_FEATURE_RETPOLINE ( 7*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */
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#define X86_FEATURE_RETPOLINE_LFENCE ( 7*32+13) /* "" Use LFENCE for Spectre variant 2 */
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#define X86_FEATURE_KERNEL_IBRS ( 7*32+12) /* "" Set/clear IBRS on kernel entry/exit */
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#define X86_FEATURE_RSB_VMEXIT ( 7*32+13) /* "" Fill RSB on VM-Exit */
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#define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */
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#define X86_FEATURE_CDP_L2 ( 7*32+15) /* Code and Data Prioritization L2 */
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#define X86_FEATURE_MSR_SPEC_CTRL ( 7*32+16) /* "" MSR SPEC_CTRL is implemented */
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@ -296,6 +296,12 @@
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#define X86_FEATURE_PER_THREAD_MBA (11*32+ 7) /* "" Per-thread Memory Bandwidth Allocation */
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#define X86_FEATURE_SGX1 (11*32+ 8) /* "" Basic SGX */
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#define X86_FEATURE_SGX2 (11*32+ 9) /* "" SGX Enclave Dynamic Memory Management (EDMM) */
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#define X86_FEATURE_ENTRY_IBPB (11*32+10) /* "" Issue an IBPB on kernel entry */
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#define X86_FEATURE_RRSBA_CTRL (11*32+11) /* "" RET prediction control */
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#define X86_FEATURE_RETPOLINE (11*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */
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#define X86_FEATURE_RETPOLINE_LFENCE (11*32+13) /* "" Use LFENCE for Spectre variant 2 */
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#define X86_FEATURE_RETHUNK (11*32+14) /* "" Use REturn THUNK */
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#define X86_FEATURE_UNRET (11*32+15) /* "" AMD BTB untrain return */
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/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
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#define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */
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@ -316,6 +322,7 @@
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#define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */
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#define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */
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#define X86_FEATURE_CPPC (13*32+27) /* Collaborative Processor Performance Control */
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#define X86_FEATURE_BTC_NO (13*32+29) /* "" Not vulnerable to Branch Type Confusion */
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#define X86_FEATURE_BRS (13*32+31) /* Branch Sampling available */
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/* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */
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@ -447,5 +454,6 @@
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#define X86_BUG_ITLB_MULTIHIT X86_BUG(23) /* CPU may incur MCE during certain page attribute changes */
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#define X86_BUG_SRBDS X86_BUG(24) /* CPU may leak RNG bits if not mitigated */
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#define X86_BUG_MMIO_STALE_DATA X86_BUG(25) /* CPU is affected by Processor MMIO Stale Data vulnerabilities */
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#define X86_BUG_RETBLEED X86_BUG(26) /* CPU is affected by RETBleed */
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#endif /* _ASM_X86_CPUFEATURES_H */
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@ -50,6 +50,25 @@
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# define DISABLE_PTI (1 << (X86_FEATURE_PTI & 31))
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#endif
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#ifdef CONFIG_RETPOLINE
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# define DISABLE_RETPOLINE 0
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#else
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# define DISABLE_RETPOLINE ((1 << (X86_FEATURE_RETPOLINE & 31)) | \
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(1 << (X86_FEATURE_RETPOLINE_LFENCE & 31)))
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#endif
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#ifdef CONFIG_RETHUNK
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# define DISABLE_RETHUNK 0
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#else
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# define DISABLE_RETHUNK (1 << (X86_FEATURE_RETHUNK & 31))
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#endif
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#ifdef CONFIG_CPU_UNRET_ENTRY
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# define DISABLE_UNRET 0
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#else
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# define DISABLE_UNRET (1 << (X86_FEATURE_UNRET & 31))
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#endif
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#ifdef CONFIG_INTEL_IOMMU_SVM
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# define DISABLE_ENQCMD 0
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#else
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@ -82,7 +101,7 @@
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#define DISABLED_MASK8 (DISABLE_TDX_GUEST)
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#define DISABLED_MASK9 (DISABLE_SGX)
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#define DISABLED_MASK10 0
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#define DISABLED_MASK11 0
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#define DISABLED_MASK11 (DISABLE_RETPOLINE|DISABLE_RETHUNK|DISABLE_UNRET)
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#define DISABLED_MASK12 0
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#define DISABLED_MASK13 0
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#define DISABLED_MASK14 0
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@ -95,6 +95,7 @@
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#define MSR_IA32_ARCH_CAPABILITIES 0x0000010a
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#define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */
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#define ARCH_CAP_IBRS_ALL BIT(1) /* Enhanced IBRS support */
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#define ARCH_CAP_RSBA BIT(2) /* RET may use alternative branch predictors */
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#define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3) /* Skip L1D flush on vmentry */
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#define ARCH_CAP_SSB_NO BIT(4) /*
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* Not susceptible to Speculative Store Bypass
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@ -576,6 +577,9 @@
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/* Fam 17h MSRs */
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#define MSR_F17H_IRPERF 0xc00000e9
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#define MSR_ZEN2_SPECTRAL_CHICKEN 0xc00110e3
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#define MSR_ZEN2_SPECTRAL_CHICKEN_BIT BIT_ULL(1)
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/* Fam 16h MSRs */
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#define MSR_F16H_L2I_PERF_CTL 0xc0010230
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#define MSR_F16H_L2I_PERF_CTR 0xc0010231
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@ -2083,6 +2083,7 @@ struct kvm_stats_header {
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#define KVM_STATS_UNIT_BYTES (0x1 << KVM_STATS_UNIT_SHIFT)
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#define KVM_STATS_UNIT_SECONDS (0x2 << KVM_STATS_UNIT_SHIFT)
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#define KVM_STATS_UNIT_CYCLES (0x3 << KVM_STATS_UNIT_SHIFT)
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#define KVM_STATS_UNIT_BOOLEAN (0x4 << KVM_STATS_UNIT_SHIFT)
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#define KVM_STATS_UNIT_MAX KVM_STATS_UNIT_CYCLES
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#define KVM_STATS_BASE_SHIFT 8
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@ -4280,6 +4280,7 @@ static int trace__replay(struct trace *trace)
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goto out;
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evsel = evlist__find_tracepoint_by_name(session->evlist, "raw_syscalls:sys_enter");
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trace->syscalls.events.sys_enter = evsel;
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/* older kernels have syscalls tp versus raw_syscalls */
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if (evsel == NULL)
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evsel = evlist__find_tracepoint_by_name(session->evlist, "syscalls:sys_enter");
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@ -4292,6 +4293,7 @@ static int trace__replay(struct trace *trace)
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}
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evsel = evlist__find_tracepoint_by_name(session->evlist, "raw_syscalls:sys_exit");
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trace->syscalls.events.sys_exit = evsel;
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if (evsel == NULL)
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evsel = evlist__find_tracepoint_by_name(session->evlist, "syscalls:sys_exit");
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if (evsel &&
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@ -20,8 +20,6 @@
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#include "tsc.h"
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#include "mmap.h"
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#include "tests.h"
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#include "pmu.h"
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#include "pmu-hybrid.h"
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/*
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* Except x86_64/i386 and Arm64, other archs don't support TSC in perf. Just
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@ -106,28 +104,21 @@ static int test__perf_time_to_tsc(struct test_suite *test __maybe_unused, int su
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evlist__config(evlist, &opts, NULL);
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evsel = evlist__first(evlist);
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evsel->core.attr.comm = 1;
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evsel->core.attr.disabled = 1;
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evsel->core.attr.enable_on_exec = 0;
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/*
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* For hybrid "cycles:u", it creates two events.
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* Init the second evsel here.
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*/
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if (perf_pmu__has_hybrid() && perf_pmu__hybrid_mounted("cpu_atom")) {
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evsel = evsel__next(evsel);
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/* For hybrid "cycles:u", it creates two events */
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evlist__for_each_entry(evlist, evsel) {
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evsel->core.attr.comm = 1;
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evsel->core.attr.disabled = 1;
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evsel->core.attr.enable_on_exec = 0;
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}
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if (evlist__open(evlist) == -ENOENT) {
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err = TEST_SKIP;
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ret = evlist__open(evlist);
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if (ret < 0) {
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if (ret == -ENOENT)
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err = TEST_SKIP;
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else
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pr_debug("evlist__open() failed\n");
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goto out_err;
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}
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CHECK__(evlist__open(evlist));
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CHECK__(evlist__mmap(evlist, UINT_MAX));
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@ -167,10 +158,12 @@ static int test__perf_time_to_tsc(struct test_suite *test __maybe_unused, int su
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goto next_event;
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if (strcmp(event->comm.comm, comm1) == 0) {
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CHECK_NOT_NULL__(evsel = evlist__event2evsel(evlist, event));
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CHECK__(evsel__parse_sample(evsel, event, &sample));
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comm1_time = sample.time;
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}
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if (strcmp(event->comm.comm, comm2) == 0) {
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CHECK_NOT_NULL__(evsel = evlist__event2evsel(evlist, event));
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CHECK__(evsel__parse_sample(evsel, event, &sample));
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comm2_time = sample.time;
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}
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