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pinctrl: renesas: r8a77965: Add vin4_g8 and vin5_high8 pins

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This patch adds vin4_g8 and vin5_high8 support to the R8A77965 SoC.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Link: https://lore.kernel.org/r/20210309114930.2433711-5-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Niklas Söderlund 2021-03-09 12:49:30 +01:00 committed by Geert Uytterhoeven
parent 2a9e4f74cd
commit f7adcca27e
1 changed files with 33 additions and 1 deletions
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34
drivers/pinctrl/renesas/pfc-r8a77965.c
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@ -4337,6 +4337,20 @@ static const union vin_data vin4_data_b_mux = {
}, },
}; };
static const unsigned int vin4_g8_pins[] = {
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
};
static const unsigned int vin4_g8_mux[] = {
VI4_DATA8_MARK, VI4_DATA9_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
};
static const unsigned int vin4_sync_pins[] = { static const unsigned int vin4_sync_pins[] = {
/* VSYNC_N, HSYNC_N */ /* VSYNC_N, HSYNC_N */
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
@ -4397,6 +4411,20 @@ static const union vin_data16 vin5_data_mux = {
}, },
}; };
static const unsigned int vin5_high8_pins[] = {
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
};
static const unsigned int vin5_high8_mux[] = {
VI5_DATA8_MARK, VI5_DATA9_MARK,
VI5_DATA10_MARK, VI5_DATA11_MARK,
VI5_DATA12_MARK, VI5_DATA13_MARK,
VI5_DATA14_MARK, VI5_DATA15_MARK,
};
static const unsigned int vin5_sync_pins[] = { static const unsigned int vin5_sync_pins[] = {
/* VSYNC_N, HSYNC_N */ /* VSYNC_N, HSYNC_N */
RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
@ -4431,7 +4459,7 @@ static const unsigned int vin5_clk_mux[] = {
}; };
static const struct { static const struct {
struct sh_pfc_pin_group common[324]; struct sh_pfc_pin_group common[326];
#ifdef CONFIG_PINCTRL_PFC_R8A77965 #ifdef CONFIG_PINCTRL_PFC_R8A77965
struct sh_pfc_pin_group automotive[30]; struct sh_pfc_pin_group automotive[30];
#endif #endif
@ -4749,6 +4777,7 @@ static const struct {
SH_PFC_PIN_GROUP(vin4_data18_b), SH_PFC_PIN_GROUP(vin4_data18_b),
VIN_DATA_PIN_GROUP(vin4_data, 20, _b), VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
VIN_DATA_PIN_GROUP(vin4_data, 24, _b), VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
SH_PFC_PIN_GROUP(vin4_g8),
SH_PFC_PIN_GROUP(vin4_sync), SH_PFC_PIN_GROUP(vin4_sync),
SH_PFC_PIN_GROUP(vin4_field), SH_PFC_PIN_GROUP(vin4_field),
SH_PFC_PIN_GROUP(vin4_clkenb), SH_PFC_PIN_GROUP(vin4_clkenb),
@ -4757,6 +4786,7 @@ static const struct {
VIN_DATA_PIN_GROUP(vin5_data, 10), VIN_DATA_PIN_GROUP(vin5_data, 10),
VIN_DATA_PIN_GROUP(vin5_data, 12), VIN_DATA_PIN_GROUP(vin5_data, 12),
VIN_DATA_PIN_GROUP(vin5_data, 16), VIN_DATA_PIN_GROUP(vin5_data, 16),
SH_PFC_PIN_GROUP(vin5_high8),
SH_PFC_PIN_GROUP(vin5_sync), SH_PFC_PIN_GROUP(vin5_sync),
SH_PFC_PIN_GROUP(vin5_field), SH_PFC_PIN_GROUP(vin5_field),
SH_PFC_PIN_GROUP(vin5_clkenb), SH_PFC_PIN_GROUP(vin5_clkenb),
@ -5307,6 +5337,7 @@ static const char * const vin4_groups[] = {
"vin4_data18_b", "vin4_data18_b",
"vin4_data20_b", "vin4_data20_b",
"vin4_data24_b", "vin4_data24_b",
"vin4_g8",
"vin4_sync", "vin4_sync",
"vin4_field", "vin4_field",
"vin4_clkenb", "vin4_clkenb",
@ -5318,6 +5349,7 @@ static const char * const vin5_groups[] = {
"vin5_data10", "vin5_data10",
"vin5_data12", "vin5_data12",
"vin5_data16", "vin5_data16",
"vin5_high8",
"vin5_sync", "vin5_sync",
"vin5_field", "vin5_field",
"vin5_clkenb", "vin5_clkenb",