leandrof/linux
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

drm/i915/glk: Update Port PLL enable sequence for Geminilkae

Browse Source 
Add steps for enabling and disabling Port PLL as per bspec.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1480667037-11215-6-git-send-email-ander.conselvan.de.oliveira@intel.com
This commit is contained in:
Madhav Chauhan 2016-12-02 10:23:53 +02:00 committed by Ander Conselvan de Oliveira
parent 51b3ee35af
commit f7044dd904
2 changed files with 22 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/i915/i915_reg.h
View File

@ -1574,6 +1574,8 @@ enum skl_disp_power_wells {
#define PORT_PLL_ENABLE (1 << 31)
#define PORT_PLL_LOCK (1 << 30)
#define PORT_PLL_REF_SEL (1 << 27)
#define PORT_PLL_POWER_ENABLE (1 << 26)
#define PORT_PLL_POWER_STATE (1 << 25)
#define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
#define _PORT_PLL_EBB_0_A 0x162034

20
drivers/gpu/drm/i915/intel_dpll_mgr.c
View File

@ -1380,6 +1380,16 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
temp |= PORT_PLL_REF_SEL;
I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
if (IS_GEMINILAKE(dev_priv)) {
temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
temp |= PORT_PLL_POWER_ENABLE;
I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
if (wait_for_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
PORT_PLL_POWER_STATE), 200))
DRM_ERROR("Power state not set for PLL:%d\n", port);
}
/* Disable 10 bit clock */
temp = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch));
temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
@ -1485,6 +1495,16 @@ static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
temp &= ~PORT_PLL_ENABLE;
I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
POSTING_READ(BXT_PORT_PLL_ENABLE(port));
if (IS_GEMINILAKE(dev_priv)) {
temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
temp &= ~PORT_PLL_POWER_ENABLE;
I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
if (wait_for_us(!(I915_READ(BXT_PORT_PLL_ENABLE(port)) &
PORT_PLL_POWER_STATE), 200))
DRM_ERROR("Power state not reset for PLL:%d\n", port);
}
}
static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,