crypto: inside-secure - add support for using the EIP197 without vendor firmware
Until now, the inside-secure driver required a set of firmware images supplied by the silicon vendor, typically under NDA, to be present in /lib/firmware/inside-secure in order to be able to function. This patch removes the dependence on this official vendor firmware by falling back to generic "mini" FW - developed specifically for this driver - that can be provided under GPL 2.0 through linux-firmwares. Signed-off-by: Pascal van Leeuwen <pvanleeuwen@verimatrix.com> Acked-by: Antoine Tenart <antoine.tenart@bootlin.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Pascal van Leeuwen
Herbert Xu
parent
625f269a5a
commit
f6cc45c854
@ -108,44 +108,143 @@ static void eip197_trc_cache_init(struct safexcel_crypto_priv *priv)
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writel(val, priv->base + EIP197_TRC_PARAMS);
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}
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static void eip197_write_firmware(struct safexcel_crypto_priv *priv,
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const struct firmware *fw, int pe, u32 ctrl,
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u32 prog_en)
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static void eip197_init_firmware(struct safexcel_crypto_priv *priv)
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{
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int pe, i;
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u32 val;
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for (pe = 0; pe < priv->config.pes; pe++) {
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/* Configure the token FIFO's */
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writel(3, EIP197_PE(priv) + EIP197_PE_ICE_PUTF_CTRL(pe));
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writel(0, EIP197_PE(priv) + EIP197_PE_ICE_PPTF_CTRL(pe));
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/* Clear the ICE scratchpad memory */
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val = readl(EIP197_PE(priv) + EIP197_PE_ICE_SCRATCH_CTRL(pe));
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val |= EIP197_PE_ICE_SCRATCH_CTRL_CHANGE_TIMER |
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EIP197_PE_ICE_SCRATCH_CTRL_TIMER_EN |
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EIP197_PE_ICE_SCRATCH_CTRL_SCRATCH_ACCESS |
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EIP197_PE_ICE_SCRATCH_CTRL_CHANGE_ACCESS;
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writel(val, EIP197_PE(priv) + EIP197_PE_ICE_SCRATCH_CTRL(pe));
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/* clear the scratchpad RAM using 32 bit writes only */
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for (i = 0; i < EIP197_NUM_OF_SCRATCH_BLOCKS; i++)
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writel(0, EIP197_PE(priv) +
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EIP197_PE_ICE_SCRATCH_RAM(pe) + (i<<2));
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/* Reset the IFPP engine to make its program mem accessible */
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writel(EIP197_PE_ICE_x_CTRL_SW_RESET |
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EIP197_PE_ICE_x_CTRL_CLR_ECC_CORR |
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EIP197_PE_ICE_x_CTRL_CLR_ECC_NON_CORR,
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EIP197_PE(priv) + EIP197_PE_ICE_FPP_CTRL(pe));
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/* Reset the IPUE engine to make its program mem accessible */
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writel(EIP197_PE_ICE_x_CTRL_SW_RESET |
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EIP197_PE_ICE_x_CTRL_CLR_ECC_CORR |
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EIP197_PE_ICE_x_CTRL_CLR_ECC_NON_CORR,
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EIP197_PE(priv) + EIP197_PE_ICE_PUE_CTRL(pe));
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/* Enable access to all IFPP program memories */
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writel(EIP197_PE_ICE_RAM_CTRL_FPP_PROG_EN,
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EIP197_PE(priv) + EIP197_PE_ICE_RAM_CTRL(pe));
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}
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}
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static int eip197_write_firmware(struct safexcel_crypto_priv *priv,
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const struct firmware *fw)
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{
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const u32 *data = (const u32 *)fw->data;
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u32 val;
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int i;
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/* Reset the engine to make its program memory accessible */
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writel(EIP197_PE_ICE_x_CTRL_SW_RESET |
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EIP197_PE_ICE_x_CTRL_CLR_ECC_CORR |
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EIP197_PE_ICE_x_CTRL_CLR_ECC_NON_CORR,
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EIP197_PE(priv) + ctrl);
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/* Enable access to the program memory */
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writel(prog_en, EIP197_PE(priv) + EIP197_PE_ICE_RAM_CTRL(pe));
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/* Write the firmware */
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for (i = 0; i < fw->size / sizeof(u32); i++)
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writel(be32_to_cpu(data[i]),
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priv->base + EIP197_CLASSIFICATION_RAMS + i * sizeof(u32));
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/* Disable access to the program memory */
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writel(0, EIP197_PE(priv) + EIP197_PE_ICE_RAM_CTRL(pe));
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/* Exclude final 2 NOPs from size */
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return i - EIP197_FW_TERMINAL_NOPS;
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}
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/* Release engine from reset */
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val = readl(EIP197_PE(priv) + ctrl);
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val &= ~EIP197_PE_ICE_x_CTRL_SW_RESET;
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writel(val, EIP197_PE(priv) + ctrl);
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/*
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* If FW is actual production firmware, then poll for its initialization
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* to complete and check if it is good for the HW, otherwise just return OK.
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*/
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static bool poll_fw_ready(struct safexcel_crypto_priv *priv, int fpp)
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{
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int pe, pollcnt;
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u32 base, pollofs;
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if (fpp)
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pollofs = EIP197_FW_FPP_READY;
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else
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pollofs = EIP197_FW_PUE_READY;
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for (pe = 0; pe < priv->config.pes; pe++) {
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base = EIP197_PE_ICE_SCRATCH_RAM(pe);
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pollcnt = EIP197_FW_START_POLLCNT;
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while (pollcnt &&
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(readl_relaxed(EIP197_PE(priv) + base +
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pollofs) != 1)) {
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pollcnt--;
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}
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if (!pollcnt) {
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dev_err(priv->dev, "FW(%d) for PE %d failed to start\n",
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fpp, pe);
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return false;
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}
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}
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return true;
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}
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static bool eip197_start_firmware(struct safexcel_crypto_priv *priv,
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int ipuesz, int ifppsz, int minifw)
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{
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int pe;
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u32 val;
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for (pe = 0; pe < priv->config.pes; pe++) {
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/* Disable access to all program memory */
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writel(0, EIP197_PE(priv) + EIP197_PE_ICE_RAM_CTRL(pe));
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/* Start IFPP microengines */
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if (minifw)
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val = 0;
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else
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val = EIP197_PE_ICE_UENG_START_OFFSET((ifppsz - 1) &
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EIP197_PE_ICE_UENG_INIT_ALIGN_MASK) |
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EIP197_PE_ICE_UENG_DEBUG_RESET;
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writel(val, EIP197_PE(priv) + EIP197_PE_ICE_FPP_CTRL(pe));
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/* Start IPUE microengines */
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if (minifw)
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val = 0;
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else
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val = EIP197_PE_ICE_UENG_START_OFFSET((ipuesz - 1) &
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EIP197_PE_ICE_UENG_INIT_ALIGN_MASK) |
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EIP197_PE_ICE_UENG_DEBUG_RESET;
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writel(val, EIP197_PE(priv) + EIP197_PE_ICE_PUE_CTRL(pe));
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}
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/* For miniFW startup, there is no initialization, so always succeed */
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if (minifw)
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return true;
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/* Wait until all the firmwares have properly started up */
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if (!poll_fw_ready(priv, 1))
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return false;
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if (!poll_fw_ready(priv, 0))
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return false;
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return true;
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}
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static int eip197_load_firmwares(struct safexcel_crypto_priv *priv)
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{
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const char *fw_name[] = {"ifpp.bin", "ipue.bin"};
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const struct firmware *fw[FW_NB];
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char fw_path[31], *dir = NULL;
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char fw_path[37], *dir = NULL;
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int i, j, ret = 0, pe;
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u32 val;
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int ipuesz, ifppsz, minifw = 0;
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if (priv->version == EIP197D_MRVL)
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dir = "eip197d";
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@ -155,51 +254,56 @@ static int eip197_load_firmwares(struct safexcel_crypto_priv *priv)
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else
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return -ENODEV;
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retry_fw:
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for (i = 0; i < FW_NB; i++) {
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snprintf(fw_path, 31, "inside-secure/%s/%s", dir, fw_name[i]);
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ret = request_firmware(&fw[i], fw_path, priv->dev);
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snprintf(fw_path, 37, "inside-secure/%s/%s", dir, fw_name[i]);
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ret = firmware_request_nowarn(&fw[i], fw_path, priv->dev);
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if (ret) {
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if (priv->version != EIP197B_MRVL)
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if (minifw || priv->version != EIP197B_MRVL)
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goto release_fw;
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/* Fallback to the old firmware location for the
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* EIP197b.
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*/
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ret = request_firmware(&fw[i], fw_name[i], priv->dev);
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if (ret) {
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dev_err(priv->dev,
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"Failed to request firmware %s (%d)\n",
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fw_name[i], ret);
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ret = firmware_request_nowarn(&fw[i], fw_name[i],
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priv->dev);
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if (ret)
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goto release_fw;
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}
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}
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}
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for (pe = 0; pe < priv->config.pes; pe++) {
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/* Clear the scratchpad memory */
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val = readl(EIP197_PE(priv) + EIP197_PE_ICE_SCRATCH_CTRL(pe));
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val |= EIP197_PE_ICE_SCRATCH_CTRL_CHANGE_TIMER |
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EIP197_PE_ICE_SCRATCH_CTRL_TIMER_EN |
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EIP197_PE_ICE_SCRATCH_CTRL_SCRATCH_ACCESS |
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EIP197_PE_ICE_SCRATCH_CTRL_CHANGE_ACCESS;
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writel(val, EIP197_PE(priv) + EIP197_PE_ICE_SCRATCH_CTRL(pe));
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eip197_init_firmware(priv);
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memset_io(EIP197_PE(priv) + EIP197_PE_ICE_SCRATCH_RAM(pe), 0,
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EIP197_NUM_OF_SCRATCH_BLOCKS * sizeof(u32));
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ifppsz = eip197_write_firmware(priv, fw[FW_IFPP]);
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eip197_write_firmware(priv, fw[FW_IFPP], pe,
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EIP197_PE_ICE_FPP_CTRL(pe),
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EIP197_PE_ICE_RAM_CTRL_FPP_PROG_EN);
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/* Enable access to IPUE program memories */
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for (pe = 0; pe < priv->config.pes; pe++)
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writel(EIP197_PE_ICE_RAM_CTRL_PUE_PROG_EN,
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EIP197_PE(priv) + EIP197_PE_ICE_RAM_CTRL(pe));
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eip197_write_firmware(priv, fw[FW_IPUE], pe,
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EIP197_PE_ICE_PUE_CTRL(pe),
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EIP197_PE_ICE_RAM_CTRL_PUE_PROG_EN);
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ipuesz = eip197_write_firmware(priv, fw[FW_IPUE]);
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if (eip197_start_firmware(priv, ipuesz, ifppsz, minifw)) {
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dev_dbg(priv->dev, "Firmware loaded successfully");
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return 0;
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}
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ret = -ENODEV;
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release_fw:
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for (j = 0; j < i; j++)
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release_firmware(fw[j]);
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if (!minifw) {
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/* Retry with minifw path */
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dev_dbg(priv->dev, "Firmware set not (fully) present or init failed, falling back to BCLA mode\n");
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dir = "eip197_minifw";
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minifw = 1;
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goto retry_fw;
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}
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dev_dbg(priv->dev, "Firmware load failed.\n");
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return ret;
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}
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@ -136,8 +136,10 @@
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#define EIP197_PE_IN_TBUF_THRES(n) (0x0100 + (0x2000 * (n)))
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#define EIP197_PE_ICE_SCRATCH_RAM(n) (0x0800 + (0x2000 * (n)))
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#define EIP197_PE_ICE_PUE_CTRL(n) (0x0c80 + (0x2000 * (n)))
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#define EIP197_PE_ICE_PUTF_CTRL(n) (0x0d00 + (0x2000 * (n)))
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#define EIP197_PE_ICE_SCRATCH_CTRL(n) (0x0d04 + (0x2000 * (n)))
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#define EIP197_PE_ICE_FPP_CTRL(n) (0x0d80 + (0x2000 * (n)))
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#define EIP197_PE_ICE_PPTF_CTRL(n) (0x0e00 + (0x2000 * (n)))
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#define EIP197_PE_ICE_RAM_CTRL(n) (0x0ff0 + (0x2000 * (n)))
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#define EIP197_PE_EIP96_TOKEN_CTRL(n) (0x1000 + (0x2000 * (n)))
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#define EIP197_PE_EIP96_FUNCTION_EN(n) (0x1004 + (0x2000 * (n)))
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@ -228,6 +230,11 @@
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#define EIP197_DxE_THR_CTRL_EN BIT(30)
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#define EIP197_DxE_THR_CTRL_RESET_PE BIT(31)
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/* EIP197_PE_ICE_PUE/FPP_CTRL */
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#define EIP197_PE_ICE_UENG_START_OFFSET(n) ((n) << 16)
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#define EIP197_PE_ICE_UENG_INIT_ALIGN_MASK 0x7ff0
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#define EIP197_PE_ICE_UENG_DEBUG_RESET BIT(3)
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/* EIP197_HIA_AIC_G_ENABLED_STAT */
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#define EIP197_G_IRQ_DFE(n) BIT((n) << 1)
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#define EIP197_G_IRQ_DSE(n) BIT(((n) << 1) + 1)
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@ -503,6 +510,11 @@ struct safexcel_command_desc {
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* Internal structures & functions
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*/
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#define EIP197_FW_TERMINAL_NOPS 2
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#define EIP197_FW_START_POLLCNT 16
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#define EIP197_FW_PUE_READY 0x14
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#define EIP197_FW_FPP_READY 0x18
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enum eip197_fw {
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FW_IFPP = 0,
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FW_IPUE,
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