Merge tag 'irq-core-2020-06-02' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq updates from Thomas Gleixner: "The generic interrupt departement provides: - Cleanup of the irq_domain API - Overhaul of the interrupt chip simulator - The usual pile of new interrupt chip drivers - Cleanups, improvements and fixes all over the place" * tag 'irq-core-2020-06-02' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (23 commits) irqchip: Fix "Loongson HyperTransport Vector support" driver build on all non-MIPS platforms dt-bindings: interrupt-controller: Add Loongson PCH MSI irqchip: Add Loongson PCH MSI controller dt-bindings: interrupt-controller: Add Loongson PCH PIC irqchip: Add Loongson PCH PIC controller dt-bindings: interrupt-controller: Add Loongson HTVEC irqchip: Add Loongson HyperTransport Vector support genirq: Check irq_data_get_irq_chip() return value before use irqchip/sifive-plic: Improve boot prints for multiple PLIC instances irqchip/sifive-plic: Setup cpuhp once after boot CPU handler is present irqchip/sifive-plic: Set default irq affinity in plic_irqdomain_map() irqchip/gic-v2, v3: Drop extra IRQ_NOAUTOEN setting for (E)PPIs irqdomain: Allow software nodes for IRQ domain creation irqdomain: Get rid of special treatment for ACPI in __irq_domain_add() irqdomain: Make __irq_domain_add() less OF-dependent iio: dummy_evgen: Fix use after free on error in iio_dummy_evgen_create() irqchip/gic-v3-its: Balance initial LPI affinity across CPUs irqchip/gic-v3-its: Track LPI distribution on a per CPU basis genirq/irq_sim: Simplify the API irqdomain: Make irq_domain_reset_irq_data() available to non-hierarchical users ...
This commit is contained in:
Linus Torvalds
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/interrupt-controller/loongson,htvec.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Loongson-3 HyperTransport Interrupt Vector Controller
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maintainers:
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- Jiaxun Yang <jiaxun.yang@flygoat.com>
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description:
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This interrupt controller is found in the Loongson-3 family of chips for
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receiving vectorized interrupts from PCH's interrupt controller.
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properties:
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compatible:
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const: loongson,htvec-1.0
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reg:
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maxItems: 1
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interrupts:
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minItems: 1
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maxItems: 4
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description: Four parent interrupts that receive chained interrupts.
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interrupt-controller: true
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'#interrupt-cells':
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const: 1
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required:
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- compatible
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- reg
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- interrupts
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- interrupt-controller
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- '#interrupt-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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htvec: interrupt-controller@fb000080 {
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compatible = "loongson,htvec-1.0";
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reg = <0xfb000080 0x40>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&liointc>;
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interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
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<25 IRQ_TYPE_LEVEL_HIGH>,
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<26 IRQ_TYPE_LEVEL_HIGH>,
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<27 IRQ_TYPE_LEVEL_HIGH>;
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};
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...
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Loongson PCH MSI Controller
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maintainers:
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- Jiaxun Yang <jiaxun.yang@flygoat.com>
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description:
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This interrupt controller is found in the Loongson LS7A family of PCH for
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transforming interrupts from PCIe MSI into HyperTransport vectorized
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interrupts.
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properties:
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compatible:
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const: loongson,pch-msi-1.0
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reg:
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maxItems: 1
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loongson,msi-base-vec:
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description:
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u32 value of the base of parent HyperTransport vector allocated
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to PCH MSI.
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allOf:
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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- minimum: 0
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maximum: 255
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loongson,msi-num-vecs:
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description:
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u32 value of the number of parent HyperTransport vectors allocated
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to PCH MSI.
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allOf:
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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- minimum: 1
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maximum: 256
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msi-controller: true
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required:
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- compatible
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- reg
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- msi-controller
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- loongson,msi-base-vec
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- loongson,msi-num-vecs
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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msi: msi-controller@2ff00000 {
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compatible = "loongson,pch-msi-1.0";
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reg = <0x2ff00000 0x4>;
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msi-controller;
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loongson,msi-base-vec = <64>;
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loongson,msi-num-vecs = <64>;
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interrupt-parent = <&htvec>;
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};
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...
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/interrupt-controller/loongson,pch-pic.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Loongson PCH PIC Controller
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maintainers:
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- Jiaxun Yang <jiaxun.yang@flygoat.com>
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description:
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This interrupt controller is found in the Loongson LS7A family of PCH for
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transforming interrupts from on-chip devices into HyperTransport vectorized
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interrupts.
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properties:
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compatible:
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const: loongson,pch-pic-1.0
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reg:
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maxItems: 1
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loongson,pic-base-vec:
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description:
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u32 value of the base of parent HyperTransport vector allocated
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to PCH PIC.
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allOf:
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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- minimum: 0
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maximum: 192
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interrupt-controller: true
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'#interrupt-cells':
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const: 2
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required:
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- compatible
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- reg
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- loongson,pic-base-vec
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- interrupt-controller
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- '#interrupt-cells'
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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pic: interrupt-controller@10000000 {
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compatible = "loongson,pch-pic-1.0";
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reg = <0x10000000 0x400>;
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interrupt-controller;
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#interrupt-cells = <2>;
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loongson,pic-base-vec = <64>;
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interrupt-parent = <&htvec>;
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};
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...
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