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clk: renesas: mstp: ensure register writes complete

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When there is no status bit, it is possible for the clock enable/disable
operation to have not completed by the time the driver code resumes
execution. This is due to the fact that write operations are sometimes
queued and delayed internally. Doing a read ensures the write operations
has completed.

Fixes: b6face404f ("ARM: shmobile: r7s72100: add essential clock nodes to dtsi")
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Chris Brandt 2017-02-14 11:08:05 -05:00 committed by Stephen Boyd
parent 6ff8ec98e1
commit f59de56335
1 changed files with 6 additions and 0 deletions
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6
drivers/clk/renesas/clk-mstp.c
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@ -91,6 +91,12 @@ static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
value |= bitmask;
cpg_mstp_write(group, value, group->smstpcr);
if (!group->mstpsr) {
/* dummy read to ensure write has completed */
cpg_mstp_read(group, group->smstpcr);
barrier_data(group->smstpcr);
}
spin_unlock_irqrestore(&group->lock, flags);
if (!enable || !group->mstpsr)