forked from Minki/linux
drm/i915: Split the crtc_mode_set function along HAS_PCH_SPLIT() lines.
This path, which shouldn't be *that* complicated, is now so littered with per-chipset tweaks that it's hard to trace the order of what happens. HAS_PCH_SPLIT() is the most radical change across chipsets, so it seems like a natural split to simplify the code. This first commit just copies the existing code without changing anything. v2: updated to track removal of call to intel_enable_plane from i9xx_crtc_mode_set Signed-off-by: Eric Anholt <eric@anholt.net> Hella-acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Eric Anholt
Keith Packard
parent
d2dff872ac
commit
f564048e20
@ -203,6 +203,12 @@ struct drm_i915_display_funcs {
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int (*get_display_clock_speed)(struct drm_device *dev);
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int (*get_fifo_size)(struct drm_device *dev, int plane);
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void (*update_wm)(struct drm_device *dev);
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int (*crtc_mode_set)(struct drm_crtc *crtc,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode,
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int x, int y,
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struct drm_framebuffer *old_fb);
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/* clock updates for mode set */
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/* cursor updates */
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/* render clock increase/decrease */
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@ -4516,11 +4516,659 @@ static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
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return dev_priv->lvds_use_ssc && i915_panel_use_ssc;
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}
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static int intel_crtc_mode_set(struct drm_crtc *crtc,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode,
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int x, int y,
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struct drm_framebuffer *old_fb)
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static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode,
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int x, int y,
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struct drm_framebuffer *old_fb)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pipe = intel_crtc->pipe;
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int plane = intel_crtc->plane;
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u32 fp_reg, dpll_reg;
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int refclk, num_connectors = 0;
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intel_clock_t clock, reduced_clock;
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u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
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bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
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bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
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struct intel_encoder *has_edp_encoder = NULL;
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struct drm_mode_config *mode_config = &dev->mode_config;
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struct intel_encoder *encoder;
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const intel_limit_t *limit;
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int ret;
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struct fdi_m_n m_n = {0};
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u32 reg, temp;
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u32 lvds_sync = 0;
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int target_clock;
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drm_vblank_pre_modeset(dev, pipe);
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list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
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if (encoder->base.crtc != crtc)
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continue;
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switch (encoder->type) {
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case INTEL_OUTPUT_LVDS:
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is_lvds = true;
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break;
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case INTEL_OUTPUT_SDVO:
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case INTEL_OUTPUT_HDMI:
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is_sdvo = true;
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if (encoder->needs_tv_clock)
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is_tv = true;
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break;
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case INTEL_OUTPUT_DVO:
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is_dvo = true;
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break;
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case INTEL_OUTPUT_TVOUT:
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is_tv = true;
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break;
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case INTEL_OUTPUT_ANALOG:
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is_crt = true;
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break;
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case INTEL_OUTPUT_DISPLAYPORT:
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is_dp = true;
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break;
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case INTEL_OUTPUT_EDP:
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has_edp_encoder = encoder;
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break;
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}
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num_connectors++;
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}
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if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
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refclk = dev_priv->lvds_ssc_freq * 1000;
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DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
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refclk / 1000);
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} else if (!IS_GEN2(dev)) {
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refclk = 96000;
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if (HAS_PCH_SPLIT(dev) &&
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(!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)))
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refclk = 120000; /* 120Mhz refclk */
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} else {
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refclk = 48000;
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}
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/*
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* Returns a set of divisors for the desired target clock with the given
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* refclk, or FALSE. The returned values represent the clock equation:
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* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
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*/
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limit = intel_limit(crtc, refclk);
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ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
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if (!ok) {
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DRM_ERROR("Couldn't find PLL settings for mode!\n");
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drm_vblank_post_modeset(dev, pipe);
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return -EINVAL;
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}
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/* Ensure that the cursor is valid for the new mode before changing... */
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intel_crtc_update_cursor(crtc, true);
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if (is_lvds && dev_priv->lvds_downclock_avail) {
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has_reduced_clock = limit->find_pll(limit, crtc,
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dev_priv->lvds_downclock,
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refclk,
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&reduced_clock);
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if (has_reduced_clock && (clock.p != reduced_clock.p)) {
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/*
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* If the different P is found, it means that we can't
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* switch the display clock by using the FP0/FP1.
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* In such case we will disable the LVDS downclock
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* feature.
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*/
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DRM_DEBUG_KMS("Different P is found for "
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"LVDS clock/downclock\n");
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has_reduced_clock = 0;
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}
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}
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/* SDVO TV has fixed PLL values depend on its clock range,
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this mirrors vbios setting. */
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if (is_sdvo && is_tv) {
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if (adjusted_mode->clock >= 100000
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&& adjusted_mode->clock < 140500) {
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clock.p1 = 2;
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clock.p2 = 10;
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clock.n = 3;
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clock.m1 = 16;
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clock.m2 = 8;
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} else if (adjusted_mode->clock >= 140500
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&& adjusted_mode->clock <= 200000) {
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clock.p1 = 1;
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clock.p2 = 10;
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clock.n = 6;
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clock.m1 = 12;
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clock.m2 = 8;
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}
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}
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/* FDI link */
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if (HAS_PCH_SPLIT(dev)) {
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int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
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int lane = 0, link_bw, bpp;
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/* CPU eDP doesn't require FDI link, so just set DP M/N
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according to current link config */
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if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
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target_clock = mode->clock;
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intel_edp_link_config(has_edp_encoder,
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&lane, &link_bw);
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} else {
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/* [e]DP over FDI requires target mode clock
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instead of link clock */
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if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
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target_clock = mode->clock;
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else
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target_clock = adjusted_mode->clock;
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/* FDI is a binary signal running at ~2.7GHz, encoding
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* each output octet as 10 bits. The actual frequency
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* is stored as a divider into a 100MHz clock, and the
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* mode pixel clock is stored in units of 1KHz.
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* Hence the bw of each lane in terms of the mode signal
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* is:
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*/
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link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
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}
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/* determine panel color depth */
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temp = I915_READ(PIPECONF(pipe));
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temp &= ~PIPE_BPC_MASK;
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if (is_lvds) {
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/* the BPC will be 6 if it is 18-bit LVDS panel */
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if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
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temp |= PIPE_8BPC;
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else
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temp |= PIPE_6BPC;
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} else if (has_edp_encoder) {
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switch (dev_priv->edp.bpp/3) {
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case 8:
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temp |= PIPE_8BPC;
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break;
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case 10:
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temp |= PIPE_10BPC;
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break;
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case 6:
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temp |= PIPE_6BPC;
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break;
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case 12:
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temp |= PIPE_12BPC;
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break;
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}
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} else
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temp |= PIPE_8BPC;
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I915_WRITE(PIPECONF(pipe), temp);
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switch (temp & PIPE_BPC_MASK) {
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case PIPE_8BPC:
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bpp = 24;
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break;
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case PIPE_10BPC:
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bpp = 30;
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break;
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case PIPE_6BPC:
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bpp = 18;
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break;
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case PIPE_12BPC:
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bpp = 36;
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break;
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default:
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DRM_ERROR("unknown pipe bpc value\n");
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bpp = 24;
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}
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if (!lane) {
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/*
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* Account for spread spectrum to avoid
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* oversubscribing the link. Max center spread
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* is 2.5%; use 5% for safety's sake.
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*/
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u32 bps = target_clock * bpp * 21 / 20;
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lane = bps / (link_bw * 8) + 1;
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}
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intel_crtc->fdi_lanes = lane;
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if (pixel_multiplier > 1)
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link_bw *= pixel_multiplier;
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ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
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}
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/* Ironlake: try to setup display ref clock before DPLL
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* enabling. This is only under driver's control after
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* PCH B stepping, previous chipset stepping should be
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* ignoring this setting.
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*/
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if (HAS_PCH_SPLIT(dev)) {
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temp = I915_READ(PCH_DREF_CONTROL);
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/* Always enable nonspread source */
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temp &= ~DREF_NONSPREAD_SOURCE_MASK;
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temp |= DREF_NONSPREAD_SOURCE_ENABLE;
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temp &= ~DREF_SSC_SOURCE_MASK;
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temp |= DREF_SSC_SOURCE_ENABLE;
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I915_WRITE(PCH_DREF_CONTROL, temp);
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POSTING_READ(PCH_DREF_CONTROL);
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udelay(200);
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if (has_edp_encoder) {
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if (intel_panel_use_ssc(dev_priv)) {
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temp |= DREF_SSC1_ENABLE;
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I915_WRITE(PCH_DREF_CONTROL, temp);
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POSTING_READ(PCH_DREF_CONTROL);
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udelay(200);
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}
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temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
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/* Enable CPU source on CPU attached eDP */
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if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
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if (intel_panel_use_ssc(dev_priv))
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temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
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else
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temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
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} else {
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/* Enable SSC on PCH eDP if needed */
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if (intel_panel_use_ssc(dev_priv)) {
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DRM_ERROR("enabling SSC on PCH\n");
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temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
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}
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}
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I915_WRITE(PCH_DREF_CONTROL, temp);
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POSTING_READ(PCH_DREF_CONTROL);
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udelay(200);
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}
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}
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if (IS_PINEVIEW(dev)) {
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fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
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if (has_reduced_clock)
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fp2 = (1 << reduced_clock.n) << 16 |
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reduced_clock.m1 << 8 | reduced_clock.m2;
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} else {
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fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
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if (has_reduced_clock)
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fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
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reduced_clock.m2;
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}
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/* Enable autotuning of the PLL clock (if permissible) */
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if (HAS_PCH_SPLIT(dev)) {
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int factor = 21;
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if (is_lvds) {
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if ((intel_panel_use_ssc(dev_priv) &&
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dev_priv->lvds_ssc_freq == 100) ||
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(I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
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factor = 25;
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} else if (is_sdvo && is_tv)
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factor = 20;
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if (clock.m1 < factor * clock.n)
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fp |= FP_CB_TUNE;
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}
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dpll = 0;
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if (!HAS_PCH_SPLIT(dev))
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dpll = DPLL_VGA_MODE_DIS;
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if (!IS_GEN2(dev)) {
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if (is_lvds)
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dpll |= DPLLB_MODE_LVDS;
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else
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dpll |= DPLLB_MODE_DAC_SERIAL;
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if (is_sdvo) {
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int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
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if (pixel_multiplier > 1) {
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if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
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dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
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else if (HAS_PCH_SPLIT(dev))
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dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
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}
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dpll |= DPLL_DVO_HIGH_SPEED;
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}
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if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
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dpll |= DPLL_DVO_HIGH_SPEED;
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/* compute bitmask from p1 value */
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if (IS_PINEVIEW(dev))
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dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
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else {
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dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
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/* also FPA1 */
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if (HAS_PCH_SPLIT(dev))
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dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
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if (IS_G4X(dev) && has_reduced_clock)
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dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
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}
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switch (clock.p2) {
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case 5:
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dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
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break;
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case 7:
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dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
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break;
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case 10:
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dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
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break;
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case 14:
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dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
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break;
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}
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if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
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dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
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} else {
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if (is_lvds) {
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dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
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} else {
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if (clock.p1 == 2)
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dpll |= PLL_P1_DIVIDE_BY_TWO;
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else
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dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
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if (clock.p2 == 4)
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dpll |= PLL_P2_DIVIDE_BY_4;
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}
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}
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if (is_sdvo && is_tv)
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dpll |= PLL_REF_INPUT_TVCLKINBC;
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else if (is_tv)
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/* XXX: just matching BIOS for now */
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/* dpll |= PLL_REF_INPUT_TVCLKINBC; */
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dpll |= 3;
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else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
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dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
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else
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dpll |= PLL_REF_INPUT_DREFCLK;
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/* setup pipeconf */
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pipeconf = I915_READ(PIPECONF(pipe));
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/* Set up the display plane register */
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dspcntr = DISPPLANE_GAMMA_ENABLE;
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/* Ironlake's plane is forced to pipe, bit 24 is to
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enable color space conversion */
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if (!HAS_PCH_SPLIT(dev)) {
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if (pipe == 0)
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dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
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else
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dspcntr |= DISPPLANE_SEL_PIPE_B;
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}
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if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
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/* Enable pixel doubling when the dot clock is > 90% of the (display)
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* core speed.
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*
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* XXX: No double-wide on 915GM pipe B. Is that the only reason for the
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* pipe == 0 check?
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*/
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if (mode->clock >
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dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
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pipeconf |= PIPECONF_DOUBLE_WIDE;
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else
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pipeconf &= ~PIPECONF_DOUBLE_WIDE;
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}
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if (!HAS_PCH_SPLIT(dev))
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dpll |= DPLL_VCO_ENABLE;
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DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
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drm_mode_debug_printmodeline(mode);
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/* assign to Ironlake registers */
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if (HAS_PCH_SPLIT(dev)) {
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fp_reg = PCH_FP0(pipe);
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dpll_reg = PCH_DPLL(pipe);
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} else {
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fp_reg = FP0(pipe);
|
||||
dpll_reg = DPLL(pipe);
|
||||
}
|
||||
|
||||
/* PCH eDP needs FDI, but CPU eDP does not */
|
||||
if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
|
||||
I915_WRITE(fp_reg, fp);
|
||||
I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
|
||||
|
||||
POSTING_READ(dpll_reg);
|
||||
udelay(150);
|
||||
}
|
||||
|
||||
/* enable transcoder DPLL */
|
||||
if (HAS_PCH_CPT(dev)) {
|
||||
temp = I915_READ(PCH_DPLL_SEL);
|
||||
switch (pipe) {
|
||||
case 0:
|
||||
temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
|
||||
break;
|
||||
case 1:
|
||||
temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
|
||||
break;
|
||||
case 2:
|
||||
/* FIXME: manage transcoder PLLs? */
|
||||
temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
I915_WRITE(PCH_DPLL_SEL, temp);
|
||||
|
||||
POSTING_READ(PCH_DPLL_SEL);
|
||||
udelay(150);
|
||||
}
|
||||
|
||||
/* The LVDS pin pair needs to be on before the DPLLs are enabled.
|
||||
* This is an exception to the general rule that mode_set doesn't turn
|
||||
* things on.
|
||||
*/
|
||||
if (is_lvds) {
|
||||
reg = LVDS;
|
||||
if (HAS_PCH_SPLIT(dev))
|
||||
reg = PCH_LVDS;
|
||||
|
||||
temp = I915_READ(reg);
|
||||
temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
|
||||
if (pipe == 1) {
|
||||
if (HAS_PCH_CPT(dev))
|
||||
temp |= PORT_TRANS_B_SEL_CPT;
|
||||
else
|
||||
temp |= LVDS_PIPEB_SELECT;
|
||||
} else {
|
||||
if (HAS_PCH_CPT(dev))
|
||||
temp &= ~PORT_TRANS_SEL_MASK;
|
||||
else
|
||||
temp &= ~LVDS_PIPEB_SELECT;
|
||||
}
|
||||
/* set the corresponsding LVDS_BORDER bit */
|
||||
temp |= dev_priv->lvds_border_bits;
|
||||
/* Set the B0-B3 data pairs corresponding to whether we're going to
|
||||
* set the DPLLs for dual-channel mode or not.
|
||||
*/
|
||||
if (clock.p2 == 7)
|
||||
temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
|
||||
else
|
||||
temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
|
||||
|
||||
/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
|
||||
* appropriately here, but we need to look more thoroughly into how
|
||||
* panels behave in the two modes.
|
||||
*/
|
||||
/* set the dithering flag on non-PCH LVDS as needed */
|
||||
if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
|
||||
if (dev_priv->lvds_dither)
|
||||
temp |= LVDS_ENABLE_DITHER;
|
||||
else
|
||||
temp &= ~LVDS_ENABLE_DITHER;
|
||||
}
|
||||
if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
|
||||
lvds_sync |= LVDS_HSYNC_POLARITY;
|
||||
if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
|
||||
lvds_sync |= LVDS_VSYNC_POLARITY;
|
||||
if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
|
||||
!= lvds_sync) {
|
||||
char flags[2] = "-+";
|
||||
DRM_INFO("Changing LVDS panel from "
|
||||
"(%chsync, %cvsync) to (%chsync, %cvsync)\n",
|
||||
flags[!(temp & LVDS_HSYNC_POLARITY)],
|
||||
flags[!(temp & LVDS_VSYNC_POLARITY)],
|
||||
flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
|
||||
flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
|
||||
temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
|
||||
temp |= lvds_sync;
|
||||
}
|
||||
I915_WRITE(reg, temp);
|
||||
}
|
||||
|
||||
/* set the dithering flag and clear for anything other than a panel. */
|
||||
if (HAS_PCH_SPLIT(dev)) {
|
||||
pipeconf &= ~PIPECONF_DITHER_EN;
|
||||
pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
|
||||
if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
|
||||
pipeconf |= PIPECONF_DITHER_EN;
|
||||
pipeconf |= PIPECONF_DITHER_TYPE_ST1;
|
||||
}
|
||||
}
|
||||
|
||||
if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
|
||||
intel_dp_set_m_n(crtc, mode, adjusted_mode);
|
||||
} else if (HAS_PCH_SPLIT(dev)) {
|
||||
/* For non-DP output, clear any trans DP clock recovery setting.*/
|
||||
I915_WRITE(TRANSDATA_M1(pipe), 0);
|
||||
I915_WRITE(TRANSDATA_N1(pipe), 0);
|
||||
I915_WRITE(TRANSDPLINK_M1(pipe), 0);
|
||||
I915_WRITE(TRANSDPLINK_N1(pipe), 0);
|
||||
}
|
||||
|
||||
if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
|
||||
I915_WRITE(dpll_reg, dpll);
|
||||
|
||||
/* Wait for the clocks to stabilize. */
|
||||
POSTING_READ(dpll_reg);
|
||||
udelay(150);
|
||||
|
||||
if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
|
||||
temp = 0;
|
||||
if (is_sdvo) {
|
||||
temp = intel_mode_get_pixel_multiplier(adjusted_mode);
|
||||
if (temp > 1)
|
||||
temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
|
||||
else
|
||||
temp = 0;
|
||||
}
|
||||
I915_WRITE(DPLL_MD(pipe), temp);
|
||||
} else {
|
||||
/* The pixel multiplier can only be updated once the
|
||||
* DPLL is enabled and the clocks are stable.
|
||||
*
|
||||
* So write it again.
|
||||
*/
|
||||
I915_WRITE(dpll_reg, dpll);
|
||||
}
|
||||
}
|
||||
|
||||
intel_crtc->lowfreq_avail = false;
|
||||
if (is_lvds && has_reduced_clock && i915_powersave) {
|
||||
I915_WRITE(fp_reg + 4, fp2);
|
||||
intel_crtc->lowfreq_avail = true;
|
||||
if (HAS_PIPE_CXSR(dev)) {
|
||||
DRM_DEBUG_KMS("enabling CxSR downclocking\n");
|
||||
pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
|
||||
}
|
||||
} else {
|
||||
I915_WRITE(fp_reg + 4, fp);
|
||||
if (HAS_PIPE_CXSR(dev)) {
|
||||
DRM_DEBUG_KMS("disabling CxSR downclocking\n");
|
||||
pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
|
||||
}
|
||||
}
|
||||
|
||||
if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
|
||||
pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
|
||||
/* the chip adds 2 halflines automatically */
|
||||
adjusted_mode->crtc_vdisplay -= 1;
|
||||
adjusted_mode->crtc_vtotal -= 1;
|
||||
adjusted_mode->crtc_vblank_start -= 1;
|
||||
adjusted_mode->crtc_vblank_end -= 1;
|
||||
adjusted_mode->crtc_vsync_end -= 1;
|
||||
adjusted_mode->crtc_vsync_start -= 1;
|
||||
} else
|
||||
pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
|
||||
|
||||
I915_WRITE(HTOTAL(pipe),
|
||||
(adjusted_mode->crtc_hdisplay - 1) |
|
||||
((adjusted_mode->crtc_htotal - 1) << 16));
|
||||
I915_WRITE(HBLANK(pipe),
|
||||
(adjusted_mode->crtc_hblank_start - 1) |
|
||||
((adjusted_mode->crtc_hblank_end - 1) << 16));
|
||||
I915_WRITE(HSYNC(pipe),
|
||||
(adjusted_mode->crtc_hsync_start - 1) |
|
||||
((adjusted_mode->crtc_hsync_end - 1) << 16));
|
||||
|
||||
I915_WRITE(VTOTAL(pipe),
|
||||
(adjusted_mode->crtc_vdisplay - 1) |
|
||||
((adjusted_mode->crtc_vtotal - 1) << 16));
|
||||
I915_WRITE(VBLANK(pipe),
|
||||
(adjusted_mode->crtc_vblank_start - 1) |
|
||||
((adjusted_mode->crtc_vblank_end - 1) << 16));
|
||||
I915_WRITE(VSYNC(pipe),
|
||||
(adjusted_mode->crtc_vsync_start - 1) |
|
||||
((adjusted_mode->crtc_vsync_end - 1) << 16));
|
||||
|
||||
/* pipesrc and dspsize control the size that is scaled from,
|
||||
* which should always be the user's requested size.
|
||||
*/
|
||||
if (!HAS_PCH_SPLIT(dev)) {
|
||||
I915_WRITE(DSPSIZE(plane),
|
||||
((mode->vdisplay - 1) << 16) |
|
||||
(mode->hdisplay - 1));
|
||||
I915_WRITE(DSPPOS(plane), 0);
|
||||
}
|
||||
I915_WRITE(PIPESRC(pipe),
|
||||
((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
|
||||
|
||||
if (HAS_PCH_SPLIT(dev)) {
|
||||
I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
|
||||
I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
|
||||
I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
|
||||
I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
|
||||
|
||||
if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
|
||||
ironlake_set_pll_edp(crtc, adjusted_mode->clock);
|
||||
}
|
||||
}
|
||||
|
||||
I915_WRITE(PIPECONF(pipe), pipeconf);
|
||||
POSTING_READ(PIPECONF(pipe));
|
||||
if (!HAS_PCH_SPLIT(dev))
|
||||
intel_enable_pipe(dev_priv, pipe, false);
|
||||
|
||||
intel_wait_for_vblank(dev, pipe);
|
||||
|
||||
if (IS_GEN5(dev)) {
|
||||
/* enable address swizzle for tiling buffer */
|
||||
temp = I915_READ(DISP_ARB_CTL);
|
||||
I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
|
||||
}
|
||||
|
||||
I915_WRITE(DSPCNTR(plane), dspcntr);
|
||||
POSTING_READ(DSPCNTR(plane));
|
||||
|
||||
ret = intel_pipe_set_base(crtc, x, y, old_fb);
|
||||
|
||||
intel_update_watermarks(dev);
|
||||
|
||||
drm_vblank_post_modeset(dev, pipe);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
|
||||
struct drm_display_mode *mode,
|
||||
struct drm_display_mode *adjusted_mode,
|
||||
int x, int y,
|
||||
struct drm_framebuffer *old_fb)
|
||||
{
|
||||
struct drm_device *dev = crtc->dev;
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
@ -5164,6 +5812,22 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int intel_crtc_mode_set(struct drm_crtc *crtc,
|
||||
struct drm_display_mode *mode,
|
||||
struct drm_display_mode *adjusted_mode,
|
||||
int x, int y,
|
||||
struct drm_framebuffer *old_fb)
|
||||
{
|
||||
struct drm_device *dev = crtc->dev;
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
int ret;
|
||||
|
||||
ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
|
||||
x, y, old_fb);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/** Loads the palette/gamma unit for the CRTC with the prepared values */
|
||||
void intel_crtc_load_lut(struct drm_crtc *crtc)
|
||||
{
|
||||
@ -7329,10 +7993,13 @@ static void intel_init_display(struct drm_device *dev)
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
|
||||
/* We always want a DPMS function */
|
||||
if (HAS_PCH_SPLIT(dev))
|
||||
if (HAS_PCH_SPLIT(dev)) {
|
||||
dev_priv->display.dpms = ironlake_crtc_dpms;
|
||||
else
|
||||
dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
|
||||
} else {
|
||||
dev_priv->display.dpms = i9xx_crtc_dpms;
|
||||
dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
|
||||
}
|
||||
|
||||
if (I915_HAS_FBC(dev)) {
|
||||
if (HAS_PCH_SPLIT(dev)) {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user