forked from Minki/linux
GIC updates for 4.6
- Basic GICv3 ACPI support - Alpine MSI widget on top of GICv3 - More RealView GIC support -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJW3++eAAoJECPQ0LrRPXpDBoMP/R8WOgjk1mbwiICjCdKs8n4f QA0BszmPTYSnwnbjqxCEgoWmDkpPGurODjyt6FQeaZFj/bhWxKTsFVcOBslFkXcc 8EB9Avx4N/zEI9VOFuQoiKLIZwSldBNJjgGPSU7lQW2pVUUyC+BmJvcLwyP76R4H 21WBjf9egHYTm1I7kWKoLqgrx993uIfSmwILV1lHuyF5Ubhw1AuNoMsvEFLGY76v ZWNfyAud7xOnbu3kNXnryKO4B8vS1q6o23yqFlxXA6HYWL9bTpWi0bseZs7G/MyF LEBN9CGukaGwGokbE8G0AxtS/c6fz2Uy51xFQRhL+EN3VDrnHbWae5Ys5B7PWgIT DObzVGHkm2V1Nl2jNkwXeeNIrr/APRMDBVJcA5tzXHjcIntHn2ez8Fg0Npo+Zv9G q8m55qbpssSQLKKu7pXG3T3fK59EghTsuFpTRSwP4QtIdyI1yxcgqaXg73s2vOFv DnCxzlXBQ9ia3QqJKY0lNd/QBUoqueGC93TijeBXawSdBhSHp0SXsUp5g99ws0sF fZTzB8dYOB2ZCJc2UW2yNlpMCBPEwCkggQ6M6NISpZLwt3wOyYhTpeBGzSk4j757 AssL9BQf5v2rBkJR93bNlIzBVCa7V0DADgAR5w+uYP4zTyt8tFg1YAoz1lY0435W xQM6Ubx4/xID4Go2sR/Q =bzNQ -----END PGP SIGNATURE----- Merge tag 'gic-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core Pull GIC updates for 4.6 from Marc Zyngier: - Basic GICv3 ACPI support - Alpine MSI widget on top of GICv3 - More RealView GIC support
This commit is contained in:
Thomas Gleixner
commit
f49e0eb221
@ -0,0 +1,26 @@
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Alpine MSIX controller
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See arm,gic-v3.txt for SPI and MSI definitions.
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Required properties:
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- compatible: should be "al,alpine-msix"
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- reg: physical base address and size of the registers
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- interrupt-parent: specifies the parent interrupt controller.
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- interrupt-controller: identifies the node as an interrupt controller
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- msi-controller: identifies the node as an PCI Message Signaled Interrupt
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controller
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- al,msi-base-spi: SPI base of the MSI frame
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- al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0
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Example:
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msix: msix {
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compatible = "al,alpine-msix";
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reg = <0x0 0xfbe00000 0x0 0x100000>;
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interrupt-parent = <&gic>;
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interrupt-controller;
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msi-controller;
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al,msi-base-spi = <160>;
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al,msi-num-spis = <160>;
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};
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@ -16,6 +16,7 @@ Main node required properties:
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"arm,cortex-a15-gic"
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"arm,cortex-a7-gic"
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"arm,cortex-a9-gic"
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"arm,eb11mp-gic"
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"arm,gic-400"
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"arm,pl390"
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"arm,tc11mp-gic"
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@ -65,6 +65,12 @@ config ARMADA_370_XP_IRQ
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select GENERIC_IRQ_CHIP
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select PCI_MSI_IRQ_DOMAIN if PCI_MSI
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config ALPINE_MSI
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bool
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depends on PCI && PCI_MSI
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select GENERIC_IRQ_CHIP
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select PCI_MSI_IRQ_DOMAIN
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config ATMEL_AIC_IRQ
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bool
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select GENERIC_IRQ_CHIP
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@ -1,5 +1,6 @@
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obj-$(CONFIG_IRQCHIP) += irqchip.o
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obj-$(CONFIG_ALPINE_MSI) += irq-alpine-msi.o
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obj-$(CONFIG_ATH79) += irq-ath79-cpu.o
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obj-$(CONFIG_ATH79) += irq-ath79-misc.o
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obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
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293
drivers/irqchip/irq-alpine-msi.c
Normal file
293
drivers/irqchip/irq-alpine-msi.c
Normal file
@ -0,0 +1,293 @@
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/*
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* Annapurna Labs MSIX support services
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*
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* Copyright (C) 2016, Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Antoine Tenart <antoine.tenart@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/irqchip.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/msi.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_pci.h>
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <asm/irq.h>
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#include <asm-generic/msi.h>
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/* MSIX message address format: local GIC target */
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#define ALPINE_MSIX_SPI_TARGET_CLUSTER0 BIT(16)
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struct alpine_msix_data {
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spinlock_t msi_map_lock;
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phys_addr_t addr;
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u32 spi_first; /* The SGI number that MSIs start */
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u32 num_spis; /* The number of SGIs for MSIs */
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unsigned long *msi_map;
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};
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static void alpine_msix_mask_msi_irq(struct irq_data *d)
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{
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pci_msi_mask_irq(d);
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irq_chip_mask_parent(d);
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}
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static void alpine_msix_unmask_msi_irq(struct irq_data *d)
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{
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pci_msi_unmask_irq(d);
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irq_chip_unmask_parent(d);
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}
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static struct irq_chip alpine_msix_irq_chip = {
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.name = "MSIx",
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.irq_mask = alpine_msix_mask_msi_irq,
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.irq_unmask = alpine_msix_unmask_msi_irq,
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.irq_eoi = irq_chip_eoi_parent,
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.irq_set_affinity = irq_chip_set_affinity_parent,
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};
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static int alpine_msix_allocate_sgi(struct alpine_msix_data *priv, int num_req)
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{
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int first;
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spin_lock(&priv->msi_map_lock);
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first = bitmap_find_next_zero_area(priv->msi_map, priv->num_spis, 0,
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num_req, 0);
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if (first >= priv->num_spis) {
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spin_unlock(&priv->msi_map_lock);
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return -ENOSPC;
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}
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bitmap_set(priv->msi_map, first, num_req);
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spin_unlock(&priv->msi_map_lock);
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return priv->spi_first + first;
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}
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static void alpine_msix_free_sgi(struct alpine_msix_data *priv, unsigned sgi,
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int num_req)
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{
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int first = sgi - priv->spi_first;
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spin_lock(&priv->msi_map_lock);
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bitmap_clear(priv->msi_map, first, num_req);
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spin_unlock(&priv->msi_map_lock);
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}
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static void alpine_msix_compose_msi_msg(struct irq_data *data,
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struct msi_msg *msg)
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{
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struct alpine_msix_data *priv = irq_data_get_irq_chip_data(data);
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phys_addr_t msg_addr = priv->addr;
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msg_addr |= (data->hwirq << 3);
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msg->address_hi = upper_32_bits(msg_addr);
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msg->address_lo = lower_32_bits(msg_addr);
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msg->data = 0;
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}
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static struct msi_domain_info alpine_msix_domain_info = {
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.flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
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MSI_FLAG_PCI_MSIX,
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.chip = &alpine_msix_irq_chip,
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};
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static struct irq_chip middle_irq_chip = {
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.name = "alpine_msix_middle",
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.irq_mask = irq_chip_mask_parent,
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.irq_unmask = irq_chip_unmask_parent,
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.irq_eoi = irq_chip_eoi_parent,
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.irq_set_affinity = irq_chip_set_affinity_parent,
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.irq_compose_msi_msg = alpine_msix_compose_msi_msg,
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};
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static int alpine_msix_gic_domain_alloc(struct irq_domain *domain,
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unsigned int virq, int sgi)
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{
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struct irq_fwspec fwspec;
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struct irq_data *d;
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int ret;
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if (!is_of_node(domain->parent->fwnode))
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return -EINVAL;
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fwspec.fwnode = domain->parent->fwnode;
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fwspec.param_count = 3;
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fwspec.param[0] = 0;
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fwspec.param[1] = sgi;
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fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
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ret = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
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if (ret)
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return ret;
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d = irq_domain_get_irq_data(domain->parent, virq);
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d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);
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return 0;
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}
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static int alpine_msix_middle_domain_alloc(struct irq_domain *domain,
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unsigned int virq,
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unsigned int nr_irqs, void *args)
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{
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struct alpine_msix_data *priv = domain->host_data;
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int sgi, err, i;
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sgi = alpine_msix_allocate_sgi(priv, nr_irqs);
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if (sgi < 0)
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return sgi;
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for (i = 0; i < nr_irqs; i++) {
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err = alpine_msix_gic_domain_alloc(domain, virq + i, sgi + i);
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if (err)
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goto err_sgi;
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irq_domain_set_hwirq_and_chip(domain, virq + i, sgi + i,
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&middle_irq_chip, priv);
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}
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return 0;
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err_sgi:
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while (--i >= 0)
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irq_domain_free_irqs_parent(domain, virq, i);
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alpine_msix_free_sgi(priv, sgi, nr_irqs);
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return err;
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}
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static void alpine_msix_middle_domain_free(struct irq_domain *domain,
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unsigned int virq,
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unsigned int nr_irqs)
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{
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struct irq_data *d = irq_domain_get_irq_data(domain, virq);
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struct alpine_msix_data *priv = irq_data_get_irq_chip_data(d);
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irq_domain_free_irqs_parent(domain, virq, nr_irqs);
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alpine_msix_free_sgi(priv, d->hwirq, nr_irqs);
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}
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static const struct irq_domain_ops alpine_msix_middle_domain_ops = {
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.alloc = alpine_msix_middle_domain_alloc,
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.free = alpine_msix_middle_domain_free,
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};
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static int alpine_msix_init_domains(struct alpine_msix_data *priv,
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struct device_node *node)
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{
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struct irq_domain *middle_domain, *msi_domain, *gic_domain;
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struct device_node *gic_node;
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gic_node = of_irq_find_parent(node);
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if (!gic_node) {
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pr_err("Failed to find the GIC node\n");
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return -ENODEV;
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}
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gic_domain = irq_find_host(gic_node);
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if (!gic_domain) {
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pr_err("Failed to find the GIC domain\n");
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return -ENXIO;
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}
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middle_domain = irq_domain_add_tree(NULL,
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&alpine_msix_middle_domain_ops,
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priv);
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if (!middle_domain) {
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pr_err("Failed to create the MSIX middle domain\n");
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return -ENOMEM;
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}
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middle_domain->parent = gic_domain;
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msi_domain = pci_msi_create_irq_domain(of_node_to_fwnode(node),
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&alpine_msix_domain_info,
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middle_domain);
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if (!msi_domain) {
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pr_err("Failed to create MSI domain\n");
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irq_domain_remove(msi_domain);
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return -ENOMEM;
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}
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return 0;
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}
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static int alpine_msix_init(struct device_node *node,
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struct device_node *parent)
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{
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struct alpine_msix_data *priv;
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struct resource res;
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int ret;
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priv = kzalloc(sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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spin_lock_init(&priv->msi_map_lock);
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ret = of_address_to_resource(node, 0, &res);
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if (ret) {
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pr_err("Failed to allocate resource\n");
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goto err_priv;
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}
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/*
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* The 20 least significant bits of addr provide direct information
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* regarding the interrupt destination.
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*
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* To select the primary GIC as the target GIC, bits [18:17] must be set
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* to 0x0. In this case, bit 16 (SPI_TARGET_CLUSTER0) must be set.
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*/
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priv->addr = res.start & GENMASK_ULL(63,20);
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priv->addr |= ALPINE_MSIX_SPI_TARGET_CLUSTER0;
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if (of_property_read_u32(node, "al,msi-base-spi", &priv->spi_first)) {
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pr_err("Unable to parse MSI base\n");
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ret = -EINVAL;
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goto err_priv;
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}
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if (of_property_read_u32(node, "al,msi-num-spis", &priv->num_spis)) {
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pr_err("Unable to parse MSI numbers\n");
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ret = -EINVAL;
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goto err_priv;
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}
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priv->msi_map = kzalloc(sizeof(*priv->msi_map) * BITS_TO_LONGS(priv->num_spis),
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GFP_KERNEL);
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if (!priv->msi_map) {
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ret = -ENOMEM;
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goto err_priv;
|
||||
}
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||||
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pr_debug("Registering %d msixs, starting at %d\n",
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priv->num_spis, priv->spi_first);
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||||
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ret = alpine_msix_init_domains(priv, node);
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||||
if (ret)
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goto err_map;
|
||||
|
||||
return 0;
|
||||
|
||||
err_map:
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kfree(priv->msi_map);
|
||||
err_priv:
|
||||
kfree(priv);
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||||
return ret;
|
||||
}
|
||||
IRQCHIP_DECLARE(alpine_msix, "al,alpine-msix", alpine_msix_init);
|
||||
@ -10,7 +10,8 @@
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
|
||||
#define REALVIEW_SYS_LOCK_OFFSET 0x20
|
||||
#define REALVIEW_PB11MP_SYS_PLD_CTRL1 0x74
|
||||
#define REALVIEW_SYS_PLD_CTRL1 0x74
|
||||
#define REALVIEW_EB_REVB_SYS_PLD_CTRL1 0xD8
|
||||
#define VERSATILE_LOCK_VAL 0xA05F
|
||||
#define PLD_INTMODE_MASK BIT(22)|BIT(23)|BIT(24)
|
||||
#define PLD_INTMODE_LEGACY 0x0
|
||||
@ -18,26 +19,57 @@
|
||||
#define PLD_INTMODE_NEW_NO_DCC BIT(23)
|
||||
#define PLD_INTMODE_FIQ_ENABLE BIT(24)
|
||||
|
||||
/* For some reason RealView EB Rev B moved this register */
|
||||
static const struct of_device_id syscon_pldset_of_match[] = {
|
||||
{
|
||||
.compatible = "arm,realview-eb11mp-revb-syscon",
|
||||
.data = (void *)REALVIEW_EB_REVB_SYS_PLD_CTRL1,
|
||||
},
|
||||
{
|
||||
.compatible = "arm,realview-eb11mp-revc-syscon",
|
||||
.data = (void *)REALVIEW_SYS_PLD_CTRL1,
|
||||
},
|
||||
{
|
||||
.compatible = "arm,realview-eb-syscon",
|
||||
.data = (void *)REALVIEW_SYS_PLD_CTRL1,
|
||||
},
|
||||
{
|
||||
.compatible = "arm,realview-pb11mp-syscon",
|
||||
.data = (void *)REALVIEW_SYS_PLD_CTRL1,
|
||||
},
|
||||
{},
|
||||
};
|
||||
|
||||
static int __init
|
||||
realview_gic_of_init(struct device_node *node, struct device_node *parent)
|
||||
{
|
||||
static struct regmap *map;
|
||||
struct device_node *np;
|
||||
const struct of_device_id *gic_id;
|
||||
u32 pld1_ctrl;
|
||||
|
||||
np = of_find_matching_node_and_match(NULL, syscon_pldset_of_match,
|
||||
&gic_id);
|
||||
if (!np)
|
||||
return -ENODEV;
|
||||
pld1_ctrl = (u32)gic_id->data;
|
||||
|
||||
/* The PB11MPCore GIC needs to be configured in the syscon */
|
||||
map = syscon_regmap_lookup_by_compatible("arm,realview-pb11mp-syscon");
|
||||
map = syscon_node_to_regmap(np);
|
||||
if (!IS_ERR(map)) {
|
||||
/* new irq mode with no DCC */
|
||||
regmap_write(map, REALVIEW_SYS_LOCK_OFFSET,
|
||||
VERSATILE_LOCK_VAL);
|
||||
regmap_update_bits(map, REALVIEW_PB11MP_SYS_PLD_CTRL1,
|
||||
regmap_update_bits(map, pld1_ctrl,
|
||||
PLD_INTMODE_NEW_NO_DCC,
|
||||
PLD_INTMODE_MASK);
|
||||
regmap_write(map, REALVIEW_SYS_LOCK_OFFSET, 0x0000);
|
||||
pr_info("TC11MP GIC: set up interrupt controller to NEW mode, no DCC\n");
|
||||
pr_info("RealView GIC: set up interrupt controller to NEW mode, no DCC\n");
|
||||
} else {
|
||||
pr_err("TC11MP GIC setup: could not find syscon\n");
|
||||
return -ENXIO;
|
||||
pr_err("RealView GIC setup: could not find syscon\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
return gic_of_init(node, parent);
|
||||
}
|
||||
IRQCHIP_DECLARE(armtc11mp_gic, "arm,tc11mp-gic", realview_gic_of_init);
|
||||
IRQCHIP_DECLARE(armeb11mp_gic, "arm,eb11mp-gic", realview_gic_of_init);
|
||||
|
||||
@ -103,7 +103,6 @@ struct its_device {
|
||||
|
||||
static LIST_HEAD(its_nodes);
|
||||
static DEFINE_SPINLOCK(its_lock);
|
||||
static struct device_node *gic_root_node;
|
||||
static struct rdists *gic_rdists;
|
||||
|
||||
#define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist))
|
||||
@ -671,7 +670,7 @@ static int its_chunk_to_lpi(int chunk)
|
||||
return (chunk << IRQS_PER_CHUNK_SHIFT) + 8192;
|
||||
}
|
||||
|
||||
static int its_lpi_init(u32 id_bits)
|
||||
static int __init its_lpi_init(u32 id_bits)
|
||||
{
|
||||
lpi_chunks = its_lpi_to_chunk(1UL << id_bits);
|
||||
|
||||
@ -1430,7 +1429,8 @@ static void its_enable_quirks(struct its_node *its)
|
||||
gic_enable_quirks(iidr, its_quirks, its);
|
||||
}
|
||||
|
||||
static int its_probe(struct device_node *node, struct irq_domain *parent)
|
||||
static int __init its_probe(struct device_node *node,
|
||||
struct irq_domain *parent)
|
||||
{
|
||||
struct resource res;
|
||||
struct its_node *its;
|
||||
@ -1591,7 +1591,7 @@ static struct of_device_id its_device_id[] = {
|
||||
{},
|
||||
};
|
||||
|
||||
int its_init(struct device_node *node, struct rdists *rdists,
|
||||
int __init its_init(struct device_node *node, struct rdists *rdists,
|
||||
struct irq_domain *parent_domain)
|
||||
{
|
||||
struct device_node *np;
|
||||
@ -1607,8 +1607,6 @@ int its_init(struct device_node *node, struct rdists *rdists,
|
||||
}
|
||||
|
||||
gic_rdists = rdists;
|
||||
gic_root_node = node;
|
||||
|
||||
its_alloc_lpi_tables();
|
||||
its_lpi_init(rdists->id_bits);
|
||||
|
||||
|
||||
@ -15,10 +15,12 @@
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <linux/acpi.h>
|
||||
#include <linux/cpu.h>
|
||||
#include <linux/cpu_pm.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
@ -38,6 +40,7 @@
|
||||
struct redist_region {
|
||||
void __iomem *redist_base;
|
||||
phys_addr_t phys_base;
|
||||
bool single_redist;
|
||||
};
|
||||
|
||||
struct gic_chip_data {
|
||||
@ -434,6 +437,9 @@ static int gic_populate_rdist(void)
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (gic_data.redist_regions[i].single_redist)
|
||||
break;
|
||||
|
||||
if (gic_data.redist_stride) {
|
||||
ptr += gic_data.redist_stride;
|
||||
} else {
|
||||
@ -634,7 +640,7 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
|
||||
else
|
||||
gic_dist_wait_for_rwp();
|
||||
|
||||
return IRQ_SET_MASK_OK;
|
||||
return IRQ_SET_MASK_OK_DONE;
|
||||
}
|
||||
#else
|
||||
#define gic_set_affinity NULL
|
||||
@ -764,6 +770,15 @@ static int gic_irq_domain_translate(struct irq_domain *d,
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (is_fwnode_irqchip(fwspec->fwnode)) {
|
||||
if(fwspec->param_count != 2)
|
||||
return -EINVAL;
|
||||
|
||||
*hwirq = fwspec->param[0];
|
||||
*type = fwspec->param[1];
|
||||
return 0;
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
@ -811,17 +826,88 @@ static void gicv3_enable_quirks(void)
|
||||
#endif
|
||||
}
|
||||
|
||||
static int __init gic_init_bases(void __iomem *dist_base,
|
||||
struct redist_region *rdist_regs,
|
||||
u32 nr_redist_regions,
|
||||
u64 redist_stride,
|
||||
struct fwnode_handle *handle)
|
||||
{
|
||||
struct device_node *node;
|
||||
u32 typer;
|
||||
int gic_irqs;
|
||||
int err;
|
||||
|
||||
if (!is_hyp_mode_available())
|
||||
static_key_slow_dec(&supports_deactivate);
|
||||
|
||||
if (static_key_true(&supports_deactivate))
|
||||
pr_info("GIC: Using split EOI/Deactivate mode\n");
|
||||
|
||||
gic_data.dist_base = dist_base;
|
||||
gic_data.redist_regions = rdist_regs;
|
||||
gic_data.nr_redist_regions = nr_redist_regions;
|
||||
gic_data.redist_stride = redist_stride;
|
||||
|
||||
gicv3_enable_quirks();
|
||||
|
||||
/*
|
||||
* Find out how many interrupts are supported.
|
||||
* The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI)
|
||||
*/
|
||||
typer = readl_relaxed(gic_data.dist_base + GICD_TYPER);
|
||||
gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer);
|
||||
gic_irqs = GICD_TYPER_IRQS(typer);
|
||||
if (gic_irqs > 1020)
|
||||
gic_irqs = 1020;
|
||||
gic_data.irq_nr = gic_irqs;
|
||||
|
||||
gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops,
|
||||
&gic_data);
|
||||
gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist));
|
||||
|
||||
if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) {
|
||||
err = -ENOMEM;
|
||||
goto out_free;
|
||||
}
|
||||
|
||||
set_handle_irq(gic_handle_irq);
|
||||
|
||||
node = to_of_node(handle);
|
||||
if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis() &&
|
||||
node) /* Temp hack to prevent ITS init for ACPI */
|
||||
its_init(node, &gic_data.rdists, gic_data.domain);
|
||||
|
||||
gic_smp_init();
|
||||
gic_dist_init();
|
||||
gic_cpu_init();
|
||||
gic_cpu_pm_init();
|
||||
|
||||
return 0;
|
||||
|
||||
out_free:
|
||||
if (gic_data.domain)
|
||||
irq_domain_remove(gic_data.domain);
|
||||
free_percpu(gic_data.rdists.rdist);
|
||||
return err;
|
||||
}
|
||||
|
||||
static int __init gic_validate_dist_version(void __iomem *dist_base)
|
||||
{
|
||||
u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
|
||||
|
||||
if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4)
|
||||
return -ENODEV;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init gic_of_init(struct device_node *node, struct device_node *parent)
|
||||
{
|
||||
void __iomem *dist_base;
|
||||
struct redist_region *rdist_regs;
|
||||
u64 redist_stride;
|
||||
u32 nr_redist_regions;
|
||||
u32 typer;
|
||||
u32 reg;
|
||||
int gic_irqs;
|
||||
int err;
|
||||
int i;
|
||||
int err, i;
|
||||
|
||||
dist_base = of_iomap(node, 0);
|
||||
if (!dist_base) {
|
||||
@ -830,11 +916,10 @@ static int __init gic_of_init(struct device_node *node, struct device_node *pare
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
|
||||
if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) {
|
||||
err = gic_validate_dist_version(dist_base);
|
||||
if (err) {
|
||||
pr_err("%s: no distributor detected, giving up\n",
|
||||
node->full_name);
|
||||
err = -ENODEV;
|
||||
goto out_unmap_dist;
|
||||
}
|
||||
|
||||
@ -865,55 +950,11 @@ static int __init gic_of_init(struct device_node *node, struct device_node *pare
|
||||
if (of_property_read_u64(node, "redistributor-stride", &redist_stride))
|
||||
redist_stride = 0;
|
||||
|
||||
if (!is_hyp_mode_available())
|
||||
static_key_slow_dec(&supports_deactivate);
|
||||
err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions,
|
||||
redist_stride, &node->fwnode);
|
||||
if (!err)
|
||||
return 0;
|
||||
|
||||
if (static_key_true(&supports_deactivate))
|
||||
pr_info("GIC: Using split EOI/Deactivate mode\n");
|
||||
|
||||
gic_data.dist_base = dist_base;
|
||||
gic_data.redist_regions = rdist_regs;
|
||||
gic_data.nr_redist_regions = nr_redist_regions;
|
||||
gic_data.redist_stride = redist_stride;
|
||||
|
||||
gicv3_enable_quirks();
|
||||
|
||||
/*
|
||||
* Find out how many interrupts are supported.
|
||||
* The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI)
|
||||
*/
|
||||
typer = readl_relaxed(gic_data.dist_base + GICD_TYPER);
|
||||
gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer);
|
||||
gic_irqs = GICD_TYPER_IRQS(typer);
|
||||
if (gic_irqs > 1020)
|
||||
gic_irqs = 1020;
|
||||
gic_data.irq_nr = gic_irqs;
|
||||
|
||||
gic_data.domain = irq_domain_add_tree(node, &gic_irq_domain_ops,
|
||||
&gic_data);
|
||||
gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist));
|
||||
|
||||
if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) {
|
||||
err = -ENOMEM;
|
||||
goto out_free;
|
||||
}
|
||||
|
||||
set_handle_irq(gic_handle_irq);
|
||||
|
||||
if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())
|
||||
its_init(node, &gic_data.rdists, gic_data.domain);
|
||||
|
||||
gic_smp_init();
|
||||
gic_dist_init();
|
||||
gic_cpu_init();
|
||||
gic_cpu_pm_init();
|
||||
|
||||
return 0;
|
||||
|
||||
out_free:
|
||||
if (gic_data.domain)
|
||||
irq_domain_remove(gic_data.domain);
|
||||
free_percpu(gic_data.rdists.rdist);
|
||||
out_unmap_rdist:
|
||||
for (i = 0; i < nr_redist_regions; i++)
|
||||
if (rdist_regs[i].redist_base)
|
||||
@ -925,3 +966,213 @@ out_unmap_dist:
|
||||
}
|
||||
|
||||
IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
|
||||
|
||||
#ifdef CONFIG_ACPI
|
||||
static void __iomem *dist_base;
|
||||
static struct redist_region *redist_regs __initdata;
|
||||
static u32 nr_redist_regions __initdata;
|
||||
static bool single_redist;
|
||||
|
||||
static void __init
|
||||
gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base)
|
||||
{
|
||||
static int count = 0;
|
||||
|
||||
redist_regs[count].phys_base = phys_base;
|
||||
redist_regs[count].redist_base = redist_base;
|
||||
redist_regs[count].single_redist = single_redist;
|
||||
count++;
|
||||
}
|
||||
|
||||
static int __init
|
||||
gic_acpi_parse_madt_redist(struct acpi_subtable_header *header,
|
||||
const unsigned long end)
|
||||
{
|
||||
struct acpi_madt_generic_redistributor *redist =
|
||||
(struct acpi_madt_generic_redistributor *)header;
|
||||
void __iomem *redist_base;
|
||||
|
||||
redist_base = ioremap(redist->base_address, redist->length);
|
||||
if (!redist_base) {
|
||||
pr_err("Couldn't map GICR region @%llx\n", redist->base_address);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
gic_acpi_register_redist(redist->base_address, redist_base);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init
|
||||
gic_acpi_parse_madt_gicc(struct acpi_subtable_header *header,
|
||||
const unsigned long end)
|
||||
{
|
||||
struct acpi_madt_generic_interrupt *gicc =
|
||||
(struct acpi_madt_generic_interrupt *)header;
|
||||
u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
|
||||
u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2;
|
||||
void __iomem *redist_base;
|
||||
|
||||
redist_base = ioremap(gicc->gicr_base_address, size);
|
||||
if (!redist_base)
|
||||
return -ENOMEM;
|
||||
|
||||
gic_acpi_register_redist(gicc->gicr_base_address, redist_base);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init gic_acpi_collect_gicr_base(void)
|
||||
{
|
||||
acpi_tbl_entry_handler redist_parser;
|
||||
enum acpi_madt_type type;
|
||||
|
||||
if (single_redist) {
|
||||
type = ACPI_MADT_TYPE_GENERIC_INTERRUPT;
|
||||
redist_parser = gic_acpi_parse_madt_gicc;
|
||||
} else {
|
||||
type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR;
|
||||
redist_parser = gic_acpi_parse_madt_redist;
|
||||
}
|
||||
|
||||
/* Collect redistributor base addresses in GICR entries */
|
||||
if (acpi_table_parse_madt(type, redist_parser, 0) > 0)
|
||||
return 0;
|
||||
|
||||
pr_info("No valid GICR entries exist\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static int __init gic_acpi_match_gicr(struct acpi_subtable_header *header,
|
||||
const unsigned long end)
|
||||
{
|
||||
/* Subtable presence means that redist exists, that's it */
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init gic_acpi_match_gicc(struct acpi_subtable_header *header,
|
||||
const unsigned long end)
|
||||
{
|
||||
struct acpi_madt_generic_interrupt *gicc =
|
||||
(struct acpi_madt_generic_interrupt *)header;
|
||||
|
||||
/*
|
||||
* If GICC is enabled and has valid gicr base address, then it means
|
||||
* GICR base is presented via GICC
|
||||
*/
|
||||
if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address)
|
||||
return 0;
|
||||
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static int __init gic_acpi_count_gicr_regions(void)
|
||||
{
|
||||
int count;
|
||||
|
||||
/*
|
||||
* Count how many redistributor regions we have. It is not allowed
|
||||
* to mix redistributor description, GICR and GICC subtables have to be
|
||||
* mutually exclusive.
|
||||
*/
|
||||
count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
|
||||
gic_acpi_match_gicr, 0);
|
||||
if (count > 0) {
|
||||
single_redist = false;
|
||||
return count;
|
||||
}
|
||||
|
||||
count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
|
||||
gic_acpi_match_gicc, 0);
|
||||
if (count > 0)
|
||||
single_redist = true;
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header,
|
||||
struct acpi_probe_entry *ape)
|
||||
{
|
||||
struct acpi_madt_generic_distributor *dist;
|
||||
int count;
|
||||
|
||||
dist = (struct acpi_madt_generic_distributor *)header;
|
||||
if (dist->version != ape->driver_data)
|
||||
return false;
|
||||
|
||||
/* We need to do that exercise anyway, the sooner the better */
|
||||
count = gic_acpi_count_gicr_regions();
|
||||
if (count <= 0)
|
||||
return false;
|
||||
|
||||
nr_redist_regions = count;
|
||||
return true;
|
||||
}
|
||||
|
||||
#define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K)
|
||||
|
||||
static int __init
|
||||
gic_acpi_init(struct acpi_subtable_header *header, const unsigned long end)
|
||||
{
|
||||
struct acpi_madt_generic_distributor *dist;
|
||||
struct fwnode_handle *domain_handle;
|
||||
int i, err;
|
||||
|
||||
/* Get distributor base address */
|
||||
dist = (struct acpi_madt_generic_distributor *)header;
|
||||
dist_base = ioremap(dist->base_address, ACPI_GICV3_DIST_MEM_SIZE);
|
||||
if (!dist_base) {
|
||||
pr_err("Unable to map GICD registers\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
err = gic_validate_dist_version(dist_base);
|
||||
if (err) {
|
||||
pr_err("No distributor detected at @%p, giving up", dist_base);
|
||||
goto out_dist_unmap;
|
||||
}
|
||||
|
||||
redist_regs = kzalloc(sizeof(*redist_regs) * nr_redist_regions,
|
||||
GFP_KERNEL);
|
||||
if (!redist_regs) {
|
||||
err = -ENOMEM;
|
||||
goto out_dist_unmap;
|
||||
}
|
||||
|
||||
err = gic_acpi_collect_gicr_base();
|
||||
if (err)
|
||||
goto out_redist_unmap;
|
||||
|
||||
domain_handle = irq_domain_alloc_fwnode(dist_base);
|
||||
if (!domain_handle) {
|
||||
err = -ENOMEM;
|
||||
goto out_redist_unmap;
|
||||
}
|
||||
|
||||
err = gic_init_bases(dist_base, redist_regs, nr_redist_regions, 0,
|
||||
domain_handle);
|
||||
if (err)
|
||||
goto out_fwhandle_free;
|
||||
|
||||
acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
|
||||
return 0;
|
||||
|
||||
out_fwhandle_free:
|
||||
irq_domain_free_fwnode(domain_handle);
|
||||
out_redist_unmap:
|
||||
for (i = 0; i < nr_redist_regions; i++)
|
||||
if (redist_regs[i].redist_base)
|
||||
iounmap(redist_regs[i].redist_base);
|
||||
kfree(redist_regs);
|
||||
out_dist_unmap:
|
||||
iounmap(dist_base);
|
||||
return err;
|
||||
}
|
||||
IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
|
||||
acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3,
|
||||
gic_acpi_init);
|
||||
IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
|
||||
acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4,
|
||||
gic_acpi_init);
|
||||
IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
|
||||
acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE,
|
||||
gic_acpi_init);
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user