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drm/i915: Compute sink's max lane count/link BW at Hotplug

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Sink's capabilities are advertised through DPCD registers and get
updated only on hotplug. So they should be computed only once in the
long pulse handler and saved off in intel_dp structure for the use
later. For this reason two new fields max_sink_lane_count and
max_sink_link_bw are added to intel_dp structure.

This also simplifies the fallback link rate/lane count logic
to handle link training failure. In that case, the max_sink_link_bw
and max_sink_lane_count can be reccomputed to match the fallback
values lowering the sink capabilities due to link train failure.

Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1480984058-552-3-git-send-email-manasi.d.navare@intel.com
This commit is contained in:
Manasi Navare 2016-12-05 16:27:36 -08:00 committed by Jani Nikula
parent 213e08ad60
commit f482984acb
2 changed files with 12 additions and 2 deletions
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10
drivers/gpu/drm/i915/intel_dp.c
View File

@ -156,7 +156,7 @@ static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
u8 source_max, sink_max;
source_max = intel_dig_port->max_lanes;
sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
sink_max = intel_dp->max_sink_lane_count;
return min(source_max, sink_max);
}
@ -213,7 +213,7 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
*sink_rates = default_rates;
return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
return (intel_dp->max_sink_link_bw >> 3) + 1;
}
static int
@ -4395,6 +4395,12 @@ intel_dp_long_pulse(struct intel_connector *intel_connector)
yesno(intel_dp_source_supports_hbr2(intel_dp)),
yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
/* Set the max lane count for sink */
intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
/* Set the max link BW for sink */
intel_dp->max_sink_link_bw = intel_dp_max_link_bw(intel_dp);
intel_dp_print_rates(intel_dp);
intel_dp_read_desc(intel_dp);

4
drivers/gpu/drm/i915/intel_drv.h
View File

@ -906,6 +906,10 @@ struct intel_dp {
/* sink rates as reported by DP_SUPPORTED_LINK_RATES */
uint8_t num_sink_rates;
int sink_rates[DP_MAX_SUPPORTED_RATES];
/* Max lane count for the sink as per DPCD registers */
uint8_t max_sink_lane_count;
/* Max link BW for the sink as per DPCD registers */
int max_sink_link_bw;
/* sink or branch descriptor */
struct intel_dp_desc desc;
struct drm_dp_aux aux;