forked from Minki/linux
drm/i915: create pipe_config->dpll for clock state
Clock computations and handling are highly encoder specific, both in the optimal clock selection and also in which clocks to use and when sharing of clocks is possible. So the best place to do this is somewhere in the encoders, with a generic fallback for those encoders without special needs. To facility this, add a pipe_config->clocks_set boolean. This patch here is only prep work, it simply sets the computed clock values in pipe_config->dpll, and uses that data in the hw clock setting functions. Haswell code isn't touched, simply because Haswell clocks work much different and need their own infrastructure (with probably a Haswell-specific config->ddi_clock substruct). Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Daniel Vetter
parent
88adfff1ad
commit
f47709a950
@ -4138,37 +4138,38 @@ static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
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return refclk;
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}
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static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
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intel_clock_t *clock)
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static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc *crtc)
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{
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unsigned dotclock = crtc->config.adjusted_mode.clock;
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struct dpll *clock = &crtc->config.dpll;
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/* SDVO TV has fixed PLL values depend on its clock range,
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this mirrors vbios setting. */
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if (adjusted_mode->clock >= 100000
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&& adjusted_mode->clock < 140500) {
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if (dotclock >= 100000 && dotclock < 140500) {
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clock->p1 = 2;
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clock->p2 = 10;
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clock->n = 3;
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clock->m1 = 16;
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clock->m2 = 8;
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} else if (adjusted_mode->clock >= 140500
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&& adjusted_mode->clock <= 200000) {
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} else if (dotclock >= 140500 && dotclock <= 200000) {
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clock->p1 = 1;
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clock->p2 = 10;
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clock->n = 6;
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clock->m1 = 12;
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clock->m2 = 8;
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}
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crtc->config.clock_set = true;
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}
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static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
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intel_clock_t *clock,
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static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
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intel_clock_t *reduced_clock)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pipe = intel_crtc->pipe;
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int pipe = crtc->pipe;
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u32 fp, fp2 = 0;
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struct dpll *clock = &crtc->config.dpll;
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if (IS_PINEVIEW(dev)) {
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fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
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@ -4184,11 +4185,11 @@ static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
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I915_WRITE(FP0(pipe), fp);
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intel_crtc->lowfreq_avail = false;
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
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crtc->lowfreq_avail = false;
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if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
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reduced_clock && i915_powersave) {
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I915_WRITE(FP1(pipe), fp2);
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intel_crtc->lowfreq_avail = true;
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crtc->lowfreq_avail = true;
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} else {
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I915_WRITE(FP1(pipe), fp);
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}
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@ -4202,14 +4203,11 @@ static void intel_dp_set_m_n(struct intel_crtc *crtc)
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intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
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}
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static void vlv_update_pll(struct drm_crtc *crtc,
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intel_clock_t *clock, intel_clock_t *reduced_clock,
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int num_connectors)
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static void vlv_update_pll(struct intel_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pipe = intel_crtc->pipe;
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int pipe = crtc->pipe;
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u32 dpll, mdiv, pdiv;
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u32 bestn, bestm1, bestm2, bestp1, bestp2;
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bool is_sdvo;
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@ -4217,8 +4215,8 @@ static void vlv_update_pll(struct drm_crtc *crtc,
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mutex_lock(&dev_priv->dpio_lock);
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is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
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intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
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is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
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intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
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dpll = DPLL_VGA_MODE_DIS;
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dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
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@ -4228,11 +4226,11 @@ static void vlv_update_pll(struct drm_crtc *crtc,
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I915_WRITE(DPLL(pipe), dpll);
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POSTING_READ(DPLL(pipe));
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bestn = clock->n;
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bestm1 = clock->m1;
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bestm2 = clock->m2;
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bestp1 = clock->p1;
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bestp2 = clock->p2;
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bestn = crtc->config.dpll.n;
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bestm1 = crtc->config.dpll.m1;
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bestm2 = crtc->config.dpll.m2;
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bestp1 = crtc->config.dpll.p1;
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bestp2 = crtc->config.dpll.p2;
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/*
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* In Valleyview PLL and program lane counter registers are exposed
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@ -4264,8 +4262,8 @@ static void vlv_update_pll(struct drm_crtc *crtc,
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intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
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if (intel_crtc->config.has_dp_encoder)
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intel_dp_set_m_n(intel_crtc);
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if (crtc->config.has_dp_encoder)
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intel_dp_set_m_n(crtc);
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I915_WRITE(DPLL(pipe), dpll);
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@ -4276,8 +4274,8 @@ static void vlv_update_pll(struct drm_crtc *crtc,
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temp = 0;
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if (is_sdvo) {
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temp = 0;
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if (intel_crtc->config.pixel_multiplier > 1) {
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temp = (intel_crtc->config.pixel_multiplier - 1)
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if (crtc->config.pixel_multiplier > 1) {
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temp = (crtc->config.pixel_multiplier - 1)
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<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
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}
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}
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@ -4285,16 +4283,15 @@ static void vlv_update_pll(struct drm_crtc *crtc,
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POSTING_READ(DPLL_MD(pipe));
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/* Now program lane control registers */
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if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
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|| intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
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{
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if(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)
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|| intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
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temp = 0x1000C4;
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if(pipe == 1)
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temp |= (1 << 21);
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intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
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}
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if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
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{
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if(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) {
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temp = 0x1000C4;
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if(pipe == 1)
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temp |= (1 << 21);
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@ -4304,39 +4301,39 @@ static void vlv_update_pll(struct drm_crtc *crtc,
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mutex_unlock(&dev_priv->dpio_lock);
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}
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static void i9xx_update_pll(struct drm_crtc *crtc,
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intel_clock_t *clock, intel_clock_t *reduced_clock,
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static void i9xx_update_pll(struct intel_crtc *crtc,
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intel_clock_t *reduced_clock,
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int num_connectors)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct intel_encoder *encoder;
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int pipe = intel_crtc->pipe;
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int pipe = crtc->pipe;
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u32 dpll;
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bool is_sdvo;
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struct dpll *clock = &crtc->config.dpll;
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i9xx_update_pll_dividers(crtc, clock, reduced_clock);
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i9xx_update_pll_dividers(crtc, reduced_clock);
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is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
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intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
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is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
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intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
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dpll = DPLL_VGA_MODE_DIS;
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
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if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
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dpll |= DPLLB_MODE_LVDS;
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else
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dpll |= DPLLB_MODE_DAC_SERIAL;
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if (is_sdvo) {
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if ((intel_crtc->config.pixel_multiplier > 1) &&
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if ((crtc->config.pixel_multiplier > 1) &&
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(IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
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dpll |= (intel_crtc->config.pixel_multiplier - 1)
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dpll |= (crtc->config.pixel_multiplier - 1)
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<< SDVO_MULTIPLIER_SHIFT_HIRES;
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}
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dpll |= DPLL_DVO_HIGH_SPEED;
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}
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
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if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
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dpll |= DPLL_DVO_HIGH_SPEED;
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/* compute bitmask from p1 value */
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@ -4364,13 +4361,13 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
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if (INTEL_INFO(dev)->gen >= 4)
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dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
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if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
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if (is_sdvo && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
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dpll |= PLL_REF_INPUT_TVCLKINBC;
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else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
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else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
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/* XXX: just matching BIOS for now */
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/* dpll |= PLL_REF_INPUT_TVCLKINBC; */
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dpll |= 3;
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else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
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else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
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intel_panel_use_ssc(dev_priv) && num_connectors < 2)
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dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
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else
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@ -4381,12 +4378,12 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
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POSTING_READ(DPLL(pipe));
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udelay(150);
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for_each_encoder_on_crtc(dev, crtc, encoder)
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for_each_encoder_on_crtc(dev, &crtc->base, encoder)
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if (encoder->pre_pll_enable)
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encoder->pre_pll_enable(encoder);
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if (intel_crtc->config.has_dp_encoder)
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intel_dp_set_m_n(intel_crtc);
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if (crtc->config.has_dp_encoder)
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intel_dp_set_m_n(crtc);
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I915_WRITE(DPLL(pipe), dpll);
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@ -4398,8 +4395,8 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
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u32 temp = 0;
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if (is_sdvo) {
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temp = 0;
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if (intel_crtc->config.pixel_multiplier > 1) {
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temp = (intel_crtc->config.pixel_multiplier - 1)
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if (crtc->config.pixel_multiplier > 1) {
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temp = (crtc->config.pixel_multiplier - 1)
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<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
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}
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}
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@ -4414,23 +4411,23 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
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}
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}
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static void i8xx_update_pll(struct drm_crtc *crtc,
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static void i8xx_update_pll(struct intel_crtc *crtc,
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struct drm_display_mode *adjusted_mode,
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intel_clock_t *clock, intel_clock_t *reduced_clock,
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intel_clock_t *reduced_clock,
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int num_connectors)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct intel_encoder *encoder;
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int pipe = intel_crtc->pipe;
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int pipe = crtc->pipe;
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u32 dpll;
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struct dpll *clock = &crtc->config.dpll;
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i9xx_update_pll_dividers(crtc, clock, reduced_clock);
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i9xx_update_pll_dividers(crtc, reduced_clock);
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dpll = DPLL_VGA_MODE_DIS;
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
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if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
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dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
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} else {
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if (clock->p1 == 2)
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@ -4441,7 +4438,7 @@ static void i8xx_update_pll(struct drm_crtc *crtc,
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dpll |= PLL_P2_DIVIDE_BY_4;
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}
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
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if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
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intel_panel_use_ssc(dev_priv) && num_connectors < 2)
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dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
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else
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@ -4452,7 +4449,7 @@ static void i8xx_update_pll(struct drm_crtc *crtc,
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POSTING_READ(DPLL(pipe));
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udelay(150);
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for_each_encoder_on_crtc(dev, crtc, encoder)
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for_each_encoder_on_crtc(dev, &crtc->base, encoder)
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if (encoder->pre_pll_enable)
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encoder->pre_pll_enable(encoder);
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@ -4599,20 +4596,26 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
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&clock,
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&reduced_clock);
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}
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/* Compat-code for transition, will disappear. */
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if (!intel_crtc->config.clock_set) {
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intel_crtc->config.dpll.n = clock.n;
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intel_crtc->config.dpll.m1 = clock.m1;
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intel_crtc->config.dpll.m2 = clock.m2;
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intel_crtc->config.dpll.p1 = clock.p1;
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intel_crtc->config.dpll.p2 = clock.p2;
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}
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if (is_sdvo && is_tv)
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i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
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i9xx_adjust_sdvo_tv_clock(intel_crtc);
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if (IS_GEN2(dev))
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i8xx_update_pll(crtc, adjusted_mode, &clock,
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i8xx_update_pll(intel_crtc, adjusted_mode,
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has_reduced_clock ? &reduced_clock : NULL,
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num_connectors);
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else if (IS_VALLEYVIEW(dev))
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vlv_update_pll(crtc, &clock,
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has_reduced_clock ? &reduced_clock : NULL,
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num_connectors);
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vlv_update_pll(intel_crtc);
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else
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i9xx_update_pll(crtc, &clock,
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i9xx_update_pll(intel_crtc,
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has_reduced_clock ? &reduced_clock : NULL,
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num_connectors);
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@ -5280,7 +5283,7 @@ static bool ironlake_compute_clocks(struct drm_crtc *crtc,
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}
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if (is_sdvo && is_tv)
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i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
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i9xx_adjust_sdvo_tv_clock(to_intel_crtc(crtc));
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return true;
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}
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@ -5584,6 +5587,14 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
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DRM_ERROR("Couldn't find PLL settings for mode!\n");
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return -EINVAL;
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}
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/* Compat-code for transition, will disappear. */
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if (!intel_crtc->config.clock_set) {
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intel_crtc->config.dpll.n = clock.n;
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intel_crtc->config.dpll.m1 = clock.m1;
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intel_crtc->config.dpll.m2 = clock.m2;
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intel_crtc->config.dpll.p1 = clock.p1;
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intel_crtc->config.dpll.p2 = clock.p2;
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}
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/* Ensure that the cursor is valid for the new mode before changing... */
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intel_crtc_update_cursor(crtc, true);
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@ -194,6 +194,18 @@ struct intel_crtc_config {
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* accordingly. */
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bool has_dp_encoder;
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bool dither;
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/* Controls for the clock computation, to override various stages. */
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bool clock_set;
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/* Settings for the intel dpll used on pretty much everything but
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* haswell. */
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struct dpll {
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unsigned n;
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unsigned m1, m2;
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unsigned p1, p2;
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} dpll;
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int pipe_bpp;
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struct intel_link_m_n dp_m_n;
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/**
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