forked from Minki/linux
MIPS: lantiq: enable pci clk conditional for xrx200 SoC
The xrx200 SoC family has the same PCI clock register layout as the AR9. Enable the same quirk as for AR9 Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4235/
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@ -145,7 +145,8 @@ static int pci_enable(struct clk *clk)
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{
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unsigned int val = ltq_cgu_r32(ifccr);
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/* set bus clock speed */
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if (of_machine_is_compatible("lantiq,ar9")) {
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if (of_machine_is_compatible("lantiq,ar9") ||
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of_machine_is_compatible("lantiq,vr9")) {
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val &= ~0x1f00000;
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if (clk->rate == CLOCK_33M)
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val |= 0xe00000;
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