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drm/amd/powerplay: drop unnecessary get_pptable_power_limit wrappers

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Minor code cleanup.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Evan Quan 2020-06-08 14:34:50 +08:00 committed by Alex Deucher
parent f6b4b4a1db
commit f3bc9aeceb
5 changed files with 3 additions and 19 deletions
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10
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
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@ -2827,13 +2827,3 @@ int smu_get_dpm_clock_table(struct smu_context *smu,
return ret;
}
uint32_t smu_get_pptable_power_limit(struct smu_context *smu)
{
uint32_t ret = 0;
if (smu->ppt_funcs->get_pptable_power_limit)
ret = smu->ppt_funcs->get_pptable_power_limit(smu);
return ret;
}

3
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
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@ -2561,7 +2561,7 @@ static uint32_t atcturus_get_max_power_limit(struct smu_context *smu) {
struct smu_table_context *table_context = &smu->smu_table;
powerplay_table = table_context->power_play_table;
max_power_limit = smu_get_pptable_power_limit(smu);
max_power_limit = arcturus_get_pptable_power_limit(smu);
if (!max_power_limit) {
// If we couldn't get the table limit, fall back on first-read value
@ -2669,7 +2669,6 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
.get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
.set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
.override_pcie_parameters = NULL,
.get_pptable_power_limit = arcturus_get_pptable_power_limit,
.set_df_cstate = arcturus_set_df_cstate,
.allow_xgmi_power_down = arcturus_allow_xgmi_power_down,
.log_thermal_throttling_event = arcturus_log_thermal_throttling_event,

3
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
View File

@ -567,7 +567,6 @@ struct pptable_funcs {
int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max);
int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max);
int (*override_pcie_parameters)(struct smu_context *smu);
uint32_t (*get_pptable_power_limit)(struct smu_context *smu);
int (*disable_umc_cdr_12gbps_workaround)(struct smu_context *smu);
int (*set_power_source)(struct smu_context *smu, enum smu_power_src_type power_src);
void (*log_thermal_throttling_event)(struct smu_context *smu);
@ -767,6 +766,4 @@ int smu_get_uclk_dpm_states(struct smu_context *smu,
int smu_get_dpm_clock_table(struct smu_context *smu,
struct dpm_clocks *clock_table);
uint32_t smu_get_pptable_power_limit(struct smu_context *smu);
#endif

3
drivers/gpu/drm/amd/powerplay/navi10_ppt.c
View File

@ -2397,7 +2397,7 @@ static uint32_t navi10_get_max_power_limit(struct smu_context *smu) {
struct smu_table_context *table_context = &smu->smu_table;
powerplay_table = table_context->power_play_table;
max_power_limit = smu_get_pptable_power_limit(smu);
max_power_limit = navi10_get_pptable_power_limit(smu);
if (!max_power_limit) {
// If we couldn't get the table limit, fall back on first-read value
@ -2504,7 +2504,6 @@ static const struct pptable_funcs navi10_ppt_funcs = {
.override_pcie_parameters = smu_v11_0_override_pcie_parameters,
.set_default_od_settings = navi10_set_default_od_settings,
.od_edit_dpm_table = navi10_od_edit_dpm_table,
.get_pptable_power_limit = navi10_get_pptable_power_limit,
.run_btc = navi10_run_btc,
.disable_umc_cdr_12gbps_workaround = navi10_disable_umc_cdr_12gbps_workaround,
.set_power_source = smu_v11_0_set_power_source,

3
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
View File

@ -1903,7 +1903,7 @@ static uint32_t sienna_cichlid_get_max_power_limit(struct smu_context *smu) {
struct smu_table_context *table_context = &smu->smu_table;
powerplay_table = table_context->power_play_table;
max_power_limit = smu_get_pptable_power_limit(smu);
max_power_limit = sienna_cichlid_get_pptable_power_limit(smu);
if (!max_power_limit) {
// If we couldn't get the table limit, fall back on first-read value
@ -2674,7 +2674,6 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
.get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
.set_soft_freq_limited_range = sienna_cichlid_set_soft_freq_limited_range,
.override_pcie_parameters = smu_v11_0_override_pcie_parameters,
.get_pptable_power_limit = sienna_cichlid_get_pptable_power_limit,
.set_thermal_range = sienna_cichlid_set_thermal_range,
.get_max_power_limit = sienna_cichlid_get_max_power_limit,
};