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The i.MX SoC update for 4.6:

Browse Source 
- Enable big endian mode support for i.MX platform
 - Add support for i.MX6QP SoC which is the latest i.MX6 family addition
 - Add basic suspend/resume support for i.MX25
 - A couple of i.MX7D support updates
 - A few random code cleanups
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Merge tag 'imx-soc-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/soc

Merge "i.MX SoC update for 4.6" from Shawn Guo:

- Enable big endian mode support for i.MX platform
- Add support for i.MX6QP SoC which is the latest i.MX6 family addition
- Add basic suspend/resume support for i.MX25
- A couple of i.MX7D support updates
- A few random code cleanups

* tag 'imx-soc-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  ARM: imx: Make reset_control_ops const
  ARM: imx: Do L2 errata only if the L2 cache isn't enabled
  ARM: imx: select ARM_CPU_SUSPEND only for imx6
  ARM: mx25: Add basic suspend/resume support
  ARM: imx: Add msl code support for imx6qp
  ARM: imx: enable big endian mode
  ARM: imx: use endian-safe readl/readw/writel/writew
  ARM: imx7d: correct chip version information
  ARM: imx: select HAVE_ARM_ARCH_TIMER if selected i.MX7D
  ARM: imx6: fix cleanup path in imx6q_suspend_init()
This commit is contained in:
Arnd Bergmann 2016-03-02 23:30:17 +01:00
commit f3a186fbfd
33 changed files with 203 additions and 132 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/include/debug/imx.S
View File

@ -11,6 +11,7 @@
* *
*/ */
#include <asm/assembler.h>
#include "imx-uart.h" #include "imx-uart.h"
/* /*
@ -34,6 +35,7 @@
.endm .endm
.macro senduart,rd,rx .macro senduart,rd,rx
ARM_BE8(rev \rd, \rd)
str \rd, [\rx, #0x40] @ TXDATA str \rd, [\rx, #0x40] @ TXDATA
.endm .endm
@ -42,6 +44,7 @@
.macro busyuart,rd,rx .macro busyuart,rd,rx
1002: ldr \rd, [\rx, #0x98] @ SR2 1002: ldr \rd, [\rx, #0x98] @ SR2
ARM_BE8(rev \rd, \rd)
tst \rd, #1 << 3 @ TXDC tst \rd, #1 << 3 @ TXDC
beq 1002b @ wait until transmit done beq 1002b @ wait until transmit done
.endm .endm

30
arch/arm/mach-imx/3ds_debugboard.c
View File

@ -94,8 +94,8 @@ static void mxc_expio_irq_handler(struct irq_desc *desc)
/* irq = gpio irq number */ /* irq = gpio irq number */
desc->irq_data.chip->irq_mask(&desc->irq_data); desc->irq_data.chip->irq_mask(&desc->irq_data);
imr_val = __raw_readw(brd_io + INTR_MASK_REG); imr_val = imx_readw(brd_io + INTR_MASK_REG);
int_valid = __raw_readw(brd_io + INTR_STATUS_REG) & ~imr_val; int_valid = imx_readw(brd_io + INTR_STATUS_REG) & ~imr_val;
expio_irq = 0; expio_irq = 0;
for (; int_valid != 0; int_valid >>= 1, expio_irq++) { for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
@ -117,17 +117,17 @@ static void expio_mask_irq(struct irq_data *d)
u16 reg; u16 reg;
u32 expio = d->hwirq; u32 expio = d->hwirq;
reg = __raw_readw(brd_io + INTR_MASK_REG); reg = imx_readw(brd_io + INTR_MASK_REG);
reg |= (1 << expio); reg |= (1 << expio);
__raw_writew(reg, brd_io + INTR_MASK_REG); imx_writew(reg, brd_io + INTR_MASK_REG);
} }
static void expio_ack_irq(struct irq_data *d) static void expio_ack_irq(struct irq_data *d)
{ {
u32 expio = d->hwirq; u32 expio = d->hwirq;
__raw_writew(1 << expio, brd_io + INTR_RESET_REG); imx_writew(1 << expio, brd_io + INTR_RESET_REG);
__raw_writew(0, brd_io + INTR_RESET_REG); imx_writew(0, brd_io + INTR_RESET_REG);
expio_mask_irq(d); expio_mask_irq(d);
} }
@ -136,9 +136,9 @@ static void expio_unmask_irq(struct irq_data *d)
u16 reg; u16 reg;
u32 expio = d->hwirq; u32 expio = d->hwirq;
reg = __raw_readw(brd_io + INTR_MASK_REG); reg = imx_readw(brd_io + INTR_MASK_REG);
reg &= ~(1 << expio); reg &= ~(1 << expio);
__raw_writew(reg, brd_io + INTR_MASK_REG); imx_writew(reg, brd_io + INTR_MASK_REG);
} }
static struct irq_chip expio_irq_chip = { static struct irq_chip expio_irq_chip = {
@ -162,9 +162,9 @@ int __init mxc_expio_init(u32 base, u32 intr_gpio)
if (brd_io == NULL) if (brd_io == NULL)
return -ENOMEM; return -ENOMEM;
if ((__raw_readw(brd_io + MAGIC_NUMBER1_REG) != 0xAAAA) || if ((imx_readw(brd_io + MAGIC_NUMBER1_REG) != 0xAAAA) ||
(__raw_readw(brd_io + MAGIC_NUMBER2_REG) != 0x5555) || (imx_readw(brd_io + MAGIC_NUMBER2_REG) != 0x5555) ||
(__raw_readw(brd_io + MAGIC_NUMBER3_REG) != 0xCAFE)) { (imx_readw(brd_io + MAGIC_NUMBER3_REG) != 0xCAFE)) {
pr_info("3-Stack Debug board not detected\n"); pr_info("3-Stack Debug board not detected\n");
iounmap(brd_io); iounmap(brd_io);
brd_io = NULL; brd_io = NULL;
@ -181,10 +181,10 @@ int __init mxc_expio_init(u32 base, u32 intr_gpio)
gpio_direction_input(intr_gpio); gpio_direction_input(intr_gpio);
/* disable the interrupt and clear the status */ /* disable the interrupt and clear the status */
__raw_writew(0, brd_io + INTR_MASK_REG); imx_writew(0, brd_io + INTR_MASK_REG);
__raw_writew(0xFFFF, brd_io + INTR_RESET_REG); imx_writew(0xFFFF, brd_io + INTR_RESET_REG);
__raw_writew(0, brd_io + INTR_RESET_REG); imx_writew(0, brd_io + INTR_RESET_REG);
__raw_writew(0x1F, brd_io + INTR_MASK_REG); imx_writew(0x1F, brd_io + INTR_MASK_REG);
irq_base = irq_alloc_descs(-1, 0, MXC_MAX_EXP_IO_LINES, numa_node_id()); irq_base = irq_alloc_descs(-1, 0, MXC_MAX_EXP_IO_LINES, numa_node_id());
WARN_ON(irq_base < 0); WARN_ON(irq_base < 0);

4
arch/arm/mach-imx/Kconfig
View File

@ -2,7 +2,7 @@ menuconfig ARCH_MXC
bool "Freescale i.MX family" bool "Freescale i.MX family"
depends on ARCH_MULTI_V4_V5 || ARCH_MULTI_V6_V7 || ARM_SINGLE_ARMV7M depends on ARCH_MULTI_V4_V5 || ARCH_MULTI_V6_V7 || ARM_SINGLE_ARMV7M
select ARCH_REQUIRE_GPIOLIB select ARCH_REQUIRE_GPIOLIB
select ARM_CPU_SUSPEND if PM select ARCH_SUPPORTS_BIG_ENDIAN
select CLKSRC_IMX_GPT select CLKSRC_IMX_GPT
select GENERIC_IRQ_CHIP select GENERIC_IRQ_CHIP
select PINCTRL select PINCTRL
@ -511,6 +511,7 @@ config SOC_IMX53
config SOC_IMX6 config SOC_IMX6
bool bool
select ARM_CPU_SUSPEND if PM
select ARM_ERRATA_754322 select ARM_ERRATA_754322
select ARM_ERRATA_775420 select ARM_ERRATA_775420
select ARM_GIC select ARM_GIC
@ -561,6 +562,7 @@ config SOC_IMX7D
bool "i.MX7 Dual support" bool "i.MX7 Dual support"
select PINCTRL_IMX7D select PINCTRL_IMX7D
select ARM_GIC select ARM_GIC
select HAVE_ARM_ARCH_TIMER
select HAVE_IMX_ANATOP select HAVE_IMX_ANATOP
select HAVE_IMX_MMDC select HAVE_IMX_MMDC
select HAVE_IMX_SRC select HAVE_IMX_SRC

2
arch/arm/mach-imx/Makefile
View File

@ -3,7 +3,7 @@ obj-y := cpu.o system.o irq-common.o
obj-$(CONFIG_SOC_IMX1) += mm-imx1.o obj-$(CONFIG_SOC_IMX1) += mm-imx1.o
obj-$(CONFIG_SOC_IMX21) += mm-imx21.o obj-$(CONFIG_SOC_IMX21) += mm-imx21.o
obj-$(CONFIG_SOC_IMX25) += cpu-imx25.o mach-imx25.o obj-$(CONFIG_SOC_IMX25) += cpu-imx25.o mach-imx25.o pm-imx25.o
obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o
obj-$(CONFIG_SOC_IMX27) += mm-imx27.o ehci-imx27.o obj-$(CONFIG_SOC_IMX27) += mm-imx27.o ehci-imx27.o

18
arch/arm/mach-imx/anatop.c
View File

@ -129,7 +129,14 @@ void __init imx_init_revision_from_anatop(void)
switch (digprog & 0xff) { switch (digprog & 0xff) {
case 0: case 0:
revision = IMX_CHIP_REVISION_1_0; /*
* For i.MX6QP, most of the code for i.MX6Q can be resued,
* so internally, we identify it as i.MX6Q Rev 2.0
*/
if (digprog >> 8 & 0x01)
revision = IMX_CHIP_REVISION_2_0;
else
revision = IMX_CHIP_REVISION_1_0;
break; break;
case 1: case 1:
revision = IMX_CHIP_REVISION_1_1; revision = IMX_CHIP_REVISION_1_1;
@ -151,7 +158,14 @@ void __init imx_init_revision_from_anatop(void)
revision = IMX_CHIP_REVISION_1_5; revision = IMX_CHIP_REVISION_1_5;
break; break;
default: default:
revision = IMX_CHIP_REVISION_UNKNOWN; /*
* Fail back to return raw register value instead of 0xff.
* It will be easy to know version information in SOC if it
* can't be recognized by known version. And some chip's (i.MX7D)
* digprog value match linux version format, so it needn't map
* again and we can use register value directly.
*/
revision = digprog & 0xff;
} }
mxc_set_cpu_type(digprog >> 16 & 0xff); mxc_set_cpu_type(digprog >> 16 & 0xff);

30
arch/arm/mach-imx/avic.c
View File

@ -66,12 +66,12 @@ static int avic_set_irq_fiq(unsigned int irq, unsigned int type)
return -EINVAL; return -EINVAL;
if (irq < AVIC_NUM_IRQS / 2) { if (irq < AVIC_NUM_IRQS / 2) {
irqt = __raw_readl(avic_base + AVIC_INTTYPEL) & ~(1 << irq); irqt = imx_readl(avic_base + AVIC_INTTYPEL) & ~(1 << irq);
__raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEL); imx_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEL);
} else { } else {
irq -= AVIC_NUM_IRQS / 2; irq -= AVIC_NUM_IRQS / 2;
irqt = __raw_readl(avic_base + AVIC_INTTYPEH) & ~(1 << irq); irqt = imx_readl(avic_base + AVIC_INTTYPEH) & ~(1 << irq);
__raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEH); imx_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEH);
} }
return 0; return 0;
@ -94,8 +94,8 @@ static void avic_irq_suspend(struct irq_data *d)
struct irq_chip_type *ct = gc->chip_types; struct irq_chip_type *ct = gc->chip_types;
int idx = d->hwirq >> 5; int idx = d->hwirq >> 5;
avic_saved_mask_reg[idx] = __raw_readl(avic_base + ct->regs.mask); avic_saved_mask_reg[idx] = imx_readl(avic_base + ct->regs.mask);
__raw_writel(gc->wake_active, avic_base + ct->regs.mask); imx_writel(gc->wake_active, avic_base + ct->regs.mask);
} }
static void avic_irq_resume(struct irq_data *d) static void avic_irq_resume(struct irq_data *d)
@ -104,7 +104,7 @@ static void avic_irq_resume(struct irq_data *d)
struct irq_chip_type *ct = gc->chip_types; struct irq_chip_type *ct = gc->chip_types;
int idx = d->hwirq >> 5; int idx = d->hwirq >> 5;
__raw_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask); imx_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask);
} }
#else #else
@ -140,7 +140,7 @@ static void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
u32 nivector; u32 nivector;
do { do {
nivector = __raw_readl(avic_base + AVIC_NIVECSR) >> 16; nivector = imx_readl(avic_base + AVIC_NIVECSR) >> 16;
if (nivector == 0xffff) if (nivector == 0xffff)
break; break;
@ -164,16 +164,16 @@ void __init mxc_init_irq(void __iomem *irqbase)
/* put the AVIC into the reset value with /* put the AVIC into the reset value with
* all interrupts disabled * all interrupts disabled
*/ */
__raw_writel(0, avic_base + AVIC_INTCNTL); imx_writel(0, avic_base + AVIC_INTCNTL);
__raw_writel(0x1f, avic_base + AVIC_NIMASK); imx_writel(0x1f, avic_base + AVIC_NIMASK);
/* disable all interrupts */ /* disable all interrupts */
__raw_writel(0, avic_base + AVIC_INTENABLEH); imx_writel(0, avic_base + AVIC_INTENABLEH);
__raw_writel(0, avic_base + AVIC_INTENABLEL); imx_writel(0, avic_base + AVIC_INTENABLEL);
/* all IRQ no FIQ */ /* all IRQ no FIQ */
__raw_writel(0, avic_base + AVIC_INTTYPEH); imx_writel(0, avic_base + AVIC_INTTYPEH);
__raw_writel(0, avic_base + AVIC_INTTYPEL); imx_writel(0, avic_base + AVIC_INTTYPEL);
irq_base = irq_alloc_descs(-1, 0, AVIC_NUM_IRQS, numa_node_id()); irq_base = irq_alloc_descs(-1, 0, AVIC_NUM_IRQS, numa_node_id());
WARN_ON(irq_base < 0); WARN_ON(irq_base < 0);
@ -188,7 +188,7 @@ void __init mxc_init_irq(void __iomem *irqbase)
/* Set default priority value (0) for all IRQ's */ /* Set default priority value (0) for all IRQ's */
for (i = 0; i < 8; i++) for (i = 0; i < 8; i++)
__raw_writel(0, avic_base + AVIC_NIPRIORITY(i)); imx_writel(0, avic_base + AVIC_NIPRIORITY(i));
set_handle_irq(avic_handle_irq); set_handle_irq(avic_handle_irq);

1
arch/arm/mach-imx/common.h
View File

@ -66,6 +66,7 @@ void imx_gpc_check_dt(void);
void imx_gpc_set_arm_power_in_lpm(bool power_off); void imx_gpc_set_arm_power_in_lpm(bool power_off);
void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw); void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw);
void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw); void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw);
void imx25_pm_init(void);
enum mxc_cpu_pwr_mode { enum mxc_cpu_pwr_mode {
WAIT_CLOCKED, /* wfi only */ WAIT_CLOCKED, /* wfi only */

3
arch/arm/mach-imx/cpu-imx27.c
View File

@ -39,8 +39,7 @@ static int mx27_read_cpu_rev(void)
* the silicon revision very early we read it here to * the silicon revision very early we read it here to
* avoid any further hooks * avoid any further hooks
*/ */
val = __raw_readl(MX27_IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR val = imx_readl(MX27_IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR + SYS_CHIP_ID));
+ SYS_CHIP_ID));
mx27_cpu_partnumber = (int)((val >> 12) & 0xFFFF); mx27_cpu_partnumber = (int)((val >> 12) & 0xFFFF);

2
arch/arm/mach-imx/cpu-imx31.c
View File

@ -39,7 +39,7 @@ static int mx31_read_cpu_rev(void)
u32 i, srev; u32 i, srev;
/* read SREV register from IIM module */ /* read SREV register from IIM module */
srev = __raw_readl(MX31_IO_ADDRESS(MX31_IIM_BASE_ADDR + MXC_IIMSREV)); srev = imx_readl(MX31_IO_ADDRESS(MX31_IIM_BASE_ADDR + MXC_IIMSREV));
srev &= 0xff; srev &= 0xff;
for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++) for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)

2
arch/arm/mach-imx/cpu-imx35.c
View File

@ -20,7 +20,7 @@ static int mx35_read_cpu_rev(void)
{ {
u32 rev; u32 rev;
rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV)); rev = imx_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV));
switch (rev) { switch (rev) {
case 0x00: case 0x00:
return IMX_CHIP_REVISION_1_0; return IMX_CHIP_REVISION_1_0;

16
arch/arm/mach-imx/cpu.c
View File

@ -45,20 +45,20 @@ void __init imx_set_aips(void __iomem *base)
* Set all MPROTx to be non-bufferable, trusted for R/W, * Set all MPROTx to be non-bufferable, trusted for R/W,
* not forced to user-mode. * not forced to user-mode.
*/ */
__raw_writel(0x77777777, base + 0x0); imx_writel(0x77777777, base + 0x0);
__raw_writel(0x77777777, base + 0x4); imx_writel(0x77777777, base + 0x4);
/* /*
* Set all OPACRx to be non-bufferable, to not require * Set all OPACRx to be non-bufferable, to not require
* supervisor privilege level for access, allow for * supervisor privilege level for access, allow for
* write access and untrusted master access. * write access and untrusted master access.
*/ */
__raw_writel(0x0, base + 0x40); imx_writel(0x0, base + 0x40);
__raw_writel(0x0, base + 0x44); imx_writel(0x0, base + 0x44);
__raw_writel(0x0, base + 0x48); imx_writel(0x0, base + 0x48);
__raw_writel(0x0, base + 0x4C); imx_writel(0x0, base + 0x4C);
reg = __raw_readl(base + 0x50) & 0x00FFFFFF; reg = imx_readl(base + 0x50) & 0x00FFFFFF;
__raw_writel(reg, base + 0x50); imx_writel(reg, base + 0x50);
} }
void __init imx_aips_allow_unprivileged_access( void __init imx_aips_allow_unprivileged_access(

22
arch/arm/mach-imx/epit.c
View File

@ -64,23 +64,23 @@ static inline void epit_irq_disable(void)
{ {
u32 val; u32 val;
val = __raw_readl(timer_base + EPITCR); val = imx_readl(timer_base + EPITCR);
val &= ~EPITCR_OCIEN; val &= ~EPITCR_OCIEN;
__raw_writel(val, timer_base + EPITCR); imx_writel(val, timer_base + EPITCR);
} }
static inline void epit_irq_enable(void) static inline void epit_irq_enable(void)
{ {
u32 val; u32 val;
val = __raw_readl(timer_base + EPITCR); val = imx_readl(timer_base + EPITCR);
val |= EPITCR_OCIEN; val |= EPITCR_OCIEN;
__raw_writel(val, timer_base + EPITCR); imx_writel(val, timer_base + EPITCR);
} }
static void epit_irq_acknowledge(void) static void epit_irq_acknowledge(void)
{ {
__raw_writel(EPITSR_OCIF, timer_base + EPITSR); imx_writel(EPITSR_OCIF, timer_base + EPITSR);
} }
static int __init epit_clocksource_init(struct clk *timer_clk) static int __init epit_clocksource_init(struct clk *timer_clk)
@ -98,9 +98,9 @@ static int epit_set_next_event(unsigned long evt,
{ {
unsigned long tcmp; unsigned long tcmp;
tcmp = __raw_readl(timer_base + EPITCNR); tcmp = imx_readl(timer_base + EPITCNR);
__raw_writel(tcmp - evt, timer_base + EPITCMPR); imx_writel(tcmp - evt, timer_base + EPITCMPR);
return 0; return 0;
} }
@ -213,11 +213,11 @@ void __init epit_timer_init(void __iomem *base, int irq)
/* /*
* Initialise to a known state (all timers off, and timing reset) * Initialise to a known state (all timers off, and timing reset)
*/ */
__raw_writel(0x0, timer_base + EPITCR); imx_writel(0x0, timer_base + EPITCR);
__raw_writel(0xffffffff, timer_base + EPITLR); imx_writel(0xffffffff, timer_base + EPITLR);
__raw_writel(EPITCR_EN | EPITCR_CLKSRC_REF_HIGH | EPITCR_WAITEN, imx_writel(EPITCR_EN | EPITCR_CLKSRC_REF_HIGH | EPITCR_WAITEN,
timer_base + EPITCR); timer_base + EPITCR);
/* init and register the timer to the framework */ /* init and register the timer to the framework */
epit_clocksource_init(timer_clk); epit_clocksource_init(timer_clk);

2
arch/arm/mach-imx/headsmp.S
View File

@ -12,6 +12,7 @@
#include <linux/linkage.h> #include <linux/linkage.h>
#include <linux/init.h> #include <linux/init.h>
#include <asm/assembler.h>
diag_reg_offset: diag_reg_offset:
.word g_diag_reg - . .word g_diag_reg - .
@ -25,6 +26,7 @@ diag_reg_offset:
.endm .endm
ENTRY(v7_secondary_startup) ENTRY(v7_secondary_startup)
ARM_BE8(setend be) @ go BE8 if entered LE
set_diag_reg set_diag_reg
b secondary_startup b secondary_startup
ENDPROC(v7_secondary_startup) ENDPROC(v7_secondary_startup)

12
arch/arm/mach-imx/iomux-imx31.c
View File

@ -57,10 +57,10 @@ void mxc_iomux_mode(unsigned int pin_mode)
spin_lock(&gpio_mux_lock); spin_lock(&gpio_mux_lock);
l = __raw_readl(reg); l = imx_readl(reg);
l &= ~(0xff << (field * 8)); l &= ~(0xff << (field * 8));
l |= mode << (field * 8); l |= mode << (field * 8);
__raw_writel(l, reg); imx_writel(l, reg);
spin_unlock(&gpio_mux_lock); spin_unlock(&gpio_mux_lock);
} }
@ -82,10 +82,10 @@ void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
spin_lock(&gpio_mux_lock); spin_lock(&gpio_mux_lock);
l = __raw_readl(reg); l = imx_readl(reg);
l &= ~(0x1ff << (field * 10)); l &= ~(0x1ff << (field * 10));
l |= config << (field * 10); l |= config << (field * 10);
__raw_writel(l, reg); imx_writel(l, reg);
spin_unlock(&gpio_mux_lock); spin_unlock(&gpio_mux_lock);
} }
@ -163,12 +163,12 @@ void mxc_iomux_set_gpr(enum iomux_gp_func gp, bool en)
u32 l; u32 l;
spin_lock(&gpio_mux_lock); spin_lock(&gpio_mux_lock);
l = __raw_readl(IOMUXGPR); l = imx_readl(IOMUXGPR);
if (en) if (en)
l |= gp; l |= gp;
else else
l &= ~gp; l &= ~gp;
__raw_writel(l, IOMUXGPR); imx_writel(l, IOMUXGPR);
spin_unlock(&gpio_mux_lock); spin_unlock(&gpio_mux_lock);
} }

4
arch/arm/mach-imx/iomux-v1.c
View File

@ -38,12 +38,12 @@ static unsigned imx_iomuxv1_numports;
static inline unsigned long imx_iomuxv1_readl(unsigned offset) static inline unsigned long imx_iomuxv1_readl(unsigned offset)
{ {
return __raw_readl(imx_iomuxv1_baseaddr + offset); return imx_readl(imx_iomuxv1_baseaddr + offset);
} }
static inline void imx_iomuxv1_writel(unsigned long val, unsigned offset) static inline void imx_iomuxv1_writel(unsigned long val, unsigned offset)
{ {
__raw_writel(val, imx_iomuxv1_baseaddr + offset); imx_writel(val, imx_iomuxv1_baseaddr + offset);
} }
static inline void imx_iomuxv1_rmwl(unsigned offset, static inline void imx_iomuxv1_rmwl(unsigned offset,

6
arch/arm/mach-imx/iomux-v3.c
View File

@ -45,13 +45,13 @@ int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT; u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
if (mux_ctrl_ofs) if (mux_ctrl_ofs)
__raw_writel(mux_mode, base + mux_ctrl_ofs); imx_writel(mux_mode, base + mux_ctrl_ofs);
if (sel_input_ofs) if (sel_input_ofs)
__raw_writel(sel_input, base + sel_input_ofs); imx_writel(sel_input, base + sel_input_ofs);
if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs) if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
__raw_writel(pad_ctrl, base + pad_ctrl_ofs); imx_writel(pad_ctrl, base + pad_ctrl_ofs);
return 0; return 0;
} }

4
arch/arm/mach-imx/mach-armadillo5x0.c
View File

@ -525,8 +525,8 @@ static void __init armadillo5x0_init(void)
imx31_add_mxc_nand(&armadillo5x0_nand_board_info); imx31_add_mxc_nand(&armadillo5x0_nand_board_info);
/* set NAND page size to 2k if not configured via boot mode pins */ /* set NAND page size to 2k if not configured via boot mode pins */
__raw_writel(__raw_readl(mx3_ccm_base + MXC_CCM_RCSR) | imx_writel(imx_readl(mx3_ccm_base + MXC_CCM_RCSR) | (1 << 30),
(1 << 30), mx3_ccm_base + MXC_CCM_RCSR); mx3_ccm_base + MXC_CCM_RCSR);
/* RTC */ /* RTC */
/* Get RTC IRQ and register the chip */ /* Get RTC IRQ and register the chip */

1
arch/arm/mach-imx/mach-imx25.c
View File

@ -41,6 +41,7 @@ static const char * const imx25_dt_board_compat[] __initconst = {
DT_MACHINE_START(IMX25_DT, "Freescale i.MX25 (Device Tree Support)") DT_MACHINE_START(IMX25_DT, "Freescale i.MX25 (Device Tree Support)")
.init_early = imx25_init_early, .init_early = imx25_init_early,
.init_late = imx25_pm_init,
.init_irq = mx25_init_irq, .init_irq = mx25_init_irq,
.dt_compat = imx25_dt_board_compat, .dt_compat = imx25_dt_board_compat,
MACHINE_END MACHINE_END

5
arch/arm/mach-imx/mach-imx51.c
View File

@ -40,11 +40,10 @@ static void __init imx51_ipu_mipi_setup(void)
WARN_ON(!hsc_addr); WARN_ON(!hsc_addr);
/* setup MIPI module to legacy mode */ /* setup MIPI module to legacy mode */
__raw_writel(0xf00, hsc_addr); imx_writel(0xf00, hsc_addr);
/* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */ /* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */
__raw_writel(__raw_readl(hsc_addr + 0x800) | 0x30ff, imx_writel(imx_readl(hsc_addr + 0x800) | 0x30ff, hsc_addr + 0x800);
hsc_addr + 0x800);
iounmap(hsc_addr); iounmap(hsc_addr);
} }

8
arch/arm/mach-imx/mach-imx6q.c
View File

@ -266,8 +266,11 @@ static void __init imx6q_init_machine(void)
{ {
struct device *parent; struct device *parent;
imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q", if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
imx_get_soc_revision()); imx_print_silicon_rev("i.MX6QP", IMX_CHIP_REVISION_1_0);
else
imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
imx_get_soc_revision());
parent = imx_soc_device_init(); parent = imx_soc_device_init();
if (parent == NULL) if (parent == NULL)
@ -399,6 +402,7 @@ static void __init imx6q_init_irq(void)
static const char * const imx6q_dt_compat[] __initconst = { static const char * const imx6q_dt_compat[] __initconst = {
"fsl,imx6dl", "fsl,imx6dl",
"fsl,imx6q", "fsl,imx6q",
"fsl,imx6qp",
NULL, NULL,
}; };

6
arch/arm/mach-imx/mach-mx27ads.c
View File

@ -202,9 +202,9 @@ static struct i2c_board_info mx27ads_i2c_devices[] = {
static void vgpio_set(struct gpio_chip *chip, unsigned offset, int value) static void vgpio_set(struct gpio_chip *chip, unsigned offset, int value)
{ {
if (value) if (value)
__raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_SET_REG); imx_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_SET_REG);
else else
__raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_CLEAR_REG); imx_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_CLEAR_REG);
} }
static int vgpio_dir_out(struct gpio_chip *chip, unsigned offset, int value) static int vgpio_dir_out(struct gpio_chip *chip, unsigned offset, int value)
@ -364,7 +364,7 @@ static void __init mx27ads_timer_init(void)
{ {
unsigned long fref = 26000000; unsigned long fref = 26000000;
if ((__raw_readw(PBC_VERSION_REG) & CKIH_27MHZ_BIT_SET) == 0) if ((imx_readw(PBC_VERSION_REG) & CKIH_27MHZ_BIT_SET) == 0)
fref = 27000000; fref = 27000000;
mx27_clocks_init(fref); mx27_clocks_init(fref);

16
arch/arm/mach-imx/mach-mx31ads.c
View File

@ -160,8 +160,8 @@ static void mx31ads_expio_irq_handler(struct irq_desc *desc)
u32 int_valid; u32 int_valid;
u32 expio_irq; u32 expio_irq;
imr_val = __raw_readw(PBC_INTMASK_SET_REG); imr_val = imx_readw(PBC_INTMASK_SET_REG);
int_valid = __raw_readw(PBC_INTSTATUS_REG) & imr_val; int_valid = imx_readw(PBC_INTSTATUS_REG) & imr_val;
expio_irq = 0; expio_irq = 0;
for (; int_valid != 0; int_valid >>= 1, expio_irq++) { for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
@ -180,8 +180,8 @@ static void expio_mask_irq(struct irq_data *d)
{ {
u32 expio = d->hwirq; u32 expio = d->hwirq;
/* mask the interrupt */ /* mask the interrupt */
__raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG); imx_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
__raw_readw(PBC_INTMASK_CLEAR_REG); imx_readw(PBC_INTMASK_CLEAR_REG);
} }
/* /*
@ -192,7 +192,7 @@ static void expio_ack_irq(struct irq_data *d)
{ {
u32 expio = d->hwirq; u32 expio = d->hwirq;
/* clear the interrupt status */ /* clear the interrupt status */
__raw_writew(1 << expio, PBC_INTSTATUS_REG); imx_writew(1 << expio, PBC_INTSTATUS_REG);
} }
/* /*
@ -203,7 +203,7 @@ static void expio_unmask_irq(struct irq_data *d)
{ {
u32 expio = d->hwirq; u32 expio = d->hwirq;
/* unmask the interrupt */ /* unmask the interrupt */
__raw_writew(1 << expio, PBC_INTMASK_SET_REG); imx_writew(1 << expio, PBC_INTMASK_SET_REG);
} }
static struct irq_chip expio_irq_chip = { static struct irq_chip expio_irq_chip = {
@ -226,8 +226,8 @@ static void __init mx31ads_init_expio(void)
mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio"); mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio");
/* disable the interrupt and clear the status */ /* disable the interrupt and clear the status */
__raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG); imx_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
__raw_writew(0xFFFF, PBC_INTSTATUS_REG); imx_writew(0xFFFF, PBC_INTSTATUS_REG);
irq_base = irq_alloc_descs(-1, 0, MXC_MAX_EXP_IO_LINES, numa_node_id()); irq_base = irq_alloc_descs(-1, 0, MXC_MAX_EXP_IO_LINES, numa_node_id());
WARN_ON(irq_base < 0); WARN_ON(irq_base < 0);

2
arch/arm/mach-imx/mach-mx31moboard.c
View File

@ -509,7 +509,7 @@ static void mx31moboard_poweroff(void)
mxc_iomux_mode(MX31_PIN_WATCHDOG_RST__WATCHDOG_RST); mxc_iomux_mode(MX31_PIN_WATCHDOG_RST__WATCHDOG_RST);
__raw_writew(1 << 6 | 1 << 2, MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR)); imx_writew(1 << 6 | 1 << 2, MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
} }
static int mx31moboard_baseboard; static int mx31moboard_baseboard;

6
arch/arm/mach-imx/mach-qong.c
View File

@ -190,9 +190,9 @@ static struct platform_device qong_nand_device = {
static void __init qong_init_nand_mtd(void) static void __init qong_init_nand_mtd(void)
{ {
/* init CS */ /* init CS */
__raw_writel(0x00004f00, MX31_IO_ADDRESS(MX31_WEIM_CSCRxU(3))); imx_writel(0x00004f00, MX31_IO_ADDRESS(MX31_WEIM_CSCRxU(3)));
__raw_writel(0x20013b31, MX31_IO_ADDRESS(MX31_WEIM_CSCRxL(3))); imx_writel(0x20013b31, MX31_IO_ADDRESS(MX31_WEIM_CSCRxL(3)));
__raw_writel(0x00020800, MX31_IO_ADDRESS(MX31_WEIM_CSCRxA(3))); imx_writel(0x00020800, MX31_IO_ADDRESS(MX31_WEIM_CSCRxA(3)));
mxc_iomux_set_gpr(MUX_SDCTL_CSD1_SEL, true); mxc_iomux_set_gpr(MUX_SDCTL_CSD1_SEL, true);

5
arch/arm/mach-imx/mxc.h
View File

@ -193,4 +193,9 @@ extern struct cpu_op *(*get_cpu_op)(int *op);
#define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35()) #define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35())
#define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27()) #define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27())
#define imx_readl readl_relaxed
#define imx_readw readw_relaxed
#define imx_writel writel_relaxed
#define imx_writew writew_relaxed
#endif /* __ASM_ARCH_MXC_H__ */ #endif /* __ASM_ARCH_MXC_H__ */

37
arch/arm/mach-imx/pm-imx25.c Normal file
View File

@ -0,0 +1,37 @@
/*
* Copyright 2016 NXP Semiconductors
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/suspend.h>
#include <linux/io.h>
static int imx25_suspend_enter(suspend_state_t state)
{
if (!IS_ENABLED(CONFIG_PM))
return 0;
switch (state) {
case PM_SUSPEND_MEM:
cpu_do_idle();
break;
default:
return -EINVAL;
}
return 0;
}
static const struct platform_suspend_ops imx25_suspend_ops = {
.enter = imx25_suspend_enter,
.valid = suspend_valid_only_mem,
};
void __init imx25_pm_init(void)
{
suspend_set_ops(&imx25_suspend_ops);
}

4
arch/arm/mach-imx/pm-imx27.c
View File

@ -19,9 +19,9 @@ static int mx27_suspend_enter(suspend_state_t state)
switch (state) { switch (state) {
case PM_SUSPEND_MEM: case PM_SUSPEND_MEM:
/* Clear MPEN and SPEN to disable MPLL/SPLL */ /* Clear MPEN and SPEN to disable MPLL/SPLL */
cscr = __raw_readl(MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR)); cscr = imx_readl(MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR));
cscr &= 0xFFFFFFFC; cscr &= 0xFFFFFFFC;
__raw_writel(cscr, MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR)); imx_writel(cscr, MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR));
/* Executes WFI */ /* Executes WFI */
cpu_do_idle(); cpu_do_idle();
break; break;

4
arch/arm/mach-imx/pm-imx3.c
View File

@ -22,14 +22,14 @@
*/ */
void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode) void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode)
{ {
int reg = __raw_readl(mx3_ccm_base + MXC_CCM_CCMR); int reg = imx_readl(mx3_ccm_base + MXC_CCM_CCMR);
reg &= ~MXC_CCM_CCMR_LPM_MASK; reg &= ~MXC_CCM_CCMR_LPM_MASK;
switch (mode) { switch (mode) {
case MX3_WAIT: case MX3_WAIT:
if (cpu_is_mx35()) if (cpu_is_mx35())
reg |= MXC_CCM_CCMR_LPM_WAIT_MX35; reg |= MXC_CCM_CCMR_LPM_WAIT_MX35;
__raw_writel(reg, mx3_ccm_base + MXC_CCM_CCMR); imx_writel(reg, mx3_ccm_base + MXC_CCM_CCMR);
break; break;
default: default:
pr_err("Unknown cpu power mode: %d\n", mode); pr_err("Unknown cpu power mode: %d\n", mode);

26
arch/arm/mach-imx/pm-imx5.c
View File

@ -153,15 +153,15 @@ static void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
int stop_mode = 0; int stop_mode = 0;
/* always allow platform to issue a deep sleep mode request */ /* always allow platform to issue a deep sleep mode request */
plat_lpc = __raw_readl(cortex_base + MXC_CORTEXA8_PLAT_LPC) & plat_lpc = imx_readl(cortex_base + MXC_CORTEXA8_PLAT_LPC) &
~(MXC_CORTEXA8_PLAT_LPC_DSM); ~(MXC_CORTEXA8_PLAT_LPC_DSM);
ccm_clpcr = __raw_readl(ccm_base + MXC_CCM_CLPCR) & ccm_clpcr = imx_readl(ccm_base + MXC_CCM_CLPCR) &
~(MXC_CCM_CLPCR_LPM_MASK); ~(MXC_CCM_CLPCR_LPM_MASK);
arm_srpgcr = __raw_readl(gpc_base + MXC_SRPG_ARM_SRPGCR) & arm_srpgcr = imx_readl(gpc_base + MXC_SRPG_ARM_SRPGCR) &
~(MXC_SRPGCR_PCR); ~(MXC_SRPGCR_PCR);
empgc0 = __raw_readl(gpc_base + MXC_SRPG_EMPGC0_SRPGCR) & empgc0 = imx_readl(gpc_base + MXC_SRPG_EMPGC0_SRPGCR) &
~(MXC_SRPGCR_PCR); ~(MXC_SRPGCR_PCR);
empgc1 = __raw_readl(gpc_base + MXC_SRPG_EMPGC1_SRPGCR) & empgc1 = imx_readl(gpc_base + MXC_SRPG_EMPGC1_SRPGCR) &
~(MXC_SRPGCR_PCR); ~(MXC_SRPGCR_PCR);
switch (mode) { switch (mode) {
@ -196,17 +196,17 @@ static void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
return; return;
} }
__raw_writel(plat_lpc, cortex_base + MXC_CORTEXA8_PLAT_LPC); imx_writel(plat_lpc, cortex_base + MXC_CORTEXA8_PLAT_LPC);
__raw_writel(ccm_clpcr, ccm_base + MXC_CCM_CLPCR); imx_writel(ccm_clpcr, ccm_base + MXC_CCM_CLPCR);
__raw_writel(arm_srpgcr, gpc_base + MXC_SRPG_ARM_SRPGCR); imx_writel(arm_srpgcr, gpc_base + MXC_SRPG_ARM_SRPGCR);
__raw_writel(arm_srpgcr, gpc_base + MXC_SRPG_NEON_SRPGCR); imx_writel(arm_srpgcr, gpc_base + MXC_SRPG_NEON_SRPGCR);
if (stop_mode) { if (stop_mode) {
empgc0 |= MXC_SRPGCR_PCR; empgc0 |= MXC_SRPGCR_PCR;
empgc1 |= MXC_SRPGCR_PCR; empgc1 |= MXC_SRPGCR_PCR;
__raw_writel(empgc0, gpc_base + MXC_SRPG_EMPGC0_SRPGCR); imx_writel(empgc0, gpc_base + MXC_SRPG_EMPGC0_SRPGCR);
__raw_writel(empgc1, gpc_base + MXC_SRPG_EMPGC1_SRPGCR); imx_writel(empgc1, gpc_base + MXC_SRPG_EMPGC1_SRPGCR);
} }
} }
@ -228,8 +228,8 @@ static int mx5_suspend_enter(suspend_state_t state)
flush_cache_all(); flush_cache_all();
/*clear the EMPGC0/1 bits */ /*clear the EMPGC0/1 bits */
__raw_writel(0, gpc_base + MXC_SRPG_EMPGC0_SRPGCR); imx_writel(0, gpc_base + MXC_SRPG_EMPGC0_SRPGCR);
__raw_writel(0, gpc_base + MXC_SRPG_EMPGC1_SRPGCR); imx_writel(0, gpc_base + MXC_SRPG_EMPGC1_SRPGCR);
if (imx5_suspend_in_ocram_fn) if (imx5_suspend_in_ocram_fn)
imx5_suspend_in_ocram_fn(suspend_ocram_base); imx5_suspend_in_ocram_fn(suspend_ocram_base);

8
arch/arm/mach-imx/pm-imx6.c
View File

@ -561,13 +561,13 @@ static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata)
goto put_node; goto put_node;
pl310_cache_map_failed: pl310_cache_map_failed:
iounmap(&pm_info->gpc_base.vbase); iounmap(pm_info->gpc_base.vbase);
gpc_map_failed: gpc_map_failed:
iounmap(&pm_info->iomuxc_base.vbase); iounmap(pm_info->iomuxc_base.vbase);
iomuxc_map_failed: iomuxc_map_failed:
iounmap(&pm_info->src_base.vbase); iounmap(pm_info->src_base.vbase);
src_map_failed: src_map_failed:
iounmap(&pm_info->mmdc_base.vbase); iounmap(pm_info->mmdc_base.vbase);
put_node: put_node:
of_node_put(node); of_node_put(node);

2
arch/arm/mach-imx/src.c
View File

@ -73,7 +73,7 @@ static int imx_src_reset_module(struct reset_controller_dev *rcdev,
return 0; return 0;
} }
static struct reset_control_ops imx_src_ops = { static const struct reset_control_ops imx_src_ops = {
.reset = imx_src_reset_module, .reset = imx_src_reset_module,
}; };

10
arch/arm/mach-imx/system.c
View File

@ -54,7 +54,7 @@ void mxc_restart(enum reboot_mode mode, const char *cmd)
wcr_enable = (1 << 2); wcr_enable = (1 << 2);
/* Assert SRS signal */ /* Assert SRS signal */
__raw_writew(wcr_enable, wdog_base); imx_writew(wcr_enable, wdog_base);
/* /*
* Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
* written twice), we add another two writes to ensure there must be at * written twice), we add another two writes to ensure there must be at
@ -62,8 +62,8 @@ void mxc_restart(enum reboot_mode mode, const char *cmd)
* the target check here, since the writes shouldn't be a huge burden * the target check here, since the writes shouldn't be a huge burden
* for other platforms. * for other platforms.
*/ */
__raw_writew(wcr_enable, wdog_base); imx_writew(wcr_enable, wdog_base);
__raw_writew(wcr_enable, wdog_base); imx_writew(wcr_enable, wdog_base);
/* wait for reset to assert... */ /* wait for reset to assert... */
mdelay(500); mdelay(500);
@ -106,6 +106,9 @@ void __init imx_init_l2cache(void)
goto out; goto out;
} }
if (readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)
goto skip_if_enabled;
/* Configure the L2 PREFETCH and POWER registers */ /* Configure the L2 PREFETCH and POWER registers */
val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL); val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL);
val |= 0x70800000; val |= 0x70800000;
@ -122,6 +125,7 @@ void __init imx_init_l2cache(void)
val &= ~(1 << 30 | 1 << 23); val &= ~(1 << 30 | 1 << 23);
writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL); writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL);
skip_if_enabled:
iounmap(l2x0_base); iounmap(l2x0_base);
of_node_put(np); of_node_put(np);

34
arch/arm/mach-imx/tzic.c
View File

@ -65,10 +65,10 @@ static int tzic_set_irq_fiq(unsigned int irq, unsigned int type)
return -EINVAL; return -EINVAL;
mask = 1U << (irq & 0x1F); mask = 1U << (irq & 0x1F);
value = __raw_readl(tzic_base + TZIC_INTSEC0(index)) | mask; value = imx_readl(tzic_base + TZIC_INTSEC0(index)) | mask;
if (type) if (type)
value &= ~mask; value &= ~mask;
__raw_writel(value, tzic_base + TZIC_INTSEC0(index)); imx_writel(value, tzic_base + TZIC_INTSEC0(index));
return 0; return 0;
} }
@ -82,15 +82,15 @@ static void tzic_irq_suspend(struct irq_data *d)
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
int idx = d->hwirq >> 5; int idx = d->hwirq >> 5;
__raw_writel(gc->wake_active, tzic_base + TZIC_WAKEUP0(idx)); imx_writel(gc->wake_active, tzic_base + TZIC_WAKEUP0(idx));
} }
static void tzic_irq_resume(struct irq_data *d) static void tzic_irq_resume(struct irq_data *d)
{ {
int idx = d->hwirq >> 5; int idx = d->hwirq >> 5;
__raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(idx)), imx_writel(imx_readl(tzic_base + TZIC_ENSET0(idx)),
tzic_base + TZIC_WAKEUP0(idx)); tzic_base + TZIC_WAKEUP0(idx));
} }
#else #else
@ -135,8 +135,8 @@ static void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs)
handled = 0; handled = 0;
for (i = 0; i < 4; i++) { for (i = 0; i < 4; i++) {
stat = __raw_readl(tzic_base + TZIC_HIPND(i)) & stat = imx_readl(tzic_base + TZIC_HIPND(i)) &
__raw_readl(tzic_base + TZIC_INTSEC0(i)); imx_readl(tzic_base + TZIC_INTSEC0(i));
while (stat) { while (stat) {
handled = 1; handled = 1;
@ -166,18 +166,18 @@ void __init tzic_init_irq(void)
/* put the TZIC into the reset value with /* put the TZIC into the reset value with
* all interrupts disabled * all interrupts disabled
*/ */
i = __raw_readl(tzic_base + TZIC_INTCNTL); i = imx_readl(tzic_base + TZIC_INTCNTL);
__raw_writel(0x80010001, tzic_base + TZIC_INTCNTL); imx_writel(0x80010001, tzic_base + TZIC_INTCNTL);
__raw_writel(0x1f, tzic_base + TZIC_PRIOMASK); imx_writel(0x1f, tzic_base + TZIC_PRIOMASK);
__raw_writel(0x02, tzic_base + TZIC_SYNCCTRL); imx_writel(0x02, tzic_base + TZIC_SYNCCTRL);
for (i = 0; i < 4; i++) for (i = 0; i < 4; i++)
__raw_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i)); imx_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i));
/* disable all interrupts */ /* disable all interrupts */
for (i = 0; i < 4; i++) for (i = 0; i < 4; i++)
__raw_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i)); imx_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i));
/* all IRQ no FIQ Warning :: No selection */ /* all IRQ no FIQ Warning :: No selection */
@ -214,13 +214,13 @@ int tzic_enable_wake(void)
{ {
unsigned int i; unsigned int i;
__raw_writel(1, tzic_base + TZIC_DSMINT); imx_writel(1, tzic_base + TZIC_DSMINT);
if (unlikely(__raw_readl(tzic_base + TZIC_DSMINT) == 0)) if (unlikely(imx_readl(tzic_base + TZIC_DSMINT) == 0))
return -EAGAIN; return -EAGAIN;
for (i = 0; i < 4; i++) for (i = 0; i < 4; i++)
__raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(i)), imx_writel(imx_readl(tzic_base + TZIC_ENSET0(i)),
tzic_base + TZIC_WAKEUP0(i)); tzic_base + TZIC_WAKEUP0(i));
return 0; return 0;
} }