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can: flexcan: rename feature into quirks

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This patch renames the "features" member of struct flexcan_devtype_data to
"quirks". The corresponding defines are renamed too, to reflect what they
actually do.

    FLEXCAN_HAS_V10_FEATURES      -> FLEXCAN_QUIRK_DISABLE_RXFG
    FLEXCAN_HAS_BROKEN_ERR_STATE  -> FLEXCAN_QUIRK_BROKEN_ERR_STATE
    FLEXCAN_HAS_MECR_FEATURES     -> FLEXCAN_QUIRK_DISABLE_MECR

Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
This commit is contained in:
Marc Kleine-Budde 2015-05-08 15:22:36 +02:00
parent 749de6fce2
commit f377bff023
1 changed files with 10 additions and 10 deletions
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20
drivers/net/can/flexcan.c
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@ -187,9 +187,9 @@
* *
* Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected. * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
*/ */
#define FLEXCAN_HAS_V10_FEATURES BIT(1) /* For core version >= 10 */ #define FLEXCAN_QUIRK_BROKEN_ERR_STATE BIT(1) /* [TR]WRN_INT not connected */
#define FLEXCAN_HAS_BROKEN_ERR_STATE BIT(2) /* [TR]WRN_INT not connected */ #define FLEXCAN_QUIRK_DISABLE_RXFG BIT(2) /* Disable RX FIFO Global mask */
#define FLEXCAN_HAS_MECR_FEATURES BIT(3) /* Memory error detection */ #define FLEXCAN_QUIRK_DISABLE_MECR BIT(3) /* Disble Memory error detection */
/* Structure of the message buffer */ /* Structure of the message buffer */
struct flexcan_mb { struct flexcan_mb {
@ -244,7 +244,7 @@ struct flexcan_regs {
}; };
struct flexcan_devtype_data { struct flexcan_devtype_data {
u32 features; /* hardware controller features */ u32 quirks; /* quirks needed for different IP cores */
}; };
struct flexcan_priv { struct flexcan_priv {
@ -263,17 +263,17 @@ struct flexcan_priv {
}; };
static struct flexcan_devtype_data fsl_p1010_devtype_data = { static struct flexcan_devtype_data fsl_p1010_devtype_data = {
.features = FLEXCAN_HAS_BROKEN_ERR_STATE, .quirks = FLEXCAN_QUIRK_BROKEN_ERR_STATE,
}; };
static struct flexcan_devtype_data fsl_imx28_devtype_data; static struct flexcan_devtype_data fsl_imx28_devtype_data;
static struct flexcan_devtype_data fsl_imx6q_devtype_data = { static struct flexcan_devtype_data fsl_imx6q_devtype_data = {
.features = FLEXCAN_HAS_V10_FEATURES, .quirks = FLEXCAN_QUIRK_DISABLE_RXFG,
}; };
static struct flexcan_devtype_data fsl_vf610_devtype_data = { static struct flexcan_devtype_data fsl_vf610_devtype_data = {
.features = FLEXCAN_HAS_V10_FEATURES | FLEXCAN_HAS_MECR_FEATURES, .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_DISABLE_MECR,
}; };
static const struct can_bittiming_const flexcan_bittiming_const = { static const struct can_bittiming_const flexcan_bittiming_const = {
@ -870,7 +870,7 @@ static int flexcan_chip_start(struct net_device *dev)
* on most Flexcan cores, too. Otherwise we don't get * on most Flexcan cores, too. Otherwise we don't get
* any error warning or passive interrupts. * any error warning or passive interrupts.
*/ */
if (priv->devtype_data->features & FLEXCAN_HAS_BROKEN_ERR_STATE || if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_ERR_STATE ||
priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
reg_ctrl |= FLEXCAN_CTRL_ERR_MSK; reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
else else
@ -900,7 +900,7 @@ static int flexcan_chip_start(struct net_device *dev)
flexcan_write(0x0, &regs->rx14mask); flexcan_write(0x0, &regs->rx14mask);
flexcan_write(0x0, &regs->rx15mask); flexcan_write(0x0, &regs->rx15mask);
if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES) if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
flexcan_write(0x0, &regs->rxfgmask); flexcan_write(0x0, &regs->rxfgmask);
/* On Vybrid, disable memory error detection interrupts /* On Vybrid, disable memory error detection interrupts
@ -909,7 +909,7 @@ static int flexcan_chip_start(struct net_device *dev)
* false positive memory errors and put the device in * false positive memory errors and put the device in
* freeze mode. * freeze mode.
*/ */
if (priv->devtype_data->features & FLEXCAN_HAS_MECR_FEATURES) { if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
/* Follow the protocol as described in "Detection /* Follow the protocol as described in "Detection
* and Correction of Memory Errors" to write to * and Correction of Memory Errors" to write to
* MECR register * MECR register