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m68knommu: move ColdFire PIT timer base addresses

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The PIT hardware timer module used in some ColdFire CPU's is not always
addressed relative to an IPSBAR register. Parts like the ColdFire 5207 and
5208 have fixed peripheral addresses. So lets not define the register
addresses of the PIT relative to an IPSBAR definition. Move the base
address definitions into the per-part headers. This is a lot more consistent
since all the other peripheral base addresses are defined in the per-part
header files already.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
This commit is contained in:
Greg Ungerer 2011-03-05 23:32:35 +10:00
parent cdfc243e7d
commit f317c71a2f
6 changed files with 32 additions and 20 deletions
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6
arch/m68k/include/asm/m520xsim.h
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@ -133,6 +133,12 @@
#define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02) #define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02)
#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04) #define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04)
/*
* PIT timer module.
*/
#define MCFPIT_BASE1 0xFC080000 /* Base address of TIMER1 */
#define MCFPIT_BASE2 0xFC084000 /* Base address of TIMER2 */
/* /*
* UART module. * UART module.
*/ */

9
arch/m68k/include/asm/m523xsim.h
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@ -118,10 +118,17 @@
#define MCFGPIO_PCLRR_TIMER (MCF_IPSBAR + 0x10003B) #define MCFGPIO_PCLRR_TIMER (MCF_IPSBAR + 0x10003B)
#define MCFGPIO_PCLRR_ETPU (MCF_IPSBAR + 0x10003C) #define MCFGPIO_PCLRR_ETPU (MCF_IPSBAR + 0x10003C)
/*
* PIT timer base addresses.
*/
#define MCFPIT_BASE1 (MCF_IPSBAR + 0x150000)
#define MCFPIT_BASE2 (MCF_IPSBAR + 0x160000)
#define MCFPIT_BASE3 (MCF_IPSBAR + 0x170000)
#define MCFPIT_BASE4 (MCF_IPSBAR + 0x180000)
/* /*
* EPort * EPort
*/ */
#define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002) #define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002)
#define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004) #define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004)
#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005) #define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005)

11
arch/m68k/include/asm/m527xsim.h
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@ -231,16 +231,21 @@
#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10007E) #define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10007E)
#endif #endif
/*
* PIT timer base addresses.
*/
#define MCFPIT_BASE1 (MCF_IPSBAR + 0x150000)
#define MCFPIT_BASE2 (MCF_IPSBAR + 0x160000)
#define MCFPIT_BASE3 (MCF_IPSBAR + 0x170000)
#define MCFPIT_BASE4 (MCF_IPSBAR + 0x180000)
/* /*
* EPort * EPort
*/ */
#define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002) #define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002)
#define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004) #define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004)
#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005) #define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005)
/* /*
* GPIO pins setups to enable the UARTs. * GPIO pins setups to enable the UARTs.
*/ */

8
arch/m68k/include/asm/m528xsim.h
View File

@ -163,6 +163,14 @@
#define MCFGPIO_PTDPAR (MCF_IPSBAR + 0x0010005B) #define MCFGPIO_PTDPAR (MCF_IPSBAR + 0x0010005B)
#define MCFGPIO_PUAPAR (MCF_IPSBAR + 0x0010005C) #define MCFGPIO_PUAPAR (MCF_IPSBAR + 0x0010005C)
/*
* PIT timer base addresses.
*/
#define MCFPIT_BASE1 (MCF_IPSBAR + 0x00150000)
#define MCFPIT_BASE2 (MCF_IPSBAR + 0x00160000)
#define MCFPIT_BASE3 (MCF_IPSBAR + 0x00170000)
#define MCFPIT_BASE4 (MCF_IPSBAR + 0x00180000)
/* /*
* Edge Port registers * Edge Port registers
*/ */

16
arch/m68k/include/asm/mcfpit.h
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@ -11,22 +11,8 @@
#define mcfpit_h #define mcfpit_h
/****************************************************************************/ /****************************************************************************/
/* /*
* Get address specific defines for the 5270/5271, 5280/5282, and 5208. * Define the PIT timer register address offsets.
*/
#if defined(CONFIG_M520x)
#define MCFPIT_BASE1 0x00080000 /* Base address of TIMER1 */
#define MCFPIT_BASE2 0x00084000 /* Base address of TIMER2 */
#else
#define MCFPIT_BASE1 0x00150000 /* Base address of TIMER1 */
#define MCFPIT_BASE2 0x00160000 /* Base address of TIMER2 */
#define MCFPIT_BASE3 0x00170000 /* Base address of TIMER3 */
#define MCFPIT_BASE4 0x00180000 /* Base address of TIMER4 */
#endif
/*
* Define the PIT timer register set addresses.
*/ */
#define MCFPIT_PCSR 0x0 /* PIT control register */ #define MCFPIT_PCSR 0x0 /* PIT control register */
#define MCFPIT_PMR 0x2 /* PIT modulus register */ #define MCFPIT_PMR 0x2 /* PIT modulus register */

2
arch/m68knommu/platform/coldfire/pit.c
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@ -31,7 +31,7 @@
* By default use timer1 as the system clock timer. * By default use timer1 as the system clock timer.
*/ */
#define FREQ ((MCF_CLK / 2) / 64) #define FREQ ((MCF_CLK / 2) / 64)
#define TA(a) (MCF_IPSBAR + MCFPIT_BASE1 + (a)) #define TA(a) (MCFPIT_BASE1 + (a))
#define PIT_CYCLES_PER_JIFFY (FREQ / HZ) #define PIT_CYCLES_PER_JIFFY (FREQ / HZ)
static u32 pit_cnt; static u32 pit_cnt;