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bnx2x: fix hw attention handling

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Use register name to initialize attention mask

Signed-off-by: Dmitry Kravkov <dmitry@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Dmitry Kravkov 2011-09-22 02:33:31 +00:00 committed by David S. Miller
parent e451e61b56
commit f2eaeb58bf
2 changed files with 16 additions and 2 deletions
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6
drivers/net/bnx2x/bnx2x_main.c
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@ -4943,7 +4943,7 @@ static void bnx2x_init_def_sb(struct bnx2x *bp)
int igu_seg_id; int igu_seg_id;
int port = BP_PORT(bp); int port = BP_PORT(bp);
int func = BP_FUNC(bp); int func = BP_FUNC(bp);
int reg_offset; int reg_offset, reg_offset_en5;
u64 section; u64 section;
int index; int index;
struct hc_sp_status_block_data sp_sb_data; struct hc_sp_status_block_data sp_sb_data;
@ -4966,6 +4966,8 @@ static void bnx2x_init_def_sb(struct bnx2x *bp)
reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
int sindex; int sindex;
/* take care of sig[0]..sig[4] */ /* take care of sig[0]..sig[4] */
@ -4980,7 +4982,7 @@ static void bnx2x_init_def_sb(struct bnx2x *bp)
* and not 16 between the different groups * and not 16 between the different groups
*/ */
bp->attn_group[index].sig[4] = REG_RD(bp, bp->attn_group[index].sig[4] = REG_RD(bp,
reg_offset + 0x10 + 0x4*index); reg_offset_en5 + 0x4*index);
else else
bp->attn_group[index].sig[4] = 0; bp->attn_group[index].sig[4] = 0;
} }

12
drivers/net/bnx2x/bnx2x_reg.h
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@ -1384,6 +1384,18 @@
Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
#define MISC_REG_AEU_ENABLE4_PXP_0 0xa108 #define MISC_REG_AEU_ENABLE4_PXP_0 0xa108
#define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8 #define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8
/* [RW 32] fifth 32b for enabling the output for function 0 output0. Mapped
* as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
* attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
* mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1
* parity; [31-10] Reserved; */
#define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0 0xa688
/* [RW 32] Fifth 32b for enabling the output for function 1 output0. Mapped
* as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
* attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
* mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1
* parity; [31-10] Reserved; */
#define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 0xa6b0
/* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu /* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu
128 bit vector */ 128 bit vector */
#define MISC_REG_AEU_GENERAL_ATTN_0 0xa000 #define MISC_REG_AEU_GENERAL_ATTN_0 0xa000