forked from Minki/linux
ARM: mach-shmobile: clock-sh7372: Add FSIDIV clock support
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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03ff858c09
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f2ace4a5d7
@ -50,6 +50,9 @@
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#define SMSTPCR3 0xe615013c
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#define SMSTPCR3 0xe615013c
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#define SMSTPCR4 0xe6150140
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#define SMSTPCR4 0xe6150140
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#define FSIDIVA 0xFE1F8000
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#define FSIDIVB 0xFE1F8008
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/* Platforms must set frequency on their DV_CLKI pin */
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/* Platforms must set frequency on their DV_CLKI pin */
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struct clk sh7372_dv_clki_clk = {
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struct clk sh7372_dv_clki_clk = {
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};
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};
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@ -417,6 +420,101 @@ static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
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fsibckcr_parent, ARRAY_SIZE(fsibckcr_parent), 6, 2),
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fsibckcr_parent, ARRAY_SIZE(fsibckcr_parent), 6, 2),
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};
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};
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/* FSI DIV */
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static unsigned long fsidiv_recalc(struct clk *clk)
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{
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unsigned long value;
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value = __raw_readl(clk->mapping->base);
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if ((value & 0x3) != 0x3)
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return 0;
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value >>= 16;
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if (value < 2)
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return 0;
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return clk->parent->rate / value;
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}
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static long fsidiv_round_rate(struct clk *clk, unsigned long rate)
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{
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return clk_rate_div_range_round(clk, 2, 0xffff, rate);
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}
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static void fsidiv_disable(struct clk *clk)
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{
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__raw_writel(0, clk->mapping->base);
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}
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static int fsidiv_enable(struct clk *clk)
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{
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unsigned long value;
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value = __raw_readl(clk->mapping->base) >> 16;
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if (value < 2) {
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fsidiv_disable(clk);
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return -ENOENT;
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}
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__raw_writel((value << 16) | 0x3, clk->mapping->base);
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return 0;
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}
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static int fsidiv_set_rate(struct clk *clk,
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unsigned long rate, int algo_id)
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{
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int idx;
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if (clk->parent->rate == rate) {
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fsidiv_disable(clk);
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return 0;
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}
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idx = (clk->parent->rate / rate) & 0xffff;
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if (idx < 2)
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return -ENOENT;
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__raw_writel(idx << 16, clk->mapping->base);
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return fsidiv_enable(clk);
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}
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static struct clk_ops fsidiv_clk_ops = {
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.recalc = fsidiv_recalc,
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.round_rate = fsidiv_round_rate,
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.set_rate = fsidiv_set_rate,
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.enable = fsidiv_enable,
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.disable = fsidiv_disable,
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};
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static struct clk_mapping sh7372_fsidiva_clk_mapping = {
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.phys = FSIDIVA,
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.len = 8,
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};
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struct clk sh7372_fsidiva_clk = {
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.ops = &fsidiv_clk_ops,
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.parent = &div6_reparent_clks[DIV6_FSIA], /* late install */
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.mapping = &sh7372_fsidiva_clk_mapping,
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};
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static struct clk_mapping sh7372_fsidivb_clk_mapping = {
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.phys = FSIDIVB,
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.len = 8,
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};
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struct clk sh7372_fsidivb_clk = {
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.ops = &fsidiv_clk_ops,
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.parent = &div6_reparent_clks[DIV6_FSIB], /* late install */
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.mapping = &sh7372_fsidivb_clk_mapping,
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};
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static struct clk *late_main_clks[] = {
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&sh7372_fsidiva_clk,
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&sh7372_fsidivb_clk,
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};
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enum { MSTP001,
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enum { MSTP001,
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MSTP131, MSTP130,
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MSTP131, MSTP130,
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MSTP129, MSTP128, MSTP127, MSTP126, MSTP125,
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MSTP129, MSTP128, MSTP127, MSTP126, MSTP125,
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@ -585,6 +683,9 @@ void __init sh7372_clock_init(void)
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if (!ret)
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if (!ret)
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ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
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ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
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for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
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ret = clk_register(late_main_clks[k]);
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clkdev_add_table(lookups, ARRAY_SIZE(lookups));
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clkdev_add_table(lookups, ARRAY_SIZE(lookups));
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if (!ret)
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if (!ret)
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@ -464,5 +464,7 @@ extern struct clk sh7372_dv_clki_div2_clk;
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extern struct clk sh7372_pllc2_clk;
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extern struct clk sh7372_pllc2_clk;
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extern struct clk sh7372_fsiack_clk;
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extern struct clk sh7372_fsiack_clk;
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extern struct clk sh7372_fsibck_clk;
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extern struct clk sh7372_fsibck_clk;
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extern struct clk sh7372_fsidiva_clk;
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extern struct clk sh7372_fsidivb_clk;
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#endif /* __ASM_SH7372_H__ */
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#endif /* __ASM_SH7372_H__ */
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