forked from Minki/linux
LoongArch: Add CPU definition headers
Add common headers (CPU definition and address space layout) for basic LoongArch support. Reviewed-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
This commit is contained in:
Huacai Chen
parent
fa96b57c14
commit
f2ac457a61
112
arch/loongarch/include/asm/addrspace.h
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112
arch/loongarch/include/asm/addrspace.h
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@ -0,0 +1,112 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*
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* Derived from MIPS:
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* Copyright (C) 1996, 99 Ralf Baechle
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* Copyright (C) 2000, 2002 Maciej W. Rozycki
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* Copyright (C) 1990, 1999 by Silicon Graphics, Inc.
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*/
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#ifndef _ASM_ADDRSPACE_H
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#define _ASM_ADDRSPACE_H
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#include <linux/const.h>
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#include <asm/loongarch.h>
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/*
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* This gives the physical RAM offset.
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*/
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#ifndef __ASSEMBLY__
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#ifndef PHYS_OFFSET
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#define PHYS_OFFSET _AC(0, UL)
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#endif
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extern unsigned long vm_map_base;
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#endif /* __ASSEMBLY__ */
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#ifndef IO_BASE
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#define IO_BASE CSR_DMW0_BASE
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#endif
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#ifndef CACHE_BASE
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#define CACHE_BASE CSR_DMW1_BASE
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#endif
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#ifndef UNCACHE_BASE
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#define UNCACHE_BASE CSR_DMW0_BASE
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#endif
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#define DMW_PABITS 48
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#define TO_PHYS_MASK ((1ULL << DMW_PABITS) - 1)
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/*
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* Memory above this physical address will be considered highmem.
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*/
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#ifndef HIGHMEM_START
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#define HIGHMEM_START (_AC(1, UL) << _AC(DMW_PABITS, UL))
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#endif
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#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK))
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#define TO_CACHE(x) (CACHE_BASE | ((x) & TO_PHYS_MASK))
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#define TO_UNCACHE(x) (UNCACHE_BASE | ((x) & TO_PHYS_MASK))
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/*
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* This handles the memory map.
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*/
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#ifndef PAGE_OFFSET
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#define PAGE_OFFSET (CACHE_BASE + PHYS_OFFSET)
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#endif
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#ifndef FIXADDR_TOP
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#define FIXADDR_TOP ((unsigned long)(long)(int)0xfffe0000)
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#endif
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#ifdef __ASSEMBLY__
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#define _ATYPE_
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#define _ATYPE32_
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#define _ATYPE64_
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#define _CONST64_(x) x
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#else
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#define _ATYPE_ __PTRDIFF_TYPE__
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#define _ATYPE32_ int
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#define _ATYPE64_ __s64
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#ifdef CONFIG_64BIT
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#define _CONST64_(x) x ## L
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#else
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#define _CONST64_(x) x ## LL
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#endif
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#endif
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/*
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* 32/64-bit LoongArch address spaces
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*/
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#ifdef __ASSEMBLY__
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#define _ACAST32_
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#define _ACAST64_
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#else
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#define _ACAST32_ (_ATYPE_)(_ATYPE32_) /* widen if necessary */
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#define _ACAST64_ (_ATYPE64_) /* do _not_ narrow */
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#endif
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#ifdef CONFIG_32BIT
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#define UVRANGE 0x00000000
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#define KPRANGE0 0x80000000
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#define KPRANGE1 0xa0000000
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#define KVRANGE 0xc0000000
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#else
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#define XUVRANGE _CONST64_(0x0000000000000000)
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#define XSPRANGE _CONST64_(0x4000000000000000)
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#define XKPRANGE _CONST64_(0x8000000000000000)
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#define XKVRANGE _CONST64_(0xc000000000000000)
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#endif
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/*
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* Returns the physical address of a KPRANGEx / XKPRANGE address
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*/
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#define PHYSADDR(a) ((_ACAST64_(a)) & TO_PHYS_MASK)
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#endif /* _ASM_ADDRSPACE_H */
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73
arch/loongarch/include/asm/cpu-features.h
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73
arch/loongarch/include/asm/cpu-features.h
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*
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* Derived from MIPS:
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* Copyright (C) 2003, 2004 Ralf Baechle
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* Copyright (C) 2004 Maciej W. Rozycki
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*/
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#ifndef __ASM_CPU_FEATURES_H
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#define __ASM_CPU_FEATURES_H
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#include <asm/cpu.h>
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#include <asm/cpu-info.h>
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#define cpu_opt(opt) (cpu_data[0].options & (opt))
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#define cpu_has(feat) (cpu_data[0].options & BIT_ULL(feat))
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#define cpu_has_loongarch (cpu_has_loongarch32 | cpu_has_loongarch64)
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#define cpu_has_loongarch32 (cpu_data[0].isa_level & LOONGARCH_CPU_ISA_32BIT)
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#define cpu_has_loongarch64 (cpu_data[0].isa_level & LOONGARCH_CPU_ISA_64BIT)
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#define cpu_icache_line_size() cpu_data[0].icache.linesz
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#define cpu_dcache_line_size() cpu_data[0].dcache.linesz
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#define cpu_vcache_line_size() cpu_data[0].vcache.linesz
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#define cpu_scache_line_size() cpu_data[0].scache.linesz
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#ifdef CONFIG_32BIT
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# define cpu_has_64bits (cpu_data[0].isa_level & LOONGARCH_CPU_ISA_64BIT)
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# define cpu_vabits 31
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# define cpu_pabits 31
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#endif
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#ifdef CONFIG_64BIT
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# define cpu_has_64bits 1
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# define cpu_vabits cpu_data[0].vabits
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# define cpu_pabits cpu_data[0].pabits
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# define __NEED_ADDRBITS_PROBE
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#endif
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/*
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* SMP assumption: Options of CPU 0 are a superset of all processors.
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* This is true for all known LoongArch systems.
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*/
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#define cpu_has_cpucfg cpu_opt(LOONGARCH_CPU_CPUCFG)
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#define cpu_has_lam cpu_opt(LOONGARCH_CPU_LAM)
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#define cpu_has_ual cpu_opt(LOONGARCH_CPU_UAL)
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#define cpu_has_fpu cpu_opt(LOONGARCH_CPU_FPU)
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#define cpu_has_lsx cpu_opt(LOONGARCH_CPU_LSX)
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#define cpu_has_lasx cpu_opt(LOONGARCH_CPU_LASX)
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#define cpu_has_complex cpu_opt(LOONGARCH_CPU_COMPLEX)
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#define cpu_has_crypto cpu_opt(LOONGARCH_CPU_CRYPTO)
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#define cpu_has_lvz cpu_opt(LOONGARCH_CPU_LVZ)
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#define cpu_has_lbt_x86 cpu_opt(LOONGARCH_CPU_LBT_X86)
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#define cpu_has_lbt_arm cpu_opt(LOONGARCH_CPU_LBT_ARM)
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#define cpu_has_lbt_mips cpu_opt(LOONGARCH_CPU_LBT_MIPS)
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#define cpu_has_lbt (cpu_has_lbt_x86|cpu_has_lbt_arm|cpu_has_lbt_mips)
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#define cpu_has_csr cpu_opt(LOONGARCH_CPU_CSR)
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#define cpu_has_tlb cpu_opt(LOONGARCH_CPU_TLB)
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#define cpu_has_watch cpu_opt(LOONGARCH_CPU_WATCH)
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#define cpu_has_vint cpu_opt(LOONGARCH_CPU_VINT)
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#define cpu_has_csripi cpu_opt(LOONGARCH_CPU_CSRIPI)
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#define cpu_has_extioi cpu_opt(LOONGARCH_CPU_EXTIOI)
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#define cpu_has_prefetch cpu_opt(LOONGARCH_CPU_PREFETCH)
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#define cpu_has_pmp cpu_opt(LOONGARCH_CPU_PMP)
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#define cpu_has_perf cpu_opt(LOONGARCH_CPU_PMP)
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#define cpu_has_scalefreq cpu_opt(LOONGARCH_CPU_SCALEFREQ)
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#define cpu_has_flatmode cpu_opt(LOONGARCH_CPU_FLATMODE)
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#define cpu_has_eiodecode cpu_opt(LOONGARCH_CPU_EIODECODE)
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#define cpu_has_guestid cpu_opt(LOONGARCH_CPU_GUESTID)
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#define cpu_has_hypervisor cpu_opt(LOONGARCH_CPU_HYPERVISOR)
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#endif /* __ASM_CPU_FEATURES_H */
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116
arch/loongarch/include/asm/cpu-info.h
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arch/loongarch/include/asm/cpu-info.h
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@ -0,0 +1,116 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#ifndef __ASM_CPU_INFO_H
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#define __ASM_CPU_INFO_H
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#include <linux/cache.h>
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#include <linux/types.h>
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#include <asm/loongarch.h>
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/*
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* Descriptor for a cache
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*/
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struct cache_desc {
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unsigned int waysize; /* Bytes per way */
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unsigned short sets; /* Number of lines per set */
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unsigned char ways; /* Number of ways */
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unsigned char linesz; /* Size of line in bytes */
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unsigned char waybit; /* Bits to select in a cache set */
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unsigned char flags; /* Flags describing cache properties */
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};
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struct cpuinfo_loongarch {
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u64 asid_cache;
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unsigned long asid_mask;
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/*
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* Capability and feature descriptor structure for LoongArch CPU
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*/
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unsigned long long options;
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unsigned int processor_id;
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unsigned int fpu_vers;
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unsigned int fpu_csr0;
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unsigned int fpu_mask;
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unsigned int cputype;
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int isa_level;
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int tlbsize;
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int tlbsizemtlb;
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int tlbsizestlbsets;
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int tlbsizestlbways;
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struct cache_desc icache; /* Primary I-cache */
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struct cache_desc dcache; /* Primary D or combined I/D cache */
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struct cache_desc vcache; /* Victim cache, between pcache and scache */
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struct cache_desc scache; /* Secondary cache */
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struct cache_desc tcache; /* Tertiary/split secondary cache */
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int core; /* physical core number in package */
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int package;/* physical package number */
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int vabits; /* Virtual Address size in bits */
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int pabits; /* Physical Address size in bits */
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unsigned int ksave_mask; /* Usable KSave mask. */
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unsigned int watch_dreg_count; /* Number data breakpoints */
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unsigned int watch_ireg_count; /* Number instruction breakpoints */
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unsigned int watch_reg_use_cnt; /* min(NUM_WATCH_REGS, watch_dreg_count + watch_ireg_count), Usable by ptrace */
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} __aligned(SMP_CACHE_BYTES);
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extern struct cpuinfo_loongarch cpu_data[];
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#define boot_cpu_data cpu_data[0]
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#define current_cpu_data cpu_data[smp_processor_id()]
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#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
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extern void cpu_probe(void);
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extern const char *__cpu_family[];
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extern const char *__cpu_full_name[];
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#define cpu_family_string() __cpu_family[raw_smp_processor_id()]
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#define cpu_full_name_string() __cpu_full_name[raw_smp_processor_id()]
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struct seq_file;
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struct notifier_block;
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extern int register_proc_cpuinfo_notifier(struct notifier_block *nb);
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extern int proc_cpuinfo_notifier_call_chain(unsigned long val, void *v);
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#define proc_cpuinfo_notifier(fn, pri) \
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({ \
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static struct notifier_block fn##_nb = { \
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.notifier_call = fn, \
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.priority = pri \
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}; \
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\
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register_proc_cpuinfo_notifier(&fn##_nb); \
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})
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struct proc_cpuinfo_notifier_args {
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struct seq_file *m;
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unsigned long n;
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};
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static inline bool cpus_are_siblings(int cpua, int cpub)
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{
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struct cpuinfo_loongarch *infoa = &cpu_data[cpua];
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struct cpuinfo_loongarch *infob = &cpu_data[cpub];
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if (infoa->package != infob->package)
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return false;
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if (infoa->core != infob->core)
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return false;
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return true;
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}
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static inline unsigned long cpu_asid_mask(struct cpuinfo_loongarch *cpuinfo)
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{
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return cpuinfo->asid_mask;
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}
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static inline void set_cpu_asid_mask(struct cpuinfo_loongarch *cpuinfo,
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unsigned long asid_mask)
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{
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cpuinfo->asid_mask = asid_mask;
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}
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#endif /* __ASM_CPU_INFO_H */
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127
arch/loongarch/include/asm/cpu.h
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127
arch/loongarch/include/asm/cpu.h
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@ -0,0 +1,127 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* cpu.h: Values of the PRID register used to match up
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* various LoongArch CPU types.
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*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#ifndef _ASM_CPU_H
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#define _ASM_CPU_H
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/*
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* As described in LoongArch specs from Loongson Technology, the PRID register
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* (CPUCFG.00) has the following layout:
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*
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* +---------------+----------------+------------+--------------------+
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* | Reserved | Company ID | Series ID | Product ID |
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* +---------------+----------------+------------+--------------------+
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* 31 24 23 16 15 12 11 0
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*/
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/*
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* Assigned Company values for bits 23:16 of the PRID register.
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*/
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#define PRID_COMP_MASK 0xff0000
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#define PRID_COMP_LOONGSON 0x140000
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/*
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* Assigned Series ID values for bits 15:12 of the PRID register. In order
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* to detect a certain CPU type exactly eventually additional registers may
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* need to be examined.
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*/
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#define PRID_SERIES_MASK 0xf000
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#define PRID_SERIES_LA132 0x8000 /* Loongson 32bit */
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#define PRID_SERIES_LA264 0xa000 /* Loongson 64bit, 2-issue */
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#define PRID_SERIES_LA364 0xb000 /* Loongson 64bit，3-issue */
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#define PRID_SERIES_LA464 0xc000 /* Loongson 64bit, 4-issue */
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#define PRID_SERIES_LA664 0xd000 /* Loongson 64bit, 6-issue */
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/*
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* Particular Product ID values for bits 11:0 of the PRID register.
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*/
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#define PRID_PRODUCT_MASK 0x0fff
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#if !defined(__ASSEMBLY__)
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enum cpu_type_enum {
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CPU_UNKNOWN,
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CPU_LOONGSON32,
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CPU_LOONGSON64,
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CPU_LAST
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};
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#endif /* !__ASSEMBLY */
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/*
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* ISA Level encodings
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*
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*/
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#define LOONGARCH_CPU_ISA_LA32R 0x00000001
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#define LOONGARCH_CPU_ISA_LA32S 0x00000002
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#define LOONGARCH_CPU_ISA_LA64 0x00000004
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#define LOONGARCH_CPU_ISA_32BIT (LOONGARCH_CPU_ISA_LA32R | LOONGARCH_CPU_ISA_LA32S)
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#define LOONGARCH_CPU_ISA_64BIT LOONGARCH_CPU_ISA_LA64
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/*
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* CPU Option encodings
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*/
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#define CPU_FEATURE_CPUCFG 0 /* CPU has CPUCFG */
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#define CPU_FEATURE_LAM 1 /* CPU has Atomic instructions */
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#define CPU_FEATURE_UAL 2 /* CPU supports unaligned access */
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#define CPU_FEATURE_FPU 3 /* CPU has FPU */
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#define CPU_FEATURE_LSX 4 /* CPU has LSX (128-bit SIMD) */
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#define CPU_FEATURE_LASX 5 /* CPU has LASX (256-bit SIMD) */
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#define CPU_FEATURE_COMPLEX 6 /* CPU has Complex instructions */
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#define CPU_FEATURE_CRYPTO 7 /* CPU has Crypto instructions */
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#define CPU_FEATURE_LVZ 8 /* CPU has Virtualization extension */
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#define CPU_FEATURE_LBT_X86 9 /* CPU has X86 Binary Translation */
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#define CPU_FEATURE_LBT_ARM 10 /* CPU has ARM Binary Translation */
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#define CPU_FEATURE_LBT_MIPS 11 /* CPU has MIPS Binary Translation */
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#define CPU_FEATURE_TLB 12 /* CPU has TLB */
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#define CPU_FEATURE_CSR 13 /* CPU has CSR */
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#define CPU_FEATURE_WATCH 14 /* CPU has watchpoint registers */
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#define CPU_FEATURE_VINT 15 /* CPU has vectored interrupts */
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#define CPU_FEATURE_CSRIPI 16 /* CPU has CSR-IPI */
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#define CPU_FEATURE_EXTIOI 17 /* CPU has EXT-IOI */
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#define CPU_FEATURE_PREFETCH 18 /* CPU has prefetch instructions */
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#define CPU_FEATURE_PMP 19 /* CPU has perfermance counter */
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#define CPU_FEATURE_SCALEFREQ 20 /* CPU supports cpufreq scaling */
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#define CPU_FEATURE_FLATMODE 21 /* CPU has flat mode */
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#define CPU_FEATURE_EIODECODE 22 /* CPU has EXTIOI interrupt pin decode mode */
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#define CPU_FEATURE_GUESTID 23 /* CPU has GuestID feature */
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#define CPU_FEATURE_HYPERVISOR 24 /* CPU has hypervisor (running in VM) */
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#define LOONGARCH_CPU_CPUCFG BIT_ULL(CPU_FEATURE_CPUCFG)
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#define LOONGARCH_CPU_LAM BIT_ULL(CPU_FEATURE_LAM)
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#define LOONGARCH_CPU_UAL BIT_ULL(CPU_FEATURE_UAL)
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#define LOONGARCH_CPU_FPU BIT_ULL(CPU_FEATURE_FPU)
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#define LOONGARCH_CPU_LSX BIT_ULL(CPU_FEATURE_LSX)
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#define LOONGARCH_CPU_LASX BIT_ULL(CPU_FEATURE_LASX)
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#define LOONGARCH_CPU_COMPLEX BIT_ULL(CPU_FEATURE_COMPLEX)
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#define LOONGARCH_CPU_CRYPTO BIT_ULL(CPU_FEATURE_CRYPTO)
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#define LOONGARCH_CPU_LVZ BIT_ULL(CPU_FEATURE_LVZ)
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#define LOONGARCH_CPU_LBT_X86 BIT_ULL(CPU_FEATURE_LBT_X86)
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#define LOONGARCH_CPU_LBT_ARM BIT_ULL(CPU_FEATURE_LBT_ARM)
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#define LOONGARCH_CPU_LBT_MIPS BIT_ULL(CPU_FEATURE_LBT_MIPS)
|
||||
#define LOONGARCH_CPU_TLB BIT_ULL(CPU_FEATURE_TLB)
|
||||
#define LOONGARCH_CPU_CSR BIT_ULL(CPU_FEATURE_CSR)
|
||||
#define LOONGARCH_CPU_WATCH BIT_ULL(CPU_FEATURE_WATCH)
|
||||
#define LOONGARCH_CPU_VINT BIT_ULL(CPU_FEATURE_VINT)
|
||||
#define LOONGARCH_CPU_CSRIPI BIT_ULL(CPU_FEATURE_CSRIPI)
|
||||
#define LOONGARCH_CPU_EXTIOI BIT_ULL(CPU_FEATURE_EXTIOI)
|
||||
#define LOONGARCH_CPU_PREFETCH BIT_ULL(CPU_FEATURE_PREFETCH)
|
||||
#define LOONGARCH_CPU_PMP BIT_ULL(CPU_FEATURE_PMP)
|
||||
#define LOONGARCH_CPU_SCALEFREQ BIT_ULL(CPU_FEATURE_SCALEFREQ)
|
||||
#define LOONGARCH_CPU_FLATMODE BIT_ULL(CPU_FEATURE_FLATMODE)
|
||||
#define LOONGARCH_CPU_EIODECODE BIT_ULL(CPU_FEATURE_EIODECODE)
|
||||
#define LOONGARCH_CPU_GUESTID BIT_ULL(CPU_FEATURE_GUESTID)
|
||||
#define LOONGARCH_CPU_HYPERVISOR BIT_ULL(CPU_FEATURE_HYPERVISOR)
|
||||
|
||||
#endif /* _ASM_CPU_H */
|
||||
53
arch/loongarch/include/asm/fpregdef.h
Normal file
53
arch/loongarch/include/asm/fpregdef.h
Normal file
@ -0,0 +1,53 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Definitions for the FPU register names
|
||||
*
|
||||
* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
|
||||
*/
|
||||
#ifndef _ASM_FPREGDEF_H
|
||||
#define _ASM_FPREGDEF_H
|
||||
|
||||
#define fa0 $f0 /* argument registers, fa0/fa1 reused as fv0/fv1 for return value */
|
||||
#define fa1 $f1
|
||||
#define fa2 $f2
|
||||
#define fa3 $f3
|
||||
#define fa4 $f4
|
||||
#define fa5 $f5
|
||||
#define fa6 $f6
|
||||
#define fa7 $f7
|
||||
#define ft0 $f8 /* caller saved */
|
||||
#define ft1 $f9
|
||||
#define ft2 $f10
|
||||
#define ft3 $f11
|
||||
#define ft4 $f12
|
||||
#define ft5 $f13
|
||||
#define ft6 $f14
|
||||
#define ft7 $f15
|
||||
#define ft8 $f16
|
||||
#define ft9 $f17
|
||||
#define ft10 $f18
|
||||
#define ft11 $f19
|
||||
#define ft12 $f20
|
||||
#define ft13 $f21
|
||||
#define ft14 $f22
|
||||
#define ft15 $f23
|
||||
#define fs0 $f24 /* callee saved */
|
||||
#define fs1 $f25
|
||||
#define fs2 $f26
|
||||
#define fs3 $f27
|
||||
#define fs4 $f28
|
||||
#define fs5 $f29
|
||||
#define fs6 $f30
|
||||
#define fs7 $f31
|
||||
|
||||
/*
|
||||
* Current binutils expects *GPRs* at FCSR position for the FCSR
|
||||
* operation instructions, so define aliases for those used.
|
||||
*/
|
||||
#define fcsr0 $r0
|
||||
#define fcsr1 $r1
|
||||
#define fcsr2 $r2
|
||||
#define fcsr3 $r3
|
||||
#define vcsr16 $r16
|
||||
|
||||
#endif /* _ASM_FPREGDEF_H */
|
||||
1516
arch/loongarch/include/asm/loongarch.h
Normal file
1516
arch/loongarch/include/asm/loongarch.h
Normal file
File diff suppressed because it is too large
Load Diff
153
arch/loongarch/include/asm/loongson.h
Normal file
153
arch/loongarch/include/asm/loongson.h
Normal file
@ -0,0 +1,153 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Author: Huacai Chen <chenhuacai@loongson.cn>
|
||||
* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
|
||||
*/
|
||||
|
||||
#ifndef __ASM_LOONGSON_H
|
||||
#define __ASM_LOONGSON_H
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/pci.h>
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/bootinfo.h>
|
||||
|
||||
extern const struct plat_smp_ops loongson3_smp_ops;
|
||||
|
||||
#define LOONGSON_REG(x) \
|
||||
(*(volatile u32 *)((char *)TO_UNCACHE(LOONGSON_REG_BASE) + (x)))
|
||||
|
||||
#define LOONGSON_LIO_BASE 0x18000000
|
||||
#define LOONGSON_LIO_SIZE 0x00100000 /* 1M */
|
||||
#define LOONGSON_LIO_TOP (LOONGSON_LIO_BASE+LOONGSON_LIO_SIZE-1)
|
||||
|
||||
#define LOONGSON_BOOT_BASE 0x1c000000
|
||||
#define LOONGSON_BOOT_SIZE 0x02000000 /* 32M */
|
||||
#define LOONGSON_BOOT_TOP (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1)
|
||||
|
||||
#define LOONGSON_REG_BASE 0x1fe00000
|
||||
#define LOONGSON_REG_SIZE 0x00100000 /* 1M */
|
||||
#define LOONGSON_REG_TOP (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1)
|
||||
|
||||
/* GPIO Regs - r/w */
|
||||
|
||||
#define LOONGSON_GPIODATA LOONGSON_REG(0x11c)
|
||||
#define LOONGSON_GPIOIE LOONGSON_REG(0x120)
|
||||
#define LOONGSON_REG_GPIO_BASE (LOONGSON_REG_BASE + 0x11c)
|
||||
|
||||
#define MAX_PACKAGES 16
|
||||
|
||||
/* Chip Config register of each physical cpu package */
|
||||
extern u64 loongson_chipcfg[MAX_PACKAGES];
|
||||
#define LOONGSON_CHIPCFG(id) (*(volatile u32 *)(loongson_chipcfg[id]))
|
||||
|
||||
/* Chip Temperature register of each physical cpu package */
|
||||
extern u64 loongson_chiptemp[MAX_PACKAGES];
|
||||
#define LOONGSON_CHIPTEMP(id) (*(volatile u32 *)(loongson_chiptemp[id]))
|
||||
|
||||
/* Freq Control register of each physical cpu package */
|
||||
extern u64 loongson_freqctrl[MAX_PACKAGES];
|
||||
#define LOONGSON_FREQCTRL(id) (*(volatile u32 *)(loongson_freqctrl[id]))
|
||||
|
||||
#define xconf_readl(addr) readl(addr)
|
||||
#define xconf_readq(addr) readq(addr)
|
||||
|
||||
static inline void xconf_writel(u32 val, volatile void __iomem *addr)
|
||||
{
|
||||
asm volatile (
|
||||
" st.w %[v], %[hw], 0 \n"
|
||||
" ld.b $r0, %[hw], 0 \n"
|
||||
:
|
||||
: [hw] "r" (addr), [v] "r" (val)
|
||||
);
|
||||
}
|
||||
|
||||
static inline void xconf_writeq(u64 val64, volatile void __iomem *addr)
|
||||
{
|
||||
asm volatile (
|
||||
" st.d %[v], %[hw], 0 \n"
|
||||
" ld.b $r0, %[hw], 0 \n"
|
||||
:
|
||||
: [hw] "r" (addr), [v] "r" (val64)
|
||||
);
|
||||
}
|
||||
|
||||
/* ============== LS7A registers =============== */
|
||||
#define LS7A_PCH_REG_BASE 0x10000000UL
|
||||
/* LPC regs */
|
||||
#define LS7A_LPC_REG_BASE (LS7A_PCH_REG_BASE + 0x00002000)
|
||||
/* CHIPCFG regs */
|
||||
#define LS7A_CHIPCFG_REG_BASE (LS7A_PCH_REG_BASE + 0x00010000)
|
||||
/* MISC reg base */
|
||||
#define LS7A_MISC_REG_BASE (LS7A_PCH_REG_BASE + 0x00080000)
|
||||
/* ACPI regs */
|
||||
#define LS7A_ACPI_REG_BASE (LS7A_MISC_REG_BASE + 0x00050000)
|
||||
/* RTC regs */
|
||||
#define LS7A_RTC_REG_BASE (LS7A_MISC_REG_BASE + 0x00050100)
|
||||
|
||||
#define LS7A_DMA_CFG (volatile void *)TO_UNCACHE(LS7A_CHIPCFG_REG_BASE + 0x041c)
|
||||
#define LS7A_DMA_NODE_SHF 8
|
||||
#define LS7A_DMA_NODE_MASK 0x1F00
|
||||
|
||||
#define LS7A_INT_MASK_REG (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x020)
|
||||
#define LS7A_INT_EDGE_REG (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x060)
|
||||
#define LS7A_INT_CLEAR_REG (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x080)
|
||||
#define LS7A_INT_HTMSI_EN_REG (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x040)
|
||||
#define LS7A_INT_ROUTE_ENTRY_REG (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x100)
|
||||
#define LS7A_INT_HTMSI_VEC_REG (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x200)
|
||||
#define LS7A_INT_STATUS_REG (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x3a0)
|
||||
#define LS7A_INT_POL_REG (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x3e0)
|
||||
#define LS7A_LPC_INT_CTL (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x2000)
|
||||
#define LS7A_LPC_INT_ENA (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x2004)
|
||||
#define LS7A_LPC_INT_STS (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x2008)
|
||||
#define LS7A_LPC_INT_CLR (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x200c)
|
||||
#define LS7A_LPC_INT_POL (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x2010)
|
||||
|
||||
#define LS7A_PMCON_SOC_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x000)
|
||||
#define LS7A_PMCON_RESUME_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x004)
|
||||
#define LS7A_PMCON_RTC_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x008)
|
||||
#define LS7A_PM1_EVT_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x00c)
|
||||
#define LS7A_PM1_ENA_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x010)
|
||||
#define LS7A_PM1_CNT_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x014)
|
||||
#define LS7A_PM1_TMR_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x018)
|
||||
#define LS7A_P_CNT_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x01c)
|
||||
#define LS7A_GPE0_STS_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x028)
|
||||
#define LS7A_GPE0_ENA_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x02c)
|
||||
#define LS7A_RST_CNT_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x030)
|
||||
#define LS7A_WD_SET_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x034)
|
||||
#define LS7A_WD_TIMER_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x038)
|
||||
#define LS7A_THSENS_CNT_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x04c)
|
||||
#define LS7A_GEN_RTC_1_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x050)
|
||||
#define LS7A_GEN_RTC_2_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x054)
|
||||
#define LS7A_DPM_CFG_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x400)
|
||||
#define LS7A_DPM_STS_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x404)
|
||||
#define LS7A_DPM_CNT_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x408)
|
||||
|
||||
typedef enum {
|
||||
ACPI_PCI_HOTPLUG_STATUS = 1 << 1,
|
||||
ACPI_CPU_HOTPLUG_STATUS = 1 << 2,
|
||||
ACPI_MEM_HOTPLUG_STATUS = 1 << 3,
|
||||
ACPI_POWERBUTTON_STATUS = 1 << 8,
|
||||
ACPI_RTC_WAKE_STATUS = 1 << 10,
|
||||
ACPI_PCI_WAKE_STATUS = 1 << 14,
|
||||
ACPI_ANY_WAKE_STATUS = 1 << 15,
|
||||
} AcpiEventStatusBits;
|
||||
|
||||
#define HT1LO_OFFSET 0xe0000000000UL
|
||||
|
||||
/* PCI Configuration Space Base */
|
||||
#define MCFG_EXT_PCICFG_BASE 0xefe00000000UL
|
||||
|
||||
/* REG ACCESS*/
|
||||
#define ls7a_readb(addr) (*(volatile unsigned char *)TO_UNCACHE(addr))
|
||||
#define ls7a_readw(addr) (*(volatile unsigned short *)TO_UNCACHE(addr))
|
||||
#define ls7a_readl(addr) (*(volatile unsigned int *)TO_UNCACHE(addr))
|
||||
#define ls7a_readq(addr) (*(volatile unsigned long *)TO_UNCACHE(addr))
|
||||
#define ls7a_writeb(val, addr) *(volatile unsigned char *)TO_UNCACHE(addr) = (val)
|
||||
#define ls7a_writew(val, addr) *(volatile unsigned short *)TO_UNCACHE(addr) = (val)
|
||||
#define ls7a_writel(val, addr) *(volatile unsigned int *)TO_UNCACHE(addr) = (val)
|
||||
#define ls7a_writeq(val, addr) *(volatile unsigned long *)TO_UNCACHE(addr) = (val)
|
||||
|
||||
#endif /* __ASM_LOONGSON_H */
|
||||
41
arch/loongarch/include/asm/regdef.h
Normal file
41
arch/loongarch/include/asm/regdef.h
Normal file
@ -0,0 +1,41 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
|
||||
*/
|
||||
#ifndef _ASM_REGDEF_H
|
||||
#define _ASM_REGDEF_H
|
||||
|
||||
#define zero $r0 /* wired zero */
|
||||
#define ra $r1 /* return address */
|
||||
#define tp $r2
|
||||
#define sp $r3 /* stack pointer */
|
||||
#define a0 $r4 /* argument registers, a0/a1 reused as v0/v1 for return value */
|
||||
#define a1 $r5
|
||||
#define a2 $r6
|
||||
#define a3 $r7
|
||||
#define a4 $r8
|
||||
#define a5 $r9
|
||||
#define a6 $r10
|
||||
#define a7 $r11
|
||||
#define t0 $r12 /* caller saved */
|
||||
#define t1 $r13
|
||||
#define t2 $r14
|
||||
#define t3 $r15
|
||||
#define t4 $r16
|
||||
#define t5 $r17
|
||||
#define t6 $r18
|
||||
#define t7 $r19
|
||||
#define t8 $r20
|
||||
#define u0 $r21
|
||||
#define fp $r22 /* frame pointer */
|
||||
#define s0 $r23 /* callee saved */
|
||||
#define s1 $r24
|
||||
#define s2 $r25
|
||||
#define s3 $r26
|
||||
#define s4 $r27
|
||||
#define s5 $r28
|
||||
#define s6 $r29
|
||||
#define s7 $r30
|
||||
#define s8 $r31
|
||||
|
||||
#endif /* _ASM_REGDEF_H */
|
||||
Loading…
Reference in New Issue
Block a user