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Berlin DT changes for v3.19 (round 1)

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- AHCI and SATA PHY nodes for BG2Q
 - Reset controller binding docs
 - Ethernet nodes for BG2, BG2CD
 - SDHCI nodes for BG2, BG2CD
 - Corresponding board changes to enable AHCI, Ethernet, SDHCI
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Merge tag 'berlin-dt-3.19-1' of git://git.infradead.org/users/hesselba/linux-berlin into next/dt

Merge "ARM: berlin: DT changes for v3.19 (round 1)" from Sebastian Hesselbarth:

"This is Berlin DT changes for v3.19 and contains those patches that missed
the v3.18 merge window plus corresponding patches to catch-up with Antoine's
BG2Q improvements for BG2 and BG2CD. We now have working SDHCI and Ethernet
on all SoCs (well, BG2CD has HDMI HEC only), SATA PHY support for BG2 is still
pending."

Berlin DT changes for v3.19 (round 1)
- AHCI and SATA PHY nodes for BG2Q
- Reset controller binding docs
- Ethernet nodes for BG2, BG2CD
- SDHCI nodes for BG2, BG2CD
- Corresponding board changes to enable AHCI, Ethernet, SDHCI

* tag 'berlin-dt-3.19-1' of git://git.infradead.org/users/hesselba/linux-berlin:
  ARM: dts: berlin: Enable eMMC on Sony NSZ-GS7
  ARM: dts: berlin: Enable WiFi on Google Chromecast
  ARM: dts: berlin: Add SDHCI controller nodes to BG2/BG2CD
  ARM: dts: berlin: Enable ethernet on Sony NSZ-GS7
  ARM: dts: berlin: Add phy-connection-type to BG2Q Ethernet
  ARM: dts: berlin: Add BG2CD ethernet DT nodes
  ARM: dts: berlin: Add BG2 ethernet DT nodes
  ARM: dts: berlin: Add GPIO leds to Google Chromecast
  ARM: dts: berlin: enable timer 1 for sched_clock
  ARM: dts: berlin: add a required reset property in the chip controller node
  Documentation: bindings: add reset bindings docs for Marvell Berlin SoCs
  ARM: dts: berlin: enable the eSATA interface on the BG2Q DMP
  ARM: dts: berlin: add the AHCI node for the BG2Q

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2014-11-08 16:47:37 -08:00
commit f26e294535
7 changed files with 211 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
Documentation/devicetree/bindings/arm/marvell,berlin.txt
View File

@ -106,11 +106,21 @@ Required subnode-properties:
- groups: a list of strings describing the group names.
- function: a string describing the function used to mux the groups.
* Reset controller binding
A reset controller is part of the chip control registers set. The chip control
node also provides the reset. The register set is not at the same offset between
Berlin SoCs.
Required property:
- #reset-cells: must be set to 2
Example:
chip: chip-control@ea0000 {
compatible = "marvell,berlin2-chip-ctrl";
#clock-cells = <1>;
#reset-cells = <2>;
reg = <0xea0000 0x400>;
clocks = <&refclk>, <&externaldev 0>;
clock-names = "refclk", "video_ext0";

9
arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
View File

@ -26,4 +26,13 @@
};
};
&eth1 { status = "okay"; };
/* Samsung M8G2FA 8GB eMMC */
&sdhci2 {
non-removable;
bus-width = <8>;
status = "okay";
};
&uart0 { status = "okay"; };

71
arch/arm/boot/dts/berlin2.dtsi
View File

@ -53,6 +53,35 @@
ranges = <0 0xf7000000 0x1000000>;
sdhci0: sdhci@ab0000 {
compatible = "mrvl,pxav3-mmc";
reg = <0xab0000 0x200>;
clocks = <&chip CLKID_SDIO0XIN>, <&chip CLKID_SDIO0>;
clock-names = "io", "core";
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sdhci1: sdhci@ab0800 {
compatible = "mrvl,pxav3-mmc";
reg = <0xab0800 0x200>;
clocks = <&chip CLKID_SDIO1XIN>, <&chip CLKID_SDIO1>;
clock-names = "io", "core";
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sdhci2: sdhci@ab1000 {
compatible = "mrvl,pxav3-mmc";
reg = <0xab1000 0x200>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&chip CLKID_NFC_ECC>, <&chip CLKID_NFC>;
clock-names = "io", "core";
pinctrl-0 = <&emmc_pmux>;
pinctrl-names = "default";
status = "disabled";
};
l2: l2-cache-controller@ac0000 {
compatible = "marvell,tauros3-cache", "arm,pl310-cache";
reg = <0xac0000 0x1000>;
@ -79,11 +108,47 @@
clocks = <&chip CLKID_TWD>;
};
eth1: ethernet@b90000 {
compatible = "marvell,pxa168-eth";
reg = <0xb90000 0x10000>;
clocks = <&chip CLKID_GETH1>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
/* set by bootloader */
local-mac-address = [00 00 00 00 00 00];
#address-cells = <1>;
#size-cells = <0>;
phy-connection-type = "mii";
phy-handle = <&ethphy1>;
status = "disabled";
ethphy1: ethernet-phy@0 {
reg = <0>;
};
};
cpu-ctrl@dd0000 {
compatible = "marvell,berlin-cpu-ctrl";
reg = <0xdd0000 0x10000>;
};
eth0: ethernet@e50000 {
compatible = "marvell,pxa168-eth";
reg = <0xe50000 0x10000>;
clocks = <&chip CLKID_GETH0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
/* set by bootloader */
local-mac-address = [00 00 00 00 00 00];
#address-cells = <1>;
#size-cells = <0>;
phy-connection-type = "mii";
phy-handle = <&ethphy0>;
status = "disabled";
ethphy0: ethernet-phy@0 {
reg = <0>;
};
};
apb@e80000 {
compatible = "simple-bus";
#address-cells = <1>;
@ -249,9 +314,15 @@
chip: chip-control@ea0000 {
compatible = "marvell,berlin2-chip-ctrl";
#clock-cells = <1>;
#reset-cells = <2>;
reg = <0xea0000 0x400>;
clocks = <&refclk>;
clock-names = "refclk";
emmc_pmux: emmc-pmux {
groups = "G26";
function = "emmc";
};
};
apb@fc0000 {

26
arch/arm/boot/dts/berlin2cd-google-chromecast.dts
View File

@ -11,6 +11,7 @@
/dts-v1/;
#include "berlin2cd.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Google Chromecast";
@ -24,6 +25,31 @@
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MB */
};
leds {
compatible = "gpio-leds";
white {
label = "white";
gpios = <&portc 1 GPIO_ACTIVE_HIGH>;
default-state = "keep";
};
red {
label = "red";
gpios = <&portc 2 GPIO_ACTIVE_HIGH>;
default-state = "keep";
};
};
};
/*
* AzureWave AW-NH387 (Marvell 88W8787)
* 802.11b/g/n + Bluetooth 2.1
*/
&sdhci0 {
non-removable;
status = "okay";
};
&uart0 { status = "okay"; };

46
arch/arm/boot/dts/berlin2cd.dtsi
View File

@ -45,6 +45,15 @@
ranges = <0 0xf7000000 0x1000000>;
sdhci0: sdhci@ab0000 {
compatible = "mrvl,pxav3-mmc";
reg = <0xab0000 0x200>;
clocks = <&chip CLKID_SDIO0XIN>, <&chip CLKID_SDIO0>;
clock-names = "io", "core";
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
l2: l2-cache-controller@ac0000 {
compatible = "arm,pl310-cache";
reg = <0xac0000 0x1000>;
@ -66,6 +75,42 @@
clocks = <&chip CLKID_TWD>;
};
eth1: ethernet@b90000 {
compatible = "marvell,pxa168-eth";
reg = <0xb90000 0x10000>;
clocks = <&chip CLKID_GETH1>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
/* set by bootloader */
local-mac-address = [00 00 00 00 00 00];
#address-cells = <1>;
#size-cells = <0>;
phy-connection-type = "mii";
phy-handle = <&ethphy1>;
status = "disabled";
ethphy1: ethernet-phy@0 {
reg = <0>;
};
};
eth0: ethernet@e50000 {
compatible = "marvell,pxa168-eth";
reg = <0xe50000 0x10000>;
clocks = <&chip CLKID_GETH0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
/* set by bootloader */
local-mac-address = [00 00 00 00 00 00];
#address-cells = <1>;
#size-cells = <0>;
phy-connection-type = "mii";
phy-handle = <&ethphy0>;
status = "disabled";
ethphy0: ethernet-phy@0 {
reg = <0>;
};
};
apb@e80000 {
compatible = "simple-bus";
#address-cells = <1>;
@ -231,6 +276,7 @@
chip: chip-control@ea0000 {
compatible = "marvell,berlin2cd-chip-ctrl";
#clock-cells = <1>;
#reset-cells = <2>;
reg = <0xea0000 0x400>;
clocks = <&refclk>;
clock-names = "refclk";

8
arch/arm/boot/dts/berlin2q-marvell-dmp.dts
View File

@ -49,3 +49,11 @@
&eth0 {
status = "okay";
};
&sata0 {
status = "okay";
};
&sata_phy {
status = "okay";
};

42
arch/arm/boot/dts/berlin2q.dtsi
View File

@ -123,6 +123,7 @@
local-mac-address = [00 00 00 00 00 00];
#address-cells = <1>;
#size-cells = <0>;
phy-connection-type = "mii";
phy-handle = <&ethphy0>;
status = "disabled";
@ -255,7 +256,6 @@
reg = <0x2c14 0x14>;
clocks = <&chip CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
timer2: timer@2c28 {
@ -349,6 +349,7 @@
chip: chip-control@ea0000 {
compatible = "marvell,berlin2q-chip-ctrl";
#clock-cells = <1>;
#reset-cells = <2>;
reg = <0xea0000 0x400>, <0xdd0170 0x10>;
clocks = <&refclk>;
clock-names = "refclk";
@ -364,6 +365,45 @@
};
};
ahci: sata@e90000 {
compatible = "marvell,berlin2q-ahci", "generic-ahci";
reg = <0xe90000 0x1000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&chip CLKID_SATA>;
#address-cells = <1>;
#size-cells = <0>;
sata0: sata-port@0 {
reg = <0>;
phys = <&sata_phy 0>;
status = "disabled";
};
sata1: sata-port@1 {
reg = <1>;
phys = <&sata_phy 1>;
status = "disabled";
};
};
sata_phy: phy@e900a0 {
compatible = "marvell,berlin2q-sata-phy";
reg = <0xe900a0 0x200>;
clocks = <&chip CLKID_SATA>;
#address-cells = <1>;
#size-cells = <0>;
#phy-cells = <1>;
status = "disabled";
sata-phy@0 {
reg = <0>;
};
sata-phy@1 {
reg = <1>;
};
};
apb@fc0000 {
compatible = "simple-bus";
#address-cells = <1>;