forked from Minki/linux
Merge tag 'r8169-upstream-20061204-00' of git://electric-eye.fr.zoreil.com/home/romieu/linux-2.6 into upstream
This commit is contained in:
Jeff Garzik
commit
f1ff0fdc35
@ -225,6 +225,7 @@ MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
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static int rx_copybreak = 200;
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static int use_dac;
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static int ignore_parity_err;
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static struct {
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u32 msg_enable;
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} debug = { -1 };
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@ -470,6 +471,8 @@ module_param(use_dac, int, 0);
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MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
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module_param_named(debug, debug.msg_enable, int, 0);
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MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
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module_param_named(ignore_parity_err, ignore_parity_err, bool, 0);
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MODULE_PARM_DESC(ignore_parity_err, "Ignore PCI parity error as target. Default: false");
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MODULE_LICENSE("GPL");
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MODULE_VERSION(RTL8169_VERSION);
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@ -1284,11 +1287,6 @@ static void rtl8169_hw_phy_config(struct net_device *dev)
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/* Shazam ! */
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if (tp->mac_version == RTL_GIGA_MAC_VER_04) {
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mdio_write(ioaddr, 31, 0x0001);
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mdio_write(ioaddr, 9, 0x273a);
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mdio_write(ioaddr, 14, 0x7bfb);
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mdio_write(ioaddr, 27, 0x841e);
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mdio_write(ioaddr, 31, 0x0002);
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mdio_write(ioaddr, 1, 0x90d0);
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mdio_write(ioaddr, 31, 0x0000);
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@ -1817,12 +1815,25 @@ static void rtl8169_hw_reset(void __iomem *ioaddr)
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RTL_R8(ChipCmd);
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}
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static void
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rtl8169_hw_start(struct net_device *dev)
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static void rtl8169_set_rx_tx_config_registers(struct rtl8169_private *tp)
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{
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void __iomem *ioaddr = tp->mmio_addr;
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u32 cfg = rtl8169_rx_config;
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cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
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RTL_W32(RxConfig, cfg);
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/* Set DMA burst size and Interframe Gap Time */
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RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
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(InterFrameGap << TxInterFrameGapShift));
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}
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static void rtl8169_hw_start(struct net_device *dev)
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{
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struct rtl8169_private *tp = netdev_priv(dev);
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void __iomem *ioaddr = tp->mmio_addr;
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struct pci_dev *pdev = tp->pci_dev;
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u16 cmd;
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u32 i;
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/* Soft reset the chip. */
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@ -1835,6 +1846,11 @@ rtl8169_hw_start(struct net_device *dev)
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msleep_interruptible(1);
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}
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if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
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RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
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pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
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}
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if (tp->mac_version == RTL_GIGA_MAC_VER_13) {
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pci_write_config_word(pdev, 0x68, 0x00);
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pci_write_config_word(pdev, 0x69, 0x08);
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@ -1842,8 +1858,6 @@ rtl8169_hw_start(struct net_device *dev)
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/* Undocumented stuff. */
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if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
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u16 cmd;
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/* Realtek's r1000_n.c driver uses '&& 0x01' here. Well... */
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if ((RTL_R8(Config2) & 0x07) & 0x01)
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RTL_W32(0x7c, 0x0007ffff);
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@ -1855,23 +1869,29 @@ rtl8169_hw_start(struct net_device *dev)
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pci_write_config_word(pdev, PCI_COMMAND, cmd);
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}
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RTL_W8(Cfg9346, Cfg9346_Unlock);
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if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
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(tp->mac_version == RTL_GIGA_MAC_VER_02) ||
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(tp->mac_version == RTL_GIGA_MAC_VER_03) ||
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(tp->mac_version == RTL_GIGA_MAC_VER_04))
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RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
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RTL_W8(EarlyTxThres, EarlyTxThld);
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/* Low hurts. Let's disable the filtering. */
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RTL_W16(RxMaxSize, 16383);
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/* Set Rx Config register */
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i = rtl8169_rx_config |
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(RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
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RTL_W32(RxConfig, i);
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if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
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(tp->mac_version == RTL_GIGA_MAC_VER_02) ||
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(tp->mac_version == RTL_GIGA_MAC_VER_03) ||
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(tp->mac_version == RTL_GIGA_MAC_VER_04))
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RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
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rtl8169_set_rx_tx_config_registers(tp);
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/* Set DMA burst size and Interframe Gap Time */
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RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
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(InterFrameGap << TxInterFrameGapShift));
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cmd = RTL_R16(CPlusCmd);
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RTL_W16(CPlusCmd, cmd);
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tp->cp_cmd |= RTL_R16(CPlusCmd) | PCIMulRW;
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tp->cp_cmd |= cmd | PCIMulRW;
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if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
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(tp->mac_version == RTL_GIGA_MAC_VER_03)) {
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@ -1897,7 +1917,15 @@ rtl8169_hw_start(struct net_device *dev)
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RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr & DMA_32BIT_MASK));
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RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr >> 32));
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RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr & DMA_32BIT_MASK));
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RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
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if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
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(tp->mac_version != RTL_GIGA_MAC_VER_02) &&
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(tp->mac_version != RTL_GIGA_MAC_VER_03) &&
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(tp->mac_version != RTL_GIGA_MAC_VER_04)) {
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RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
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rtl8169_set_rx_tx_config_registers(tp);
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}
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RTL_W8(Cfg9346, Cfg9346_Lock);
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/* Initially a 10 us delay. Turned it into a PCI commit. - FR */
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@ -1992,7 +2020,7 @@ static int rtl8169_alloc_rx_skb(struct pci_dev *pdev, struct sk_buff **sk_buff,
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if (!skb)
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goto err_out;
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skb_reserve(skb, align);
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skb_reserve(skb, (align - 1) & (u32)skb->data);
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*sk_buff = skb;
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mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
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@ -2355,12 +2383,17 @@ static void rtl8169_pcierr_interrupt(struct net_device *dev)
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/*
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* The recovery sequence below admits a very elaborated explanation:
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* - it seems to work;
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* - I did not see what else could be done.
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* - I did not see what else could be done;
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* - it makes iop3xx happy.
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*
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* Feel free to adjust to your needs.
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*/
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pci_write_config_word(pdev, PCI_COMMAND,
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pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
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if (ignore_parity_err)
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pci_cmd &= ~PCI_COMMAND_PARITY;
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else
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pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
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pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
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pci_write_config_word(pdev, PCI_STATUS,
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pci_status & (PCI_STATUS_DETECTED_PARITY |
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@ -2374,10 +2407,11 @@ static void rtl8169_pcierr_interrupt(struct net_device *dev)
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tp->cp_cmd &= ~PCIDAC;
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RTL_W16(CPlusCmd, tp->cp_cmd);
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dev->features &= ~NETIF_F_HIGHDMA;
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rtl8169_schedule_work(dev, rtl8169_reinit_task);
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}
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rtl8169_hw_reset(ioaddr);
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rtl8169_schedule_work(dev, rtl8169_reinit_task);
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}
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static void
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@ -2457,7 +2491,7 @@ static inline int rtl8169_try_rx_copy(struct sk_buff **sk_buff, int pkt_size,
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skb = dev_alloc_skb(pkt_size + align);
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if (skb) {
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skb_reserve(skb, align);
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skb_reserve(skb, (align - 1) & (u32)skb->data);
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eth_copy_and_sum(skb, sk_buff[0]->data, pkt_size, 0);
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*sk_buff = skb;
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rtl8169_mark_to_asic(desc, rx_buf_sz);
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