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MIPS: Octeon: Reverse the order of register accesses to the FAU

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64 bit access is unaffected but for 32 bit access, swap high and
low words.  Similarly for 16 bit access, reverse the order of the
four possible words, and for 8 bit access reverse the order of byte
accesses.

Signed-off-by: Paul Martin <paul.martin@codethink.co.uk>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9630/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Paul Martin 2015-03-30 17:00:58 +01:00 committed by Ralf Baechle
parent b0abf36ffd
commit f1e770cf51
1 changed files with 22 additions and 0 deletions
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22
arch/mips/include/asm/octeon/cvmx-fau.h
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@ -105,6 +105,16 @@ typedef union {
} s;
} cvmx_fau_async_tagwait_result_t;
#ifdef __BIG_ENDIAN_BITFIELD
#define SWIZZLE_8 0
#define SWIZZLE_16 0
#define SWIZZLE_32 0
#else
#define SWIZZLE_8 0x7
#define SWIZZLE_16 0x6
#define SWIZZLE_32 0x4
#endif
/**
* Builds a store I/O address for writing to the FAU
*
@ -175,6 +185,7 @@ static inline int64_t cvmx_fau_fetch_and_add64(cvmx_fau_reg_64_t reg,
static inline int32_t cvmx_fau_fetch_and_add32(cvmx_fau_reg_32_t reg,
int32_t value)
{
reg ^= SWIZZLE_32;
return cvmx_read64_int32(__cvmx_fau_atomic_address(0, reg, value));
}
@ -189,6 +200,7 @@ static inline int32_t cvmx_fau_fetch_and_add32(cvmx_fau_reg_32_t reg,
static inline int16_t cvmx_fau_fetch_and_add16(cvmx_fau_reg_16_t reg,
int16_t value)
{
reg ^= SWIZZLE_16;
return cvmx_read64_int16(__cvmx_fau_atomic_address(0, reg, value));
}
@ -201,6 +213,7 @@ static inline int16_t cvmx_fau_fetch_and_add16(cvmx_fau_reg_16_t reg,
*/
static inline int8_t cvmx_fau_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value)
{
reg ^= SWIZZLE_8;
return cvmx_read64_int8(__cvmx_fau_atomic_address(0, reg, value));
}
@ -247,6 +260,7 @@ cvmx_fau_tagwait_fetch_and_add32(cvmx_fau_reg_32_t reg, int32_t value)
uint64_t i32;
cvmx_fau_tagwait32_t t;
} result;
reg ^= SWIZZLE_32;
result.i32 =
cvmx_read64_int32(__cvmx_fau_atomic_address(1, reg, value));
return result.t;
@ -270,6 +284,7 @@ cvmx_fau_tagwait_fetch_and_add16(cvmx_fau_reg_16_t reg, int16_t value)
uint64_t i16;
cvmx_fau_tagwait16_t t;
} result;
reg ^= SWIZZLE_16;
result.i16 =
cvmx_read64_int16(__cvmx_fau_atomic_address(1, reg, value));
return result.t;
@ -292,6 +307,7 @@ cvmx_fau_tagwait_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value)
uint64_t i8;
cvmx_fau_tagwait8_t t;
} result;
reg ^= SWIZZLE_8;
result.i8 = cvmx_read64_int8(__cvmx_fau_atomic_address(1, reg, value));
return result.t;
}
@ -521,6 +537,7 @@ static inline void cvmx_fau_atomic_add64(cvmx_fau_reg_64_t reg, int64_t value)
*/
static inline void cvmx_fau_atomic_add32(cvmx_fau_reg_32_t reg, int32_t value)
{
reg ^= SWIZZLE_32;
cvmx_write64_int32(__cvmx_fau_store_address(0, reg), value);
}
@ -533,6 +550,7 @@ static inline void cvmx_fau_atomic_add32(cvmx_fau_reg_32_t reg, int32_t value)
*/
static inline void cvmx_fau_atomic_add16(cvmx_fau_reg_16_t reg, int16_t value)
{
reg ^= SWIZZLE_16;
cvmx_write64_int16(__cvmx_fau_store_address(0, reg), value);
}
@ -544,6 +562,7 @@ static inline void cvmx_fau_atomic_add16(cvmx_fau_reg_16_t reg, int16_t value)
*/
static inline void cvmx_fau_atomic_add8(cvmx_fau_reg_8_t reg, int8_t value)
{
reg ^= SWIZZLE_8;
cvmx_write64_int8(__cvmx_fau_store_address(0, reg), value);
}
@ -568,6 +587,7 @@ static inline void cvmx_fau_atomic_write64(cvmx_fau_reg_64_t reg, int64_t value)
*/
static inline void cvmx_fau_atomic_write32(cvmx_fau_reg_32_t reg, int32_t value)
{
reg ^= SWIZZLE_32;
cvmx_write64_int32(__cvmx_fau_store_address(1, reg), value);
}
@ -580,6 +600,7 @@ static inline void cvmx_fau_atomic_write32(cvmx_fau_reg_32_t reg, int32_t value)
*/
static inline void cvmx_fau_atomic_write16(cvmx_fau_reg_16_t reg, int16_t value)
{
reg ^= SWIZZLE_16;
cvmx_write64_int16(__cvmx_fau_store_address(1, reg), value);
}
@ -591,6 +612,7 @@ static inline void cvmx_fau_atomic_write16(cvmx_fau_reg_16_t reg, int16_t value)
*/
static inline void cvmx_fau_atomic_write8(cvmx_fau_reg_8_t reg, int8_t value)
{
reg ^= SWIZZLE_8;
cvmx_write64_int8(__cvmx_fau_store_address(1, reg), value);
}