drm/amdgpu: update umc_info v3_3 structure for ECC
new member introduced in umc_info v3_3 to indicate ECC capability Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -2635,7 +2635,18 @@ struct atom_umc_info_v3_3
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uint32_t pstate_uclk_10khz[4];
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uint32_t pstate_uclk_10khz[4];
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uint16_t umcgoldenoffset;
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uint16_t umcgoldenoffset;
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uint16_t densitygoldenoffset;
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uint16_t densitygoldenoffset;
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uint32_t reserved[4];
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uint32_t umc_config1;
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uint32_t bist_data_startaddr;
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uint32_t reserved[2];
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};
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enum atom_umc_config1_def {
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UMC_CONFIG1__ENABLE_PSTATE_PHASE_STORE_TRAIN = 0x00000001,
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UMC_CONFIG1__ENABLE_AUTO_FRAMING = 0x00000002,
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UMC_CONFIG1__ENABLE_RESTORE_BIST_DATA = 0x00000004,
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UMC_CONFIG1__DISABLE_STROBE_MODE = 0x00000008,
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UMC_CONFIG1__DEBUG_DATA_PARITY_EN = 0x00000010,
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UMC_CONFIG1__ENABLE_ECC_CAPABLE = 0x00010000,
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};
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};
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/*
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/*
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