forked from Minki/linux
kvm: x86: mmu: Lockless access tracking for Intel CPUs without EPT A bits.
This change implements lockless access tracking for Intel CPUs without EPT A bits. This is achieved by marking the PTEs as not-present (but not completely clearing them) when clear_flush_young() is called after marking the pages as accessed. When an EPT Violation is generated as a result of the VM accessing those pages, the PTEs are restored to their original values. Signed-off-by: Junaid Shahid <junaids@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
parent
37f0e8fe6b
commit
f160c7b7bb
@ -1064,7 +1064,8 @@ void kvm_mmu_setup(struct kvm_vcpu *vcpu);
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void kvm_mmu_init_vm(struct kvm *kvm);
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void kvm_mmu_uninit_vm(struct kvm *kvm);
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void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
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u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask);
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u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask,
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u64 acc_track_mask);
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void kvm_mmu_reset_context(struct kvm_vcpu *vcpu);
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void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
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@ -469,11 +469,14 @@ enum vmcs_field {
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#define VMX_EPT_IPAT_BIT (1ull << 6)
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#define VMX_EPT_ACCESS_BIT (1ull << 8)
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#define VMX_EPT_DIRTY_BIT (1ull << 9)
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#define VMX_EPT_RWX_MASK (VMX_EPT_READABLE_MASK | \
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VMX_EPT_WRITABLE_MASK | \
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VMX_EPT_EXECUTABLE_MASK)
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#define VMX_EPT_MT_MASK (7ull << VMX_EPT_MT_EPTE_SHIFT)
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/* The mask to use to trigger an EPT Misconfiguration in order to track MMIO */
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#define VMX_EPT_MISCONFIG_WX_VALUE (VMX_EPT_WRITABLE_MASK | \
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VMX_EPT_EXECUTABLE_MASK)
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#define VMX_EPT_MISCONFIG_WX_VALUE (VMX_EPT_WRITABLE_MASK | \
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VMX_EPT_EXECUTABLE_MASK)
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#define VMX_EPT_IDENTITY_PAGETABLE_ADDR 0xfffbc000ul
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@ -38,6 +38,7 @@
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#include <linux/slab.h>
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#include <linux/uaccess.h>
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#include <linux/hash.h>
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#include <linux/kern_levels.h>
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#include <asm/page.h>
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#include <asm/cmpxchg.h>
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@ -130,6 +131,10 @@ module_param(dbg, bool, 0644);
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#define ACC_USER_MASK PT_USER_MASK
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#define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
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/* The mask for the R/X bits in EPT PTEs */
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#define PT64_EPT_READABLE_MASK 0x1ull
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#define PT64_EPT_EXECUTABLE_MASK 0x4ull
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#include <trace/events/kvm.h>
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#define CREATE_TRACE_POINTS
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@ -179,6 +184,25 @@ static u64 __read_mostly shadow_dirty_mask;
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static u64 __read_mostly shadow_mmio_mask;
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static u64 __read_mostly shadow_present_mask;
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/*
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* The mask/value to distinguish a PTE that has been marked not-present for
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* access tracking purposes.
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* The mask would be either 0 if access tracking is disabled, or
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* SPTE_SPECIAL_MASK|VMX_EPT_RWX_MASK if access tracking is enabled.
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*/
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static u64 __read_mostly shadow_acc_track_mask;
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static const u64 shadow_acc_track_value = SPTE_SPECIAL_MASK;
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/*
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* The mask/shift to use for saving the original R/X bits when marking the PTE
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* as not-present for access tracking purposes. We do not save the W bit as the
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* PTEs being access tracked also need to be dirty tracked, so the W bit will be
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* restored only when a write is attempted to the page.
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*/
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static const u64 shadow_acc_track_saved_bits_mask = PT64_EPT_READABLE_MASK |
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PT64_EPT_EXECUTABLE_MASK;
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static const u64 shadow_acc_track_saved_bits_shift = PT64_SECOND_AVAIL_BITS_SHIFT;
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static void mmu_spte_set(u64 *sptep, u64 spte);
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static void mmu_free_roots(struct kvm_vcpu *vcpu);
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@ -188,6 +212,12 @@ void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask)
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}
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EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
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static inline bool is_access_track_spte(u64 spte)
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{
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/* Always false if shadow_acc_track_mask is zero. */
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return (spte & shadow_acc_track_mask) == shadow_acc_track_value;
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}
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/*
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* the low bit of the generation number is always presumed to be zero.
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* This disables mmio caching during memslot updates. The concept is
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@ -285,7 +315,8 @@ static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte)
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}
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void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
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u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask)
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u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask,
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u64 acc_track_mask)
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{
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shadow_user_mask = user_mask;
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shadow_accessed_mask = accessed_mask;
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@ -293,9 +324,23 @@ void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
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shadow_nx_mask = nx_mask;
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shadow_x_mask = x_mask;
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shadow_present_mask = p_mask;
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shadow_acc_track_mask = acc_track_mask;
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WARN_ON(shadow_accessed_mask != 0 && shadow_acc_track_mask != 0);
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}
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EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
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void kvm_mmu_clear_all_pte_masks(void)
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{
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shadow_user_mask = 0;
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shadow_accessed_mask = 0;
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shadow_dirty_mask = 0;
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shadow_nx_mask = 0;
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shadow_x_mask = 0;
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shadow_mmio_mask = 0;
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shadow_present_mask = 0;
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shadow_acc_track_mask = 0;
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}
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static int is_cpuid_PSE36(void)
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{
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return 1;
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@ -308,7 +353,7 @@ static int is_nx(struct kvm_vcpu *vcpu)
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static int is_shadow_present_pte(u64 pte)
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{
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return (pte & 0xFFFFFFFFull) && !is_mmio_spte(pte);
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return (pte != 0) && !is_mmio_spte(pte);
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}
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static int is_large_pte(u64 pte)
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@ -482,32 +527,32 @@ static bool spte_can_locklessly_be_made_writable(u64 spte)
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static bool spte_has_volatile_bits(u64 spte)
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{
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if (!is_shadow_present_pte(spte))
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return false;
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/*
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* Always atomically update spte if it can be updated
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* out of mmu-lock, it can ensure dirty bit is not lost,
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* also, it can help us to get a stable is_writable_pte()
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* to ensure tlb flush is not missed.
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*/
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if (spte_can_locklessly_be_made_writable(spte))
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if (spte_can_locklessly_be_made_writable(spte) ||
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is_access_track_spte(spte))
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return true;
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if (!shadow_accessed_mask)
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return false;
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if (shadow_accessed_mask) {
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if ((spte & shadow_accessed_mask) == 0 ||
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(is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0))
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return true;
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}
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if (!is_shadow_present_pte(spte))
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return false;
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if ((spte & shadow_accessed_mask) &&
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(!is_writable_pte(spte) || (spte & shadow_dirty_mask)))
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return false;
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return true;
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return false;
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}
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static bool is_accessed_spte(u64 spte)
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{
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return shadow_accessed_mask ? spte & shadow_accessed_mask
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: true;
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: !is_access_track_spte(spte);
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}
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static bool is_dirty_spte(u64 spte)
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@ -651,6 +696,61 @@ static u64 mmu_spte_get_lockless(u64 *sptep)
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return __get_spte_lockless(sptep);
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}
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static u64 mark_spte_for_access_track(u64 spte)
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{
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if (shadow_accessed_mask != 0)
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return spte & ~shadow_accessed_mask;
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if (shadow_acc_track_mask == 0 || is_access_track_spte(spte))
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return spte;
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/*
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* Verify that the write-protection that we do below will be fixable
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* via the fast page fault path. Currently, that is always the case, at
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* least when using EPT (which is when access tracking would be used).
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*/
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WARN_ONCE((spte & PT_WRITABLE_MASK) &&
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!spte_can_locklessly_be_made_writable(spte),
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"kvm: Writable SPTE is not locklessly dirty-trackable\n");
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WARN_ONCE(spte & (shadow_acc_track_saved_bits_mask <<
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shadow_acc_track_saved_bits_shift),
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"kvm: Access Tracking saved bit locations are not zero\n");
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spte |= (spte & shadow_acc_track_saved_bits_mask) <<
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shadow_acc_track_saved_bits_shift;
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spte &= ~shadow_acc_track_mask;
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spte |= shadow_acc_track_value;
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return spte;
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}
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/* Returns the Accessed status of the PTE and resets it at the same time. */
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static bool mmu_spte_age(u64 *sptep)
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{
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u64 spte = mmu_spte_get_lockless(sptep);
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if (!is_accessed_spte(spte))
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return false;
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if (shadow_accessed_mask) {
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clear_bit((ffs(shadow_accessed_mask) - 1),
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(unsigned long *)sptep);
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} else {
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/*
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* Capture the dirty status of the page, so that it doesn't get
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* lost when the SPTE is marked for access tracking.
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*/
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if (is_writable_pte(spte))
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kvm_set_pfn_dirty(spte_to_pfn(spte));
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spte = mark_spte_for_access_track(spte);
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mmu_spte_update_no_track(sptep, spte);
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}
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return true;
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}
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static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
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{
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/*
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@ -1435,7 +1535,7 @@ static int kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
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restart:
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for_each_rmap_spte(rmap_head, &iter, sptep) {
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rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n",
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sptep, *sptep, gfn, level);
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sptep, *sptep, gfn, level);
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need_flush = 1;
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@ -1448,7 +1548,8 @@ restart:
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new_spte &= ~PT_WRITABLE_MASK;
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new_spte &= ~SPTE_HOST_WRITEABLE;
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new_spte &= ~shadow_accessed_mask;
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new_spte = mark_spte_for_access_track(new_spte);
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mmu_spte_clear_track_bits(sptep);
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mmu_spte_set(sptep, new_spte);
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@ -1610,15 +1711,8 @@ static int kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
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struct rmap_iterator uninitialized_var(iter);
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int young = 0;
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BUG_ON(!shadow_accessed_mask);
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for_each_rmap_spte(rmap_head, &iter, sptep) {
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if (*sptep & shadow_accessed_mask) {
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young = 1;
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clear_bit((ffs(shadow_accessed_mask) - 1),
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(unsigned long *)sptep);
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}
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}
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for_each_rmap_spte(rmap_head, &iter, sptep)
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young |= mmu_spte_age(sptep);
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trace_kvm_age_page(gfn, level, slot, young);
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return young;
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@ -1632,11 +1726,11 @@ static int kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
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struct rmap_iterator iter;
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/*
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* If there's no access bit in the secondary pte set by the
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* hardware it's up to gup-fast/gup to set the access bit in
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* the primary pte or in the page structure.
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* If there's no access bit in the secondary pte set by the hardware and
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* fast access tracking is also not enabled, it's up to gup-fast/gup to
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* set the access bit in the primary pte or in the page structure.
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*/
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if (!shadow_accessed_mask)
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if (!shadow_accessed_mask && !shadow_acc_track_mask)
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goto out;
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for_each_rmap_spte(rmap_head, &iter, sptep)
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@ -1671,7 +1765,7 @@ int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end)
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* This has some overhead, but not as much as the cost of swapping
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* out actively used pages or breaking up actively used hugepages.
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*/
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if (!shadow_accessed_mask)
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if (!shadow_accessed_mask && !shadow_acc_track_mask)
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return kvm_handle_hva_range(kvm, start, end, 0,
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kvm_unmap_rmapp);
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@ -2603,6 +2697,9 @@ static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
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spte |= shadow_dirty_mask;
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}
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if (speculative)
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spte = mark_spte_for_access_track(spte);
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set_pte:
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if (mmu_spte_update(sptep, spte))
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kvm_flush_remote_tlbs(vcpu->kvm);
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@ -2656,7 +2753,7 @@ static bool mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, unsigned pte_access,
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pgprintk("%s: setting spte %llx\n", __func__, *sptep);
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pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
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is_large_pte(*sptep)? "2MB" : "4kB",
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*sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
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*sptep & PT_WRITABLE_MASK ? "RW" : "R", gfn,
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*sptep, sptep);
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if (!was_rmapped && is_large_pte(*sptep))
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++vcpu->kvm->stat.lpages;
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@ -2889,16 +2986,28 @@ static bool page_fault_can_be_fast(u32 error_code)
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if (unlikely(error_code & PFERR_RSVD_MASK))
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return false;
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/*
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* #PF can be fast only if the shadow page table is present and it
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* is caused by write-protect, that means we just need change the
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* W bit of the spte which can be done out of mmu-lock.
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*/
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if (!(error_code & PFERR_PRESENT_MASK) ||
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!(error_code & PFERR_WRITE_MASK))
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/* See if the page fault is due to an NX violation */
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if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))
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== (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))))
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return false;
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return true;
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/*
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* #PF can be fast if:
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* 1. The shadow page table entry is not present, which could mean that
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* the fault is potentially caused by access tracking (if enabled).
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* 2. The shadow page table entry is present and the fault
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* is caused by write-protect, that means we just need change the W
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* bit of the spte which can be done out of mmu-lock.
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*
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* However, if access tracking is disabled we know that a non-present
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* page must be a genuine page fault where we have to create a new SPTE.
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* So, if access tracking is disabled, we return true only for write
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* accesses to a present page.
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*/
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return shadow_acc_track_mask != 0 ||
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((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK))
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== (PFERR_WRITE_MASK | PFERR_PRESENT_MASK));
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}
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/*
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@ -2907,17 +3016,26 @@ static bool page_fault_can_be_fast(u32 error_code)
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*/
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static bool
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fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
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u64 *sptep, u64 spte)
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u64 *sptep, u64 old_spte,
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bool remove_write_prot, bool remove_acc_track)
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{
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gfn_t gfn;
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u64 new_spte = old_spte;
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WARN_ON(!sp->role.direct);
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/*
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* The gfn of direct spte is stable since it is calculated
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* by sp->gfn.
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*/
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gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
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if (remove_acc_track) {
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u64 saved_bits = (old_spte >> shadow_acc_track_saved_bits_shift)
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& shadow_acc_track_saved_bits_mask;
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new_spte &= ~shadow_acc_track_mask;
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new_spte &= ~(shadow_acc_track_saved_bits_mask <<
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shadow_acc_track_saved_bits_shift);
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new_spte |= saved_bits;
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}
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if (remove_write_prot)
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new_spte |= PT_WRITABLE_MASK;
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/*
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* Theoretically we could also set dirty bit (and flush TLB) here in
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@ -2931,10 +3049,17 @@ fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
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*
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* Compare with set_spte where instead shadow_dirty_mask is set.
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*/
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if (cmpxchg64(sptep, spte, spte | PT_WRITABLE_MASK) != spte)
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if (cmpxchg64(sptep, old_spte, new_spte) != old_spte)
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return false;
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kvm_vcpu_mark_page_dirty(vcpu, gfn);
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if (remove_write_prot) {
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/*
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* The gfn of direct spte is stable since it is
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* calculated by sp->gfn.
|
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*/
|
||||
gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
|
||||
kvm_vcpu_mark_page_dirty(vcpu, gfn);
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
@ -2965,35 +3090,55 @@ static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level,
|
||||
break;
|
||||
|
||||
do {
|
||||
/*
|
||||
* If the mapping has been changed, let the vcpu fault on the
|
||||
* same address again.
|
||||
*/
|
||||
if (!is_shadow_present_pte(spte)) {
|
||||
fault_handled = true;
|
||||
break;
|
||||
}
|
||||
bool remove_write_prot = false;
|
||||
bool remove_acc_track;
|
||||
|
||||
sp = page_header(__pa(iterator.sptep));
|
||||
if (!is_last_spte(spte, sp->role.level))
|
||||
break;
|
||||
|
||||
/*
|
||||
* Check if it is a spurious fault caused by TLB lazily flushed.
|
||||
* Check whether the memory access that caused the fault would
|
||||
* still cause it if it were to be performed right now. If not,
|
||||
* then this is a spurious fault caused by TLB lazily flushed,
|
||||
* or some other CPU has already fixed the PTE after the
|
||||
* current CPU took the fault.
|
||||
*
|
||||
* Need not check the access of upper level table entries since
|
||||
* they are always ACC_ALL.
|
||||
*/
|
||||
if (is_writable_pte(spte)) {
|
||||
fault_handled = true;
|
||||
break;
|
||||
|
||||
if (error_code & PFERR_FETCH_MASK) {
|
||||
if ((spte & (shadow_x_mask | shadow_nx_mask))
|
||||
== shadow_x_mask) {
|
||||
fault_handled = true;
|
||||
break;
|
||||
}
|
||||
} else if (error_code & PFERR_WRITE_MASK) {
|
||||
if (is_writable_pte(spte)) {
|
||||
fault_handled = true;
|
||||
break;
|
||||
}
|
||||
|
||||
/*
|
||||
* Currently, to simplify the code, write-protection can
|
||||
* be removed in the fast path only if the SPTE was
|
||||
* write-protected for dirty-logging.
|
||||
*/
|
||||
remove_write_prot =
|
||||
spte_can_locklessly_be_made_writable(spte);
|
||||
} else {
|
||||
/* Fault was on Read access */
|
||||
if (spte & PT_PRESENT_MASK) {
|
||||
fault_handled = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Currently, to simplify the code, only the spte
|
||||
* write-protected by dirty-log can be fast fixed.
|
||||
*/
|
||||
if (!spte_can_locklessly_be_made_writable(spte))
|
||||
remove_acc_track = is_access_track_spte(spte);
|
||||
|
||||
/* Verify that the fault can be handled in the fast path */
|
||||
if (!remove_acc_track && !remove_write_prot)
|
||||
break;
|
||||
|
||||
/*
|
||||
@ -3007,7 +3152,7 @@ static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level,
|
||||
*
|
||||
* See the comments in kvm_arch_commit_memory_region().
|
||||
*/
|
||||
if (sp->role.level > PT_PAGE_TABLE_LEVEL)
|
||||
if (sp->role.level > PT_PAGE_TABLE_LEVEL && remove_write_prot)
|
||||
break;
|
||||
|
||||
/*
|
||||
@ -3016,7 +3161,9 @@ static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level,
|
||||
* Documentation/virtual/kvm/locking.txt to get more detail.
|
||||
*/
|
||||
fault_handled = fast_pf_fix_direct_spte(vcpu, sp,
|
||||
iterator.sptep, spte);
|
||||
iterator.sptep, spte,
|
||||
remove_write_prot,
|
||||
remove_acc_track);
|
||||
if (fault_handled)
|
||||
break;
|
||||
|
||||
@ -5105,6 +5252,8 @@ static void mmu_destroy_caches(void)
|
||||
|
||||
int kvm_mmu_module_init(void)
|
||||
{
|
||||
kvm_mmu_clear_all_pte_masks();
|
||||
|
||||
pte_list_desc_cache = kmem_cache_create("pte_list_desc",
|
||||
sizeof(struct pte_list_desc),
|
||||
0, 0, NULL);
|
||||
|
@ -6578,6 +6578,19 @@ static void wakeup_handler(void)
|
||||
spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
|
||||
}
|
||||
|
||||
void vmx_enable_tdp(void)
|
||||
{
|
||||
kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
|
||||
enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
|
||||
enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
|
||||
0ull, VMX_EPT_EXECUTABLE_MASK,
|
||||
cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
|
||||
enable_ept_ad_bits ? 0ull : SPTE_SPECIAL_MASK | VMX_EPT_RWX_MASK);
|
||||
|
||||
ept_set_mmio_spte_mask();
|
||||
kvm_enable_tdp();
|
||||
}
|
||||
|
||||
static __init int hardware_setup(void)
|
||||
{
|
||||
int r = -ENOMEM, i, msr;
|
||||
@ -6703,16 +6716,9 @@ static __init int hardware_setup(void)
|
||||
/* SELF-IPI */
|
||||
vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W, true);
|
||||
|
||||
if (enable_ept) {
|
||||
kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
|
||||
(enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
|
||||
(enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
|
||||
0ull, VMX_EPT_EXECUTABLE_MASK,
|
||||
cpu_has_vmx_ept_execute_only() ?
|
||||
0ull : VMX_EPT_READABLE_MASK);
|
||||
ept_set_mmio_spte_mask();
|
||||
kvm_enable_tdp();
|
||||
} else
|
||||
if (enable_ept)
|
||||
vmx_enable_tdp();
|
||||
else
|
||||
kvm_disable_tdp();
|
||||
|
||||
update_ple_window_actual_max();
|
||||
|
@ -6025,7 +6025,7 @@ int kvm_arch_init(void *opaque)
|
||||
|
||||
kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
|
||||
PT_DIRTY_MASK, PT64_NX_MASK, 0,
|
||||
PT_PRESENT_MASK);
|
||||
PT_PRESENT_MASK, 0);
|
||||
kvm_timer_init();
|
||||
|
||||
perf_register_guest_info_callbacks(&kvm_guest_cbs);
|
||||
|
Loading…
Reference in New Issue
Block a user