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drivers: net: xgene: fix: Coalescing values for v2 hardware

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Changing the interrupt trigger region id to 2 and the
corresponding threshold set0/set1 values to 8/16.

Signed-off-by: Iyappan Subramanian <isubramanian@apm.com>
Signed-off-by: Toan Le <toanle@apm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Iyappan Subramanian 2016-10-31 16:00:27 -07:00 committed by David S. Miller
parent b5a4a3eb4e
commit f126df8503
2 changed files with 9 additions and 5 deletions
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2
drivers/net/ethernet/apm/xgene/xgene_enet_hw.h
View File

@ -55,8 +55,10 @@ enum xgene_enet_rm {
#define PREFETCH_BUF_EN BIT(21) #define PREFETCH_BUF_EN BIT(21)
#define CSR_RING_ID_BUF 0x000c #define CSR_RING_ID_BUF 0x000c
#define CSR_PBM_COAL 0x0014 #define CSR_PBM_COAL 0x0014
#define CSR_PBM_CTICK0 0x0018
#define CSR_PBM_CTICK1 0x001c #define CSR_PBM_CTICK1 0x001c
#define CSR_PBM_CTICK2 0x0020 #define CSR_PBM_CTICK2 0x0020
#define CSR_PBM_CTICK3 0x0024
#define CSR_THRESHOLD0_SET1 0x0030 #define CSR_THRESHOLD0_SET1 0x0030
#define CSR_THRESHOLD1_SET1 0x0034 #define CSR_THRESHOLD1_SET1 0x0034
#define CSR_RING_NE_INT_MODE 0x017c #define CSR_RING_NE_INT_MODE 0x017c

12
drivers/net/ethernet/apm/xgene/xgene_enet_ring2.c
View File

@ -30,7 +30,7 @@ static void xgene_enet_ring_init(struct xgene_enet_desc_ring *ring)
ring_cfg[0] |= SET_VAL(X2_INTLINE, ring->id & RING_BUFNUM_MASK); ring_cfg[0] |= SET_VAL(X2_INTLINE, ring->id & RING_BUFNUM_MASK);
ring_cfg[3] |= SET_BIT(X2_DEQINTEN); ring_cfg[3] |= SET_BIT(X2_DEQINTEN);
} }
ring_cfg[0] |= SET_VAL(X2_CFGCRID, 1); ring_cfg[0] |= SET_VAL(X2_CFGCRID, 2);
addr >>= 8; addr >>= 8;
ring_cfg[2] |= QCOHERENT | SET_VAL(RINGADDRL, addr); ring_cfg[2] |= QCOHERENT | SET_VAL(RINGADDRL, addr);
@ -192,13 +192,15 @@ static u32 xgene_enet_ring_len(struct xgene_enet_desc_ring *ring)
static void xgene_enet_setup_coalescing(struct xgene_enet_desc_ring *ring) static void xgene_enet_setup_coalescing(struct xgene_enet_desc_ring *ring)
{ {
u32 data = 0x7777; u32 data = 0x77777777;
xgene_enet_ring_wr32(ring, CSR_PBM_COAL, 0x8e); xgene_enet_ring_wr32(ring, CSR_PBM_COAL, 0x8e);
xgene_enet_ring_wr32(ring, CSR_PBM_CTICK0, data);
xgene_enet_ring_wr32(ring, CSR_PBM_CTICK1, data); xgene_enet_ring_wr32(ring, CSR_PBM_CTICK1, data);
xgene_enet_ring_wr32(ring, CSR_PBM_CTICK2, data << 16); xgene_enet_ring_wr32(ring, CSR_PBM_CTICK2, data);
xgene_enet_ring_wr32(ring, CSR_THRESHOLD0_SET1, 0x40); xgene_enet_ring_wr32(ring, CSR_PBM_CTICK3, data);
xgene_enet_ring_wr32(ring, CSR_THRESHOLD1_SET1, 0x80); xgene_enet_ring_wr32(ring, CSR_THRESHOLD0_SET1, 0x08);
xgene_enet_ring_wr32(ring, CSR_THRESHOLD1_SET1, 0x10);
} }
struct xgene_ring_ops xgene_ring2_ops = { struct xgene_ring_ops xgene_ring2_ops = {