forked from Minki/linux
x86: cpufeature: add Intel features from CPUID and AVX specs
Add all Intel CPUID features currently documented in the CPUID spec (AP-485, 241618-032, Dec 2007) and the AVX Programming Reference (319433-003, Aug 2008). Signed-off-by: H. Peter Anvin <hpa@zytor.com>
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@ -91,6 +91,8 @@
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/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
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#define X86_FEATURE_XMM3 (4*32+ 0) /* "pni" SSE-3 */
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#define X86_FEATURE_PCLMULQDQ (4*32+ 1) /* PCLMULQDQ instruction */
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#define X86_FEATURE_DTES64 (4*32+ 2) /* 64-bit Debug Store */
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#define X86_FEATURE_MWAIT (4*32+ 3) /* "monitor" Monitor/Mwait support */
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#define X86_FEATURE_DSCPL (4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */
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#define X86_FEATURE_VMX (4*32+ 5) /* Hardware virtualization */
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@ -99,11 +101,18 @@
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#define X86_FEATURE_TM2 (4*32+ 8) /* Thermal Monitor 2 */
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#define X86_FEATURE_SSSE3 (4*32+ 9) /* Supplemental SSE-3 */
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#define X86_FEATURE_CID (4*32+10) /* Context ID */
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#define X86_FEATURE_FMA (4*32+12) /* Fused multiply-add */
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#define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */
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#define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */
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#define X86_FEATURE_PDCM (4*32+15) /* Performance Capabilities */
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#define X86_FEATURE_DCA (4*32+18) /* Direct Cache Access */
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#define X86_FEATURE_XMM4_1 (4*32+19) /* "sse4_1" SSE-4.1 */
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#define X86_FEATURE_XMM4_2 (4*32+20) /* "sse4_2" SSE-4.2 */
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#define X86_FEATURE_X2APIC (4*32+21) /* x2APIC */
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#define X86_FEATURE_AES (4*32+25) /* AES instructions */
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#define X86_FEATURE_XSAVE (4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
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#define X86_FEATURE_OSXSAVE (4*32+27) /* "" XSAVE enabled in the OS */
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#define X86_FEATURE_AVX (4*32+28) /* Advanced Vector Extensions */
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/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
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#define X86_FEATURE_XSTORE (5*32+ 2) /* "rng" RNG present (xstore) */
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@ -213,7 +222,10 @@ extern const char * const x86_power_flags[32];
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#define cpu_has_gbpages boot_cpu_has(X86_FEATURE_GBPAGES)
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#define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON)
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#define cpu_has_pat boot_cpu_has(X86_FEATURE_PAT)
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#define cpu_has_xmm4_1 boot_cpu_has(X86_FEATURE_XMM4_1)
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#define cpu_has_xmm4_2 boot_cpu_has(X86_FEATURE_XMM4_2)
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#define cpu_has_x2apic boot_cpu_has(X86_FEATURE_X2APIC)
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#define cpu_has_xsave boot_cpu_has(X86_FEATURE_XSAVE)
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#if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64)
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# define cpu_has_invlpg 1
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