forked from Minki/linux
staging: octeon-usb: use a single .h file
Merge USBC and USBN register definitions into a single header file. Although all HW definitions are purely internal to the driver, it's better to keep them separate due to the large size of the file. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Aaro Koskinen
Greg Kroah-Hartman
parent
7d7bc26b1d
commit
f121910396
@ -1,343 +0,0 @@
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/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
|
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* permission.
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* This Software, including technical data, may be subject to U.S. export
|
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* control laws, including the U.S. Export Administration Act and its associated
|
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* regulations, and may be subject to export or import regulations in other
|
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* countries.
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||||
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||||
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
|
||||
* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
|
||||
* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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||||
* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION
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* OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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/**
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* cvmx-usbnx-defs.h
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*
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* Configuration and status register (CSR) type definitions for
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* Octeon usbnx.
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*
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*/
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#ifndef __CVMX_USBNX_TYPEDEFS_H__
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#define __CVMX_USBNX_TYPEDEFS_H__
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#define CVMX_USBNXBID1(bid) (((bid) & 1) * 0x10000000ull)
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#define CVMX_USBNXBID2(bid) (((bid) & 1) * 0x100000000000ull)
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#define CVMX_USBNXREG1(reg, bid) \
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(CVMX_ADD_IO_SEG(0x0001180068000000ull | reg) + CVMX_USBNXBID1(bid))
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#define CVMX_USBNXREG2(reg, bid) \
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(CVMX_ADD_IO_SEG(0x00016F0000000000ull | reg) + CVMX_USBNXBID2(bid))
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#define CVMX_USBNX_CLK_CTL(bid) CVMX_USBNXREG1(0x10, bid)
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#define CVMX_USBNX_DMA0_INB_CHN0(bid) CVMX_USBNXREG2(0x818, bid)
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#define CVMX_USBNX_DMA0_OUTB_CHN0(bid) CVMX_USBNXREG2(0x858, bid)
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#define CVMX_USBNX_USBP_CTL_STATUS(bid) CVMX_USBNXREG1(0x18, bid)
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/**
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* cvmx_usbn#_clk_ctl
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*
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* USBN_CLK_CTL = USBN's Clock Control
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*
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* This register is used to control the frequency of the hclk and the
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* hreset and phy_rst signals.
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*/
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union cvmx_usbnx_clk_ctl {
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uint64_t u64;
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/**
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* struct cvmx_usbnx_clk_ctl_s
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* @divide2: The 'hclk' used by the USB subsystem is derived
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* from the eclk.
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* Also see the field DIVIDE. DIVIDE2<1> must currently
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* be zero because it is not implemented, so the maximum
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* ratio of eclk/hclk is currently 16.
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* The actual divide number for hclk is:
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* (DIVIDE2 + 1) * (DIVIDE + 1)
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* @hclk_rst: When this field is '0' the HCLK-DIVIDER used to
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* generate the hclk in the USB Subsystem is held
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* in reset. This bit must be set to '0' before
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* changing the value os DIVIDE in this register.
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* The reset to the HCLK_DIVIDERis also asserted
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* when core reset is asserted.
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* @p_x_on: Force USB-PHY on during suspend.
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* '1' USB-PHY XO block is powered-down during
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* suspend.
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* '0' USB-PHY XO block is powered-up during
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* suspend.
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* The value of this field must be set while POR is
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* active.
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* @p_rtype: PHY reference clock type
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* On CN50XX/CN52XX/CN56XX the values are:
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* '0' The USB-PHY uses a 12MHz crystal as a clock source
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* at the USB_XO and USB_XI pins.
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* '1' Reserved.
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* '2' The USB_PHY uses 12/24/48MHz 2.5V board clock at the
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* USB_XO pin. USB_XI should be tied to ground in this
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* case.
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* '3' Reserved.
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* On CN3xxx bits 14 and 15 are p_xenbn and p_rclk and values are:
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* '0' Reserved.
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* '1' Reserved.
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* '2' The PHY PLL uses the XO block output as a reference.
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* The XO block uses an external clock supplied on the
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* XO pin. USB_XI should be tied to ground for this
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* usage.
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* '3' The XO block uses the clock from a crystal.
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* @p_com_on: '0' Force USB-PHY XO Bias, Bandgap and PLL to
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* remain powered in Suspend Mode.
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* '1' The USB-PHY XO Bias, Bandgap and PLL are
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* powered down in suspend mode.
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* The value of this field must be set while POR is
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* active.
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* @p_c_sel: Phy clock speed select.
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* Selects the reference clock / crystal frequency.
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* '11': Reserved
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* '10': 48 MHz (reserved when a crystal is used)
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* '01': 24 MHz (reserved when a crystal is used)
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* '00': 12 MHz
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* The value of this field must be set while POR is
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* active.
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* NOTE: if a crystal is used as a reference clock,
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* this field must be set to 12 MHz.
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* @cdiv_byp: Used to enable the bypass input to the USB_CLK_DIV.
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* @sd_mode: Scaledown mode for the USBC. Control timing events
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* in the USBC, for normal operation this must be '0'.
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* @s_bist: Starts bist on the hclk memories, during the '0'
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* to '1' transition.
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* @por: Power On Reset for the PHY.
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* Resets all the PHYS registers and state machines.
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* @enable: When '1' allows the generation of the hclk. When
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* '0' the hclk will not be generated. SEE DIVIDE
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* field of this register.
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* @prst: When this field is '0' the reset associated with
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* the phy_clk functionality in the USB Subsystem is
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* help in reset. This bit should not be set to '1'
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* until the time it takes 6 clocks (hclk or phy_clk,
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* whichever is slower) has passed. Under normal
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* operation once this bit is set to '1' it should not
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* be set to '0'.
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* @hrst: When this field is '0' the reset associated with
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* the hclk functioanlity in the USB Subsystem is
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* held in reset.This bit should not be set to '1'
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* until 12ms after phy_clk is stable. Under normal
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* operation, once this bit is set to '1' it should
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* not be set to '0'.
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* @divide: The frequency of 'hclk' used by the USB subsystem
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* is the eclk frequency divided by the value of
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* (DIVIDE2 + 1) * (DIVIDE + 1), also see the field
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* DIVIDE2 of this register.
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* The hclk frequency should be less than 125Mhz.
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* After writing a value to this field the SW should
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* read the field for the value written.
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* The ENABLE field of this register should not be set
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* until AFTER this field is set and then read.
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*/
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struct cvmx_usbnx_clk_ctl_s {
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uint64_t reserved_20_63 : 44;
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uint64_t divide2 : 2;
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uint64_t hclk_rst : 1;
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uint64_t p_x_on : 1;
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uint64_t p_rtype : 2;
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uint64_t p_com_on : 1;
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uint64_t p_c_sel : 2;
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uint64_t cdiv_byp : 1;
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uint64_t sd_mode : 2;
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uint64_t s_bist : 1;
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uint64_t por : 1;
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uint64_t enable : 1;
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uint64_t prst : 1;
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uint64_t hrst : 1;
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uint64_t divide : 3;
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} s;
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};
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/**
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* cvmx_usbn#_usbp_ctl_status
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*
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* USBN_USBP_CTL_STATUS = USBP Control And Status Register
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*
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* Contains general control and status information for the USBN block.
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*/
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union cvmx_usbnx_usbp_ctl_status {
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uint64_t u64;
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/**
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* struct cvmx_usbnx_usbp_ctl_status_s
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* @txrisetune: HS Transmitter Rise/Fall Time Adjustment
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* @txvreftune: HS DC Voltage Level Adjustment
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* @txfslstune: FS/LS Source Impedence Adjustment
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* @txhsxvtune: Transmitter High-Speed Crossover Adjustment
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* @sqrxtune: Squelch Threshold Adjustment
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* @compdistune: Disconnect Threshold Adjustment
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* @otgtune: VBUS Valid Threshold Adjustment
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* @otgdisable: OTG Block Disable
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* @portreset: Per_Port Reset
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* @drvvbus: Drive VBUS
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* @lsbist: Low-Speed BIST Enable.
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* @fsbist: Full-Speed BIST Enable.
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* @hsbist: High-Speed BIST Enable.
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* @bist_done: PHY Bist Done.
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* Asserted at the end of the PHY BIST sequence.
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* @bist_err: PHY Bist Error.
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* Indicates an internal error was detected during
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* the BIST sequence.
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* @tdata_out: PHY Test Data Out.
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* Presents either internaly generated signals or
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* test register contents, based upon the value of
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* test_data_out_sel.
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* @siddq: Drives the USBP (USB-PHY) SIDDQ input.
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* Normally should be set to zero.
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* When customers have no intent to use USB PHY
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* interface, they should:
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* - still provide 3.3V to USB_VDD33, and
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* - tie USB_REXT to 3.3V supply, and
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* - set USBN*_USBP_CTL_STATUS[SIDDQ]=1
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* @txpreemphasistune: HS Transmitter Pre-Emphasis Enable
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* @dma_bmode: When set to 1 the L2C DMA address will be updated
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* with byte-counts between packets. When set to 0
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* the L2C DMA address is incremented to the next
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* 4-byte aligned address after adding byte-count.
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* @usbc_end: Bigendian input to the USB Core. This should be
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* set to '0' for operation.
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* @usbp_bist: PHY, This is cleared '0' to run BIST on the USBP.
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* @tclk: PHY Test Clock, used to load TDATA_IN to the USBP.
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* @dp_pulld: PHY DP_PULLDOWN input to the USB-PHY.
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* This signal enables the pull-down resistance on
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* the D+ line. '1' pull down-resistance is connected
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* to D+/ '0' pull down resistance is not connected
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* to D+. When an A/B device is acting as a host
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* (downstream-facing port), dp_pulldown and
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* dm_pulldown are enabled. This must not toggle
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* during normal opeartion.
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* @dm_pulld: PHY DM_PULLDOWN input to the USB-PHY.
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* This signal enables the pull-down resistance on
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* the D- line. '1' pull down-resistance is connected
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* to D-. '0' pull down resistance is not connected
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* to D-. When an A/B device is acting as a host
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* (downstream-facing port), dp_pulldown and
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* dm_pulldown are enabled. This must not toggle
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* during normal opeartion.
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* @hst_mode: When '0' the USB is acting as HOST, when '1'
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* USB is acting as device. This field needs to be
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* set while the USB is in reset.
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* @tuning: Transmitter Tuning for High-Speed Operation.
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* Tunes the current supply and rise/fall output
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* times for high-speed operation.
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* [20:19] == 11: Current supply increased
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* approximately 9%
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* [20:19] == 10: Current supply increased
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* approximately 4.5%
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* [20:19] == 01: Design default.
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* [20:19] == 00: Current supply decreased
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* approximately 4.5%
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* [22:21] == 11: Rise and fall times are increased.
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* [22:21] == 10: Design default.
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* [22:21] == 01: Rise and fall times are decreased.
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* [22:21] == 00: Rise and fall times are decreased
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* further as compared to the 01 setting.
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* @tx_bs_enh: Transmit Bit Stuffing on [15:8].
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* Enables or disables bit stuffing on data[15:8]
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* when bit-stuffing is enabled.
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* @tx_bs_en: Transmit Bit Stuffing on [7:0].
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* Enables or disables bit stuffing on data[7:0]
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* when bit-stuffing is enabled.
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* @loop_enb: PHY Loopback Test Enable.
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* '1': During data transmission the receive is
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* enabled.
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* '0': During data transmission the receive is
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* disabled.
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* Must be '0' for normal operation.
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* @vtest_enb: Analog Test Pin Enable.
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* '1' The PHY's analog_test pin is enabled for the
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* input and output of applicable analog test signals.
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* '0' THe analog_test pin is disabled.
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* @bist_enb: Built-In Self Test Enable.
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* Used to activate BIST in the PHY.
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* @tdata_sel: Test Data Out Select.
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* '1' test_data_out[3:0] (PHY) register contents
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* are output. '0' internaly generated signals are
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* output.
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* @taddr_in: Mode Address for Test Interface.
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* Specifies the register address for writing to or
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* reading from the PHY test interface register.
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* @tdata_in: Internal Testing Register Input Data and Select
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* This is a test bus. Data is present on [3:0],
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* and its corresponding select (enable) is present
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* on bits [7:4].
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* @ate_reset: Reset input from automatic test equipment.
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* This is a test signal. When the USB Core is
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* powered up (not in Susned Mode), an automatic
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* tester can use this to disable phy_clock and
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* free_clk, then re-eanable them with an aligned
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* phase.
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* '1': The phy_clk and free_clk outputs are
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* disabled. "0": The phy_clock and free_clk outputs
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* are available within a specific period after the
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* de-assertion.
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*/
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struct cvmx_usbnx_usbp_ctl_status_s {
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uint64_t txrisetune : 1;
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uint64_t txvreftune : 4;
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uint64_t txfslstune : 4;
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uint64_t txhsxvtune : 2;
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uint64_t sqrxtune : 3;
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uint64_t compdistune : 3;
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uint64_t otgtune : 3;
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uint64_t otgdisable : 1;
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uint64_t portreset : 1;
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uint64_t drvvbus : 1;
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uint64_t lsbist : 1;
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uint64_t fsbist : 1;
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uint64_t hsbist : 1;
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uint64_t bist_done : 1;
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uint64_t bist_err : 1;
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uint64_t tdata_out : 4;
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uint64_t siddq : 1;
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uint64_t txpreemphasistune : 1;
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uint64_t dma_bmode : 1;
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uint64_t usbc_end : 1;
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uint64_t usbp_bist : 1;
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uint64_t tclk : 1;
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uint64_t dp_pulld : 1;
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uint64_t dm_pulld : 1;
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uint64_t hst_mode : 1;
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uint64_t tuning : 4;
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uint64_t tx_bs_enh : 1;
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uint64_t tx_bs_en : 1;
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uint64_t loop_enb : 1;
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uint64_t vtest_enb : 1;
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uint64_t bist_enb : 1;
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uint64_t tdata_sel : 1;
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uint64_t taddr_in : 4;
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uint64_t tdata_in : 8;
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uint64_t ate_reset : 1;
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} s;
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};
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#endif
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@ -66,8 +66,7 @@
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#include <asm/octeon/cvmx-sysinfo.h>
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#include <asm/octeon/cvmx-helper-board.h>
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#include "cvmx-usbcx-defs.h"
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#include "cvmx-usbnx-defs.h"
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#include "octeon-hcd.h"
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/**
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* enum cvmx_usb_speed - the possible USB device speeds
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@ -1,7 +1,14 @@
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/***********************license start***************
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||||
* Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
|
||||
* reserved.
|
||||
/*
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||||
* Octeon HCD hardware register definitions.
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*
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* This file is subject to the terms and conditions of the GNU General Public
|
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* License. See the file "COPYING" in the main directory of this archive
|
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* for more details.
|
||||
*
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* Some parts of the code were originally released under BSD license:
|
||||
*
|
||||
* Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
|
||||
* reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
@ -14,17 +21,17 @@
|
||||
* copyright notice, this list of conditions and the following
|
||||
* disclaimer in the documentation and/or other materials provided
|
||||
* with the distribution.
|
||||
|
||||
*
|
||||
* * Neither the name of Cavium Networks nor the names of
|
||||
* its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written
|
||||
* permission.
|
||||
|
||||
*
|
||||
* This Software, including technical data, may be subject to U.S. export
|
||||
* control laws, including the U.S. Export Administration Act and its associated
|
||||
* regulations, and may be subject to export or import regulations in other
|
||||
* regulations, and may be subject to export or import regulations in other
|
||||
* countries.
|
||||
|
||||
*
|
||||
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
|
||||
* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
|
||||
* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
|
||||
@ -33,20 +40,12 @@
|
||||
* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
|
||||
* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
|
||||
* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
|
||||
* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
|
||||
* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
|
||||
***********************license end**************************************/
|
||||
|
||||
|
||||
/**
|
||||
* cvmx-usbcx-defs.h
|
||||
*
|
||||
* Configuration and status register (CSR) type definitions for
|
||||
* Octeon usbcx.
|
||||
*
|
||||
*/
|
||||
#ifndef __CVMX_USBCX_TYPEDEFS_H__
|
||||
#define __CVMX_USBCX_TYPEDEFS_H__
|
||||
|
||||
#ifndef __OCTEON_HCD_H__
|
||||
#define __OCTEON_HCD_H__
|
||||
|
||||
#define CVMX_USBCXBASE 0x00016F0010000000ull
|
||||
#define CVMX_USBCXREG1(reg, bid) \
|
||||
@ -81,6 +80,19 @@
|
||||
#define CVMX_USBCX_HPTXFSIZ(bid) CVMX_USBCXREG1(0x100, bid)
|
||||
#define CVMX_USBCX_HPTXSTS(bid) CVMX_USBCXREG1(0x410, bid)
|
||||
|
||||
#define CVMX_USBNXBID1(bid) (((bid) & 1) * 0x10000000ull)
|
||||
#define CVMX_USBNXBID2(bid) (((bid) & 1) * 0x100000000000ull)
|
||||
|
||||
#define CVMX_USBNXREG1(reg, bid) \
|
||||
(CVMX_ADD_IO_SEG(0x0001180068000000ull | reg) + CVMX_USBNXBID1(bid))
|
||||
#define CVMX_USBNXREG2(reg, bid) \
|
||||
(CVMX_ADD_IO_SEG(0x00016F0000000000ull | reg) + CVMX_USBNXBID2(bid))
|
||||
|
||||
#define CVMX_USBNX_CLK_CTL(bid) CVMX_USBNXREG1(0x10, bid)
|
||||
#define CVMX_USBNX_DMA0_INB_CHN0(bid) CVMX_USBNXREG2(0x818, bid)
|
||||
#define CVMX_USBNX_DMA0_OUTB_CHN0(bid) CVMX_USBNXREG2(0x858, bid)
|
||||
#define CVMX_USBNX_USBP_CTL_STATUS(bid) CVMX_USBNXREG1(0x18, bid)
|
||||
|
||||
/**
|
||||
* cvmx_usbc#_gahbcfg
|
||||
*
|
||||
@ -1525,4 +1537,283 @@ union cvmx_usbcx_hptxsts {
|
||||
} s;
|
||||
};
|
||||
|
||||
#endif
|
||||
/**
|
||||
* cvmx_usbn#_clk_ctl
|
||||
*
|
||||
* USBN_CLK_CTL = USBN's Clock Control
|
||||
*
|
||||
* This register is used to control the frequency of the hclk and the
|
||||
* hreset and phy_rst signals.
|
||||
*/
|
||||
union cvmx_usbnx_clk_ctl {
|
||||
uint64_t u64;
|
||||
/**
|
||||
* struct cvmx_usbnx_clk_ctl_s
|
||||
* @divide2: The 'hclk' used by the USB subsystem is derived
|
||||
* from the eclk.
|
||||
* Also see the field DIVIDE. DIVIDE2<1> must currently
|
||||
* be zero because it is not implemented, so the maximum
|
||||
* ratio of eclk/hclk is currently 16.
|
||||
* The actual divide number for hclk is:
|
||||
* (DIVIDE2 + 1) * (DIVIDE + 1)
|
||||
* @hclk_rst: When this field is '0' the HCLK-DIVIDER used to
|
||||
* generate the hclk in the USB Subsystem is held
|
||||
* in reset. This bit must be set to '0' before
|
||||
* changing the value os DIVIDE in this register.
|
||||
* The reset to the HCLK_DIVIDERis also asserted
|
||||
* when core reset is asserted.
|
||||
* @p_x_on: Force USB-PHY on during suspend.
|
||||
* '1' USB-PHY XO block is powered-down during
|
||||
* suspend.
|
||||
* '0' USB-PHY XO block is powered-up during
|
||||
* suspend.
|
||||
* The value of this field must be set while POR is
|
||||
* active.
|
||||
* @p_rtype: PHY reference clock type
|
||||
* On CN50XX/CN52XX/CN56XX the values are:
|
||||
* '0' The USB-PHY uses a 12MHz crystal as a clock source
|
||||
* at the USB_XO and USB_XI pins.
|
||||
* '1' Reserved.
|
||||
* '2' The USB_PHY uses 12/24/48MHz 2.5V board clock at the
|
||||
* USB_XO pin. USB_XI should be tied to ground in this
|
||||
* case.
|
||||
* '3' Reserved.
|
||||
* On CN3xxx bits 14 and 15 are p_xenbn and p_rclk and values are:
|
||||
* '0' Reserved.
|
||||
* '1' Reserved.
|
||||
* '2' The PHY PLL uses the XO block output as a reference.
|
||||
* The XO block uses an external clock supplied on the
|
||||
* XO pin. USB_XI should be tied to ground for this
|
||||
* usage.
|
||||
* '3' The XO block uses the clock from a crystal.
|
||||
* @p_com_on: '0' Force USB-PHY XO Bias, Bandgap and PLL to
|
||||
* remain powered in Suspend Mode.
|
||||
* '1' The USB-PHY XO Bias, Bandgap and PLL are
|
||||
* powered down in suspend mode.
|
||||
* The value of this field must be set while POR is
|
||||
* active.
|
||||
* @p_c_sel: Phy clock speed select.
|
||||
* Selects the reference clock / crystal frequency.
|
||||
* '11': Reserved
|
||||
* '10': 48 MHz (reserved when a crystal is used)
|
||||
* '01': 24 MHz (reserved when a crystal is used)
|
||||
* '00': 12 MHz
|
||||
* The value of this field must be set while POR is
|
||||
* active.
|
||||
* NOTE: if a crystal is used as a reference clock,
|
||||
* this field must be set to 12 MHz.
|
||||
* @cdiv_byp: Used to enable the bypass input to the USB_CLK_DIV.
|
||||
* @sd_mode: Scaledown mode for the USBC. Control timing events
|
||||
* in the USBC, for normal operation this must be '0'.
|
||||
* @s_bist: Starts bist on the hclk memories, during the '0'
|
||||
* to '1' transition.
|
||||
* @por: Power On Reset for the PHY.
|
||||
* Resets all the PHYS registers and state machines.
|
||||
* @enable: When '1' allows the generation of the hclk. When
|
||||
* '0' the hclk will not be generated. SEE DIVIDE
|
||||
* field of this register.
|
||||
* @prst: When this field is '0' the reset associated with
|
||||
* the phy_clk functionality in the USB Subsystem is
|
||||
* help in reset. This bit should not be set to '1'
|
||||
* until the time it takes 6 clocks (hclk or phy_clk,
|
||||
* whichever is slower) has passed. Under normal
|
||||
* operation once this bit is set to '1' it should not
|
||||
* be set to '0'.
|
||||
* @hrst: When this field is '0' the reset associated with
|
||||
* the hclk functioanlity in the USB Subsystem is
|
||||
* held in reset.This bit should not be set to '1'
|
||||
* until 12ms after phy_clk is stable. Under normal
|
||||
* operation, once this bit is set to '1' it should
|
||||
* not be set to '0'.
|
||||
* @divide: The frequency of 'hclk' used by the USB subsystem
|
||||
* is the eclk frequency divided by the value of
|
||||
* (DIVIDE2 + 1) * (DIVIDE + 1), also see the field
|
||||
* DIVIDE2 of this register.
|
||||
* The hclk frequency should be less than 125Mhz.
|
||||
* After writing a value to this field the SW should
|
||||
* read the field for the value written.
|
||||
* The ENABLE field of this register should not be set
|
||||
* until AFTER this field is set and then read.
|
||||
*/
|
||||
struct cvmx_usbnx_clk_ctl_s {
|
||||
uint64_t reserved_20_63 : 44;
|
||||
uint64_t divide2 : 2;
|
||||
uint64_t hclk_rst : 1;
|
||||
uint64_t p_x_on : 1;
|
||||
uint64_t p_rtype : 2;
|
||||
uint64_t p_com_on : 1;
|
||||
uint64_t p_c_sel : 2;
|
||||
uint64_t cdiv_byp : 1;
|
||||
uint64_t sd_mode : 2;
|
||||
uint64_t s_bist : 1;
|
||||
uint64_t por : 1;
|
||||
uint64_t enable : 1;
|
||||
uint64_t prst : 1;
|
||||
uint64_t hrst : 1;
|
||||
uint64_t divide : 3;
|
||||
} s;
|
||||
};
|
||||
|
||||
/**
|
||||
* cvmx_usbn#_usbp_ctl_status
|
||||
*
|
||||
* USBN_USBP_CTL_STATUS = USBP Control And Status Register
|
||||
*
|
||||
* Contains general control and status information for the USBN block.
|
||||
*/
|
||||
union cvmx_usbnx_usbp_ctl_status {
|
||||
uint64_t u64;
|
||||
/**
|
||||
* struct cvmx_usbnx_usbp_ctl_status_s
|
||||
* @txrisetune: HS Transmitter Rise/Fall Time Adjustment
|
||||
* @txvreftune: HS DC Voltage Level Adjustment
|
||||
* @txfslstune: FS/LS Source Impedence Adjustment
|
||||
* @txhsxvtune: Transmitter High-Speed Crossover Adjustment
|
||||
* @sqrxtune: Squelch Threshold Adjustment
|
||||
* @compdistune: Disconnect Threshold Adjustment
|
||||
* @otgtune: VBUS Valid Threshold Adjustment
|
||||
* @otgdisable: OTG Block Disable
|
||||
* @portreset: Per_Port Reset
|
||||
* @drvvbus: Drive VBUS
|
||||
* @lsbist: Low-Speed BIST Enable.
|
||||
* @fsbist: Full-Speed BIST Enable.
|
||||
* @hsbist: High-Speed BIST Enable.
|
||||
* @bist_done: PHY Bist Done.
|
||||
* Asserted at the end of the PHY BIST sequence.
|
||||
* @bist_err: PHY Bist Error.
|
||||
* Indicates an internal error was detected during
|
||||
* the BIST sequence.
|
||||
* @tdata_out: PHY Test Data Out.
|
||||
* Presents either internaly generated signals or
|
||||
* test register contents, based upon the value of
|
||||
* test_data_out_sel.
|
||||
* @siddq: Drives the USBP (USB-PHY) SIDDQ input.
|
||||
* Normally should be set to zero.
|
||||
* When customers have no intent to use USB PHY
|
||||
* interface, they should:
|
||||
* - still provide 3.3V to USB_VDD33, and
|
||||
* - tie USB_REXT to 3.3V supply, and
|
||||
* - set USBN*_USBP_CTL_STATUS[SIDDQ]=1
|
||||
* @txpreemphasistune: HS Transmitter Pre-Emphasis Enable
|
||||
* @dma_bmode: When set to 1 the L2C DMA address will be updated
|
||||
* with byte-counts between packets. When set to 0
|
||||
* the L2C DMA address is incremented to the next
|
||||
* 4-byte aligned address after adding byte-count.
|
||||
* @usbc_end: Bigendian input to the USB Core. This should be
|
||||
* set to '0' for operation.
|
||||
* @usbp_bist: PHY, This is cleared '0' to run BIST on the USBP.
|
||||
* @tclk: PHY Test Clock, used to load TDATA_IN to the USBP.
|
||||
* @dp_pulld: PHY DP_PULLDOWN input to the USB-PHY.
|
||||
* This signal enables the pull-down resistance on
|
||||
* the D+ line. '1' pull down-resistance is connected
|
||||
* to D+/ '0' pull down resistance is not connected
|
||||
* to D+. When an A/B device is acting as a host
|
||||
* (downstream-facing port), dp_pulldown and
|
||||
* dm_pulldown are enabled. This must not toggle
|
||||
* during normal opeartion.
|
||||
* @dm_pulld: PHY DM_PULLDOWN input to the USB-PHY.
|
||||
* This signal enables the pull-down resistance on
|
||||
* the D- line. '1' pull down-resistance is connected
|
||||
* to D-. '0' pull down resistance is not connected
|
||||
* to D-. When an A/B device is acting as a host
|
||||
* (downstream-facing port), dp_pulldown and
|
||||
* dm_pulldown are enabled. This must not toggle
|
||||
* during normal opeartion.
|
||||
* @hst_mode: When '0' the USB is acting as HOST, when '1'
|
||||
* USB is acting as device. This field needs to be
|
||||
* set while the USB is in reset.
|
||||
* @tuning: Transmitter Tuning for High-Speed Operation.
|
||||
* Tunes the current supply and rise/fall output
|
||||
* times for high-speed operation.
|
||||
* [20:19] == 11: Current supply increased
|
||||
* approximately 9%
|
||||
* [20:19] == 10: Current supply increased
|
||||
* approximately 4.5%
|
||||
* [20:19] == 01: Design default.
|
||||
* [20:19] == 00: Current supply decreased
|
||||
* approximately 4.5%
|
||||
* [22:21] == 11: Rise and fall times are increased.
|
||||
* [22:21] == 10: Design default.
|
||||
* [22:21] == 01: Rise and fall times are decreased.
|
||||
* [22:21] == 00: Rise and fall times are decreased
|
||||
* further as compared to the 01 setting.
|
||||
* @tx_bs_enh: Transmit Bit Stuffing on [15:8].
|
||||
* Enables or disables bit stuffing on data[15:8]
|
||||
* when bit-stuffing is enabled.
|
||||
* @tx_bs_en: Transmit Bit Stuffing on [7:0].
|
||||
* Enables or disables bit stuffing on data[7:0]
|
||||
* when bit-stuffing is enabled.
|
||||
* @loop_enb: PHY Loopback Test Enable.
|
||||
* '1': During data transmission the receive is
|
||||
* enabled.
|
||||
* '0': During data transmission the receive is
|
||||
* disabled.
|
||||
* Must be '0' for normal operation.
|
||||
* @vtest_enb: Analog Test Pin Enable.
|
||||
* '1' The PHY's analog_test pin is enabled for the
|
||||
* input and output of applicable analog test signals.
|
||||
* '0' THe analog_test pin is disabled.
|
||||
* @bist_enb: Built-In Self Test Enable.
|
||||
* Used to activate BIST in the PHY.
|
||||
* @tdata_sel: Test Data Out Select.
|
||||
* '1' test_data_out[3:0] (PHY) register contents
|
||||
* are output. '0' internaly generated signals are
|
||||
* output.
|
||||
* @taddr_in: Mode Address for Test Interface.
|
||||
* Specifies the register address for writing to or
|
||||
* reading from the PHY test interface register.
|
||||
* @tdata_in: Internal Testing Register Input Data and Select
|
||||
* This is a test bus. Data is present on [3:0],
|
||||
* and its corresponding select (enable) is present
|
||||
* on bits [7:4].
|
||||
* @ate_reset: Reset input from automatic test equipment.
|
||||
* This is a test signal. When the USB Core is
|
||||
* powered up (not in Susned Mode), an automatic
|
||||
* tester can use this to disable phy_clock and
|
||||
* free_clk, then re-eanable them with an aligned
|
||||
* phase.
|
||||
* '1': The phy_clk and free_clk outputs are
|
||||
* disabled. "0": The phy_clock and free_clk outputs
|
||||
* are available within a specific period after the
|
||||
* de-assertion.
|
||||
*/
|
||||
struct cvmx_usbnx_usbp_ctl_status_s {
|
||||
uint64_t txrisetune : 1;
|
||||
uint64_t txvreftune : 4;
|
||||
uint64_t txfslstune : 4;
|
||||
uint64_t txhsxvtune : 2;
|
||||
uint64_t sqrxtune : 3;
|
||||
uint64_t compdistune : 3;
|
||||
uint64_t otgtune : 3;
|
||||
uint64_t otgdisable : 1;
|
||||
uint64_t portreset : 1;
|
||||
uint64_t drvvbus : 1;
|
||||
uint64_t lsbist : 1;
|
||||
uint64_t fsbist : 1;
|
||||
uint64_t hsbist : 1;
|
||||
uint64_t bist_done : 1;
|
||||
uint64_t bist_err : 1;
|
||||
uint64_t tdata_out : 4;
|
||||
uint64_t siddq : 1;
|
||||
uint64_t txpreemphasistune : 1;
|
||||
uint64_t dma_bmode : 1;
|
||||
uint64_t usbc_end : 1;
|
||||
uint64_t usbp_bist : 1;
|
||||
uint64_t tclk : 1;
|
||||
uint64_t dp_pulld : 1;
|
||||
uint64_t dm_pulld : 1;
|
||||
uint64_t hst_mode : 1;
|
||||
uint64_t tuning : 4;
|
||||
uint64_t tx_bs_enh : 1;
|
||||
uint64_t tx_bs_en : 1;
|
||||
uint64_t loop_enb : 1;
|
||||
uint64_t vtest_enb : 1;
|
||||
uint64_t bist_enb : 1;
|
||||
uint64_t tdata_sel : 1;
|
||||
uint64_t taddr_in : 4;
|
||||
uint64_t tdata_in : 8;
|
||||
uint64_t ate_reset : 1;
|
||||
} s;
|
||||
};
|
||||
|
||||
#endif /* __OCTEON_HCD_H__ */
|
||||
Loading…
Reference in New Issue
Block a user