forked from Minki/linux
MIPS: only register FTLBPar exception handler for supported models
Previously ExcCode 16 is unconditionally treated as the FTLB parity
exception (FTLBPar), but in fact its semantic is implementation-
dependent. Looking at various manuals it seems the FTLBPar exception is
only present on some recent MIPS Technologies cores, so only register
the handler on these.
Fixes: 75b5b5e0a2
("MIPS: Add support for FTLBs")
Reviewed-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: WANG Xuerui <git@xen0n.name>
Cc: Paul Burton <paulburton@kernel.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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@ -568,6 +568,10 @@
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# define cpu_has_mac2008_only __opt(MIPS_CPU_MAC_2008_ONLY)
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# define cpu_has_mac2008_only __opt(MIPS_CPU_MAC_2008_ONLY)
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#endif
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#endif
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#ifndef cpu_has_ftlbparex
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# define cpu_has_ftlbparex __opt(MIPS_CPU_FTLBPAREX)
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#endif
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#ifdef CONFIG_SMP
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#ifdef CONFIG_SMP
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/*
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/*
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* Some systems share FTLB RAMs between threads within a core (siblings in
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* Some systems share FTLB RAMs between threads within a core (siblings in
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@ -427,6 +427,7 @@ enum cpu_type_enum {
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#define MIPS_CPU_MM_SYSAD BIT_ULL(58) /* CPU supports write-through SysAD Valid merge */
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#define MIPS_CPU_MM_SYSAD BIT_ULL(58) /* CPU supports write-through SysAD Valid merge */
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#define MIPS_CPU_MM_FULL BIT_ULL(59) /* CPU supports write-through full merge */
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#define MIPS_CPU_MM_FULL BIT_ULL(59) /* CPU supports write-through full merge */
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#define MIPS_CPU_MAC_2008_ONLY BIT_ULL(60) /* CPU Only support MAC2008 Fused multiply-add instruction */
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#define MIPS_CPU_MAC_2008_ONLY BIT_ULL(60) /* CPU Only support MAC2008 Fused multiply-add instruction */
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#define MIPS_CPU_FTLBPAREX BIT_ULL(61) /* CPU has FTLB parity exception */
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/*
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/*
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* CPU ASE encodings
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* CPU ASE encodings
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@ -1827,6 +1827,19 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
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default:
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default:
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break;
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break;
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}
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}
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/* Recent MIPS cores use the implementation-dependent ExcCode 16 for
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* cache/FTLB parity exceptions.
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*/
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switch (__get_cpu_type(c->cputype)) {
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case CPU_PROAPTIV:
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case CPU_P5600:
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case CPU_P6600:
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case CPU_I6400:
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case CPU_I6500:
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c->options |= MIPS_CPU_FTLBPAREX;
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break;
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}
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}
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}
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static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
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static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
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@ -2454,6 +2454,7 @@ void __init trap_init(void)
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if (cpu_has_fpu && !cpu_has_nofpuex)
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if (cpu_has_fpu && !cpu_has_nofpuex)
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set_except_vector(EXCCODE_FPE, handle_fpe);
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set_except_vector(EXCCODE_FPE, handle_fpe);
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if (cpu_has_ftlbparex)
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set_except_vector(MIPS_EXCCODE_TLBPAR, handle_ftlb);
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set_except_vector(MIPS_EXCCODE_TLBPAR, handle_ftlb);
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if (cpu_has_rixiex) {
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if (cpu_has_rixiex) {
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