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drm/amdgpu: add the trailing fence per ring

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The trailing fence for ring is used to track the
completion of preemption.

Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jack Xiao 2019-01-10 14:28:08 +08:00 committed by Alex Deucher
parent dfc9847956
commit ef3e13238b
3 changed files with 27 additions and 5 deletions
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18
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
View File

@ -707,22 +707,30 @@ static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data)
amdgpu_fence_process(ring);
seq_printf(m, "--- ring %d (%s) ---\n", i, ring->name);
seq_printf(m, "Last signaled fence 0x%08x\n",
seq_printf(m, "Last signaled fence 0x%08x\n",
atomic_read(&ring->fence_drv.last_seq));
seq_printf(m, "Last emitted 0x%08x\n",
seq_printf(m, "Last emitted 0x%08x\n",
ring->fence_drv.sync_seq);
if (ring->funcs->type == AMDGPU_RING_TYPE_GFX ||
ring->funcs->type == AMDGPU_RING_TYPE_SDMA) {
seq_printf(m, "Last signaled trailing fence 0x%08x\n",
le32_to_cpu(*ring->trail_fence_cpu_addr));
seq_printf(m, "Last emitted 0x%08x\n",
ring->trail_seq);
}
if (ring->funcs->type != AMDGPU_RING_TYPE_GFX)
continue;
/* set in CP_VMID_PREEMPT and preemption occurred */
seq_printf(m, "Last preempted 0x%08x\n",
seq_printf(m, "Last preempted 0x%08x\n",
le32_to_cpu(*(ring->fence_drv.cpu_addr + 2)));
/* set in CP_VMID_RESET and reset occurred */
seq_printf(m, "Last reset 0x%08x\n",
seq_printf(m, "Last reset 0x%08x\n",
le32_to_cpu(*(ring->fence_drv.cpu_addr + 4)));
/* Both preemption and reset occurred */
seq_printf(m, "Last both 0x%08x\n",
seq_printf(m, "Last both 0x%08x\n",
le32_to_cpu(*(ring->fence_drv.cpu_addr + 6)));
}
return 0;

10
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
View File

@ -281,6 +281,16 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
return r;
}
r = amdgpu_device_wb_get(adev, &ring->trail_fence_offs);
if (r) {
dev_err(adev->dev,
"(%d) ring trail_fence_offs wb alloc failed\n", r);
return r;
}
ring->trail_fence_gpu_addr =
adev->wb.gpu_addr + (ring->trail_fence_offs * 4);
ring->trail_fence_cpu_addr = &adev->wb.wb[ring->trail_fence_offs];
r = amdgpu_device_wb_get(adev, &ring->cond_exe_offs);
if (r) {
dev_err(adev->dev, "(%d) ring cond_exec_polling wb alloc failed\n", r);

4
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
View File

@ -206,6 +206,10 @@ struct amdgpu_ring {
unsigned fence_offs;
uint64_t current_ctx;
char name[16];
u32 trail_seq;
unsigned trail_fence_offs;
u64 trail_fence_gpu_addr;
volatile u32 *trail_fence_cpu_addr;
unsigned cond_exe_offs;
u64 cond_exe_gpu_addr;
volatile u32 *cond_exe_cpu_addr;