Allwinner clock changes for 4.16, part 2
The hardware description for the DE2 clocks on the A64 and H5 SoCs is fixed, and support for these clocks on the H3 is added. Also, the description for the TCON1 clock on the A83T is fixed. All these are non-critical, as they have no users. -----BEGIN PGP SIGNATURE----- iQJCBAABCgAsFiEE2nN1m/hhnkhOWjtHOJpUIZwPJDAFAlpS6O4OHHdlbnNAY3Np ZS5vcmcACgkQOJpUIZwPJDB+exAAnM/bWFyjJTdSEkKu3y1R9O1kCJ9IccCg8Y+k WN0/rl3Afh40lr6hwa3rS4DqROtjyMSU421nJIlnU6MyBLkNokCJvnibKbltoFNY QXg96QfSoD0ThdEOkro4nt0y4FdLZ31YQ3DFqhs6X0uxgMOUQUrcs+0a1m28zVj6 zCXcf4GT3DodrhyF5StqBnR3znNY/NxlBYomPfv8MSD5mG1Zqi1So1FwTaqiyF5d oIxwSg+tBltrXloV1fJmgWFkM18WRQvoAEkEWRxwILKrmzLr2m/XI91M+xcRkjym X++CLIEhK2dsVu2jOLwFv6/51fkaWI8FjU+0ZNrZR/rdpBMvCCPgyjcqnxtMiTv/ F4j5NWME5C3vtsAjHxdJEK10zC/CmG+0G7exP4k6Gf/Ril4otE5nJBfnrXwmAPvy 3hv8R7eTngaxU/RQhiH920W1hfCDfaEILsDEXiWTgiLfN7jHv41Z9K9Di/9UCuUc rZ5fsAvRr/+AKnx/fXIWEz4LrieXIgPHYcq9Gd8I8S718tog9nPSXot7sMYQSGVy RXAW7CuMSm82glnTlwrH8cV/MmBoAHUuOsTktacfPHxNruyz5JOo1JNb95lj7B1F A9Uk6dYs2MYxNI4wSWjRB7G/hQMXaTYLd+wvLbqtObkg+d+/w0vM0Vx6vFGumTHv YMVu+4w= =bN56 -----END PGP SIGNATURE----- Merge tag 'sunxi-clk-for-4.16-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner Pull Allwinner clock changes from Chen-Yu Tsai: - Fix hardware description for the DE2 clocks on the A64 and H5 SoCs - Support DE2 clocks on the H3 - Fix description for the TCON1 clock on A83T All these are non-critical, as they have no users. * tag 'sunxi-clk-for-4.16-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: a83t: Add M divider to TCON1 clock clk: sunxi-ng: fix the A64/H5 clock description of DE2 CCU clk: sunxi-ng: add support for Allwinner H3 DE2 CCU dt-bindings: fix the binding of Allwinner DE2 CCU of A83T and H3
This commit is contained in:
Stephen Boyd
commit
ef0e5f382f
@ -4,13 +4,14 @@ Allwinner Display Engine 2.0 Clock Control Binding
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Required properties :
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- compatible: must contain one of the following compatibles:
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- "allwinner,sun8i-a83t-de2-clk"
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- "allwinner,sun8i-h3-de2-clk"
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- "allwinner,sun8i-v3s-de2-clk"
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- "allwinner,sun50i-h5-de2-clk"
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- reg: Must contain the registers base address and length
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- clocks: phandle to the clocks feeding the display engine subsystem.
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Three are needed:
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- "mod": the display engine module clock
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- "mod": the display engine module clock (on A83T it's the DE PLL)
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- "bus": the bus clock for the whole display engine subsystem
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- clock-names: Must contain the clock names described just above
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- resets: phandle to the reset control for the display engine subsystem.
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@ -19,7 +20,7 @@ Required properties :
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Example:
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de2_clocks: clock@1000000 {
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compatible = "allwinner,sun8i-a83t-de2-clk";
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compatible = "allwinner,sun8i-h3-de2-clk";
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reg = <0x01000000 0x100000>;
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clocks = <&ccu CLK_BUS_DE>,
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<&ccu CLK_DE>;
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@ -504,8 +504,8 @@ static SUNXI_CCU_MUX_WITH_GATE(tcon0_clk, "tcon0", tcon0_parents,
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0x118, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
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static const char * const tcon1_parents[] = { "pll-video1" };
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static SUNXI_CCU_MUX_WITH_GATE(tcon1_clk, "tcon1", tcon1_parents,
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0x11c, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
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static SUNXI_CCU_M_WITH_MUX_GATE(tcon1_clk, "tcon1", tcon1_parents,
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0x11c, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
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static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M", 0x130, BIT(16), 0);
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@ -41,6 +41,8 @@ static SUNXI_CCU_GATE(wb_clk, "wb", "wb-div",
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static SUNXI_CCU_M(mixer0_div_clk, "mixer0-div", "de", 0x0c, 0, 4,
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CLK_SET_RATE_PARENT);
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static SUNXI_CCU_M(mixer1_div_clk, "mixer1-div", "de", 0x0c, 4, 4,
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CLK_SET_RATE_PARENT);
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static SUNXI_CCU_M(wb_div_clk, "wb-div", "de", 0x0c, 8, 4,
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CLK_SET_RATE_PARENT);
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@ -65,6 +67,20 @@ static struct ccu_common *sun8i_a83t_de2_clks[] = {
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&wb_div_a83_clk.common,
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};
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static struct ccu_common *sun8i_h3_de2_clks[] = {
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&mixer0_clk.common,
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&mixer1_clk.common,
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&wb_clk.common,
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&bus_mixer0_clk.common,
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&bus_mixer1_clk.common,
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&bus_wb_clk.common,
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&mixer0_div_clk.common,
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&mixer1_div_clk.common,
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&wb_div_clk.common,
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};
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static struct ccu_common *sun8i_v3s_de2_clks[] = {
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&mixer0_clk.common,
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&wb_clk.common,
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@ -93,6 +109,23 @@ static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks = {
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.num = CLK_NUMBER,
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};
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static struct clk_hw_onecell_data sun8i_h3_de2_hw_clks = {
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.hws = {
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[CLK_MIXER0] = &mixer0_clk.common.hw,
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[CLK_MIXER1] = &mixer1_clk.common.hw,
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[CLK_WB] = &wb_clk.common.hw,
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[CLK_BUS_MIXER0] = &bus_mixer0_clk.common.hw,
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[CLK_BUS_MIXER1] = &bus_mixer1_clk.common.hw,
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[CLK_BUS_WB] = &bus_wb_clk.common.hw,
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[CLK_MIXER0_DIV] = &mixer0_div_clk.common.hw,
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[CLK_MIXER1_DIV] = &mixer1_div_clk.common.hw,
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[CLK_WB_DIV] = &wb_div_clk.common.hw,
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},
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.num = CLK_NUMBER,
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};
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static struct clk_hw_onecell_data sun8i_v3s_de2_hw_clks = {
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.hws = {
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[CLK_MIXER0] = &mixer0_clk.common.hw,
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@ -133,11 +166,21 @@ static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc = {
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.num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets),
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};
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static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = {
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.ccu_clks = sun8i_a83t_de2_clks,
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.num_ccu_clks = ARRAY_SIZE(sun8i_a83t_de2_clks),
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static const struct sunxi_ccu_desc sun8i_h3_de2_clk_desc = {
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.ccu_clks = sun8i_h3_de2_clks,
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.num_ccu_clks = ARRAY_SIZE(sun8i_h3_de2_clks),
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.hw_clks = &sun8i_a83t_de2_hw_clks,
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.hw_clks = &sun8i_h3_de2_hw_clks,
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.resets = sun8i_a83t_de2_resets,
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.num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets),
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};
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static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = {
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.ccu_clks = sun8i_h3_de2_clks,
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.num_ccu_clks = ARRAY_SIZE(sun8i_h3_de2_clks),
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.hw_clks = &sun8i_h3_de2_hw_clks,
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.resets = sun50i_a64_de2_resets,
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.num_resets = ARRAY_SIZE(sun50i_a64_de2_resets),
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@ -237,6 +280,10 @@ static const struct of_device_id sunxi_de2_clk_ids[] = {
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.compatible = "allwinner,sun8i-a83t-de2-clk",
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.data = &sun8i_a83t_de2_clk_desc,
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},
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{
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.compatible = "allwinner,sun8i-h3-de2-clk",
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.data = &sun8i_h3_de2_clk_desc,
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},
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{
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.compatible = "allwinner,sun8i-v3s-de2-clk",
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.data = &sun8i_v3s_de2_clk_desc,
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