drm/amd/display: Add w/a to reset PHY before link training in verify_link_cap
[Why] PHY will sometimes be in bad state on hotplugging display from USB-C dongle. [How] Add additional calls to disable and then enable PHY before link training starts during verify_link_cap. Signed-off-by: George Shen <george.shen@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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5adc673c77
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drivers/gpu/drm/amd/display/dc
@ -1892,6 +1892,16 @@ bool dp_verify_link_cap(
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/* disable PHY done possible by BIOS, will be done by driver itself */
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dp_disable_link_phy(link, link->connector_signal);
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/* Temporary Renoir-specific workaround for SWDEV-215184;
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* PHY will sometimes be in bad state on hotplugging display from certain USB-C dongle,
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* so add extra cycle of enabling and disabling the PHY before first link training.
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*/
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if (link->link_enc->features.flags.bits.DP_IS_USB_C &&
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link->dc->debug.usbc_combo_phy_reset_wa) {
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dp_enable_link_phy(link, link->connector_signal, dp_cs_id, cur);
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dp_disable_link_phy(link, link->connector_signal);
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}
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dp_cs_id = get_clock_source_id(link);
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/* link training starts with the maximum common settings
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@ -421,6 +421,7 @@ struct dc_debug_options {
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bool disable_dram_clock_change_vactive_support;
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bool validate_dml_output;
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bool enable_dmcub_surface_flip;
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bool usbc_combo_phy_reset_wa;
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};
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struct dc_debug_data {
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@ -835,7 +835,8 @@ static const struct dc_debug_options debug_defaults_drv = {
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.scl_reset_length10 = true,
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.sanity_checks = true,
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.disable_48mhz_pwrdwn = false,
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.nv12_iflip_vm_wa = true
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.nv12_iflip_vm_wa = true,
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.usbc_combo_phy_reset_wa = true
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};
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static const struct dc_debug_options debug_defaults_diags = {
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