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ARM: dts: dra7 clock data

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This patch creates a unique node for each clock in the DRA7 power,
reset and clock manager (PRCM).

TODO: apll_pcie clock node is still a dummy in this version, and
proper support for the APLL should be added.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Tero Kristo 2013-07-18 17:18:33 +03:00 committed by Mike Turquette
parent 85dc74e9bd
commit ee6c750761
2 changed files with 2026 additions and 0 deletions
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41
arch/arm/boot/dts/dra7.dtsi
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@ -104,6 +104,45 @@
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
prm: prm@4ae06000 {
compatible = "ti,dra7-prm";
reg = <0x4ae06000 0x3000>;
prm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
prm_clockdomains: clockdomains {
};
};
cm_core_aon: cm_core_aon@4a005000 {
compatible = "ti,dra7-cm-core-aon";
reg = <0x4a005000 0x2000>;
cm_core_aon_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
cm_core_aon_clockdomains: clockdomains {
};
};
cm_core: cm_core@4a008000 {
compatible = "ti,dra7-cm-core";
reg = <0x4a008000 0x3000>;
cm_core_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
cm_core_clockdomains: clockdomains {
};
};
counter32k: counter@4ae04000 { counter32k: counter@4ae04000 {
compatible = "ti,omap-counter32k"; compatible = "ti,omap-counter32k";
reg = <0x4ae04000 0x40>; reg = <0x4ae04000 0x40>;
@ -584,3 +623,5 @@
}; };
}; };
}; };
/include/ "dra7xx-clocks.dtsi"

1985
arch/arm/boot/dts/dra7xx-clocks.dtsi Normal file
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