forked from Minki/linux
Merge branch 'clk-unused' into clk-next
- Remove efm32 clk driver - Remove tango4 clk driver - Remove zte zx clk driver - Remove sirf prima2/atlast clk drivers - Remove u300 clk driver * clk-unused: clk: remove u300 driver clk: remove sirf prima2/atlas drivers clk: remove zte zx driver clk: remove tango4 driver clk: Drop unused efm32gg driver
This commit is contained in:
Stephen Boyd
commit
ee6b84a3fc
@ -1,55 +0,0 @@
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* Clock and reset bindings for CSR atlas7
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Required properties:
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- compatible: Should be "sirf,atlas7-car"
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- reg: Address and length of the register set
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- #clock-cells: Should be <1>
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- #reset-cells: Should be <1>
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell.
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The ID list atlas7_clks defined in drivers/clk/sirf/clk-atlas7.c
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The reset consumer should specify the desired reset by having the reset
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ID in its "reset" phandle cell.
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The ID list atlas7_reset_unit defined in drivers/clk/sirf/clk-atlas7.c
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Examples: Clock and reset controller node:
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car: clock-controller@18620000 {
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compatible = "sirf,atlas7-car";
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reg = <0x18620000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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Examples: Consumers using clock or reset:
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timer@10dc0000 {
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compatible = "sirf,macro-tick";
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reg = <0x10dc0000 0x1000>;
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clocks = <&car 54>;
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interrupts = <0 0 0>,
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<0 1 0>,
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<0 2 0>,
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<0 49 0>,
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<0 50 0>,
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<0 51 0>;
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};
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uart1: uart@18020000 {
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cell-index = <1>;
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compatible = "sirf,macro-uart";
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reg = <0x18020000 0x1000>;
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clocks = <&clks 95>;
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interrupts = <0 18 0>;
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fifosize = <32>;
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};
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vpp@13110000 {
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compatible = "sirf,prima2-vpp";
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reg = <0x13110000 0x10000>;
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interrupts = <0 31 0>;
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clocks = <&car 85>;
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resets = <&car 29>;
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};
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@ -1,73 +0,0 @@
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* Clock bindings for CSR SiRFprimaII
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Required properties:
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- compatible: Should be "sirf,prima2-clkc"
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- reg: Address and length of the register set
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- interrupts: Should contain clock controller interrupt
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- #clock-cells: Should be <1>
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell. The following is a full list of prima2
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clocks and IDs.
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Clock ID
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---------------------------
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rtc 0
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osc 1
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pll1 2
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pll2 3
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pll3 4
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mem 5
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sys 6
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security 7
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dsp 8
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gps 9
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mf 10
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io 11
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cpu 12
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uart0 13
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uart1 14
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uart2 15
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tsc 16
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i2c0 17
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i2c1 18
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spi0 19
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spi1 20
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pwmc 21
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efuse 22
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pulse 23
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dmac0 24
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dmac1 25
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nand 26
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audio 27
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usp0 28
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usp1 29
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usp2 30
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vip 31
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gfx 32
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mm 33
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lcd 34
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vpp 35
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mmc01 36
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mmc23 37
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mmc45 38
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usbpll 39
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usb0 40
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usb1 41
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Examples:
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clks: clock-controller@88000000 {
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compatible = "sirf,prima2-clkc";
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reg = <0x88000000 0x1000>;
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interrupts = <3>;
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#clock-cells = <1>;
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};
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i2c0: i2c@b00e0000 {
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cell-index = <0>;
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compatible = "sirf,prima2-i2c";
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reg = <0xb00e0000 0x10000>;
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interrupts = <24>;
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clocks = <&clks 17>;
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};
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@ -1,80 +0,0 @@
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Clock bindings for ST-Ericsson U300 System Controller Clocks
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Bindings for the gated system controller clocks:
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Required properties:
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- compatible: must be "stericsson,u300-syscon-clk"
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- #clock-cells: must be <0>
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- clock-type: specifies the type of clock:
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0 = slow clock
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1 = fast clock
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2 = rest/remaining clock
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- clock-id: specifies the clock in the type range
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Optional properties:
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- clocks: parent clock(s)
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The available clocks per type are as follows:
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Type: ID: Clock:
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-------------------
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0 0 Slow peripheral bridge clock
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0 1 UART0 clock
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0 4 GPIO clock
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0 6 RTC clock
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0 7 Application timer clock
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0 8 Access timer clock
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1 0 Fast peripheral bridge clock
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1 1 I2C bus 0 clock
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1 2 I2C bus 1 clock
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1 5 MMC interface peripheral (silicon) clock
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1 6 SPI clock
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2 3 CPU clock
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2 4 DMA controller clock
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2 5 External Memory Interface (EMIF) clock
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2 6 NAND flask interface clock
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2 8 XGAM graphics engine clock
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2 9 Shared External Memory Interface (SEMI) clock
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2 10 AHB Subsystem Bridge clock
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2 12 Interrupt controller clock
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Example:
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gpio_clk: gpio_clk@13M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <0>; /* Slow */
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clock-id = <4>;
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clocks = <&slow_clk>;
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};
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gpio: gpio@c0016000 {
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compatible = "stericsson,gpio-coh901";
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(...)
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clocks = <&gpio_clk>;
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};
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Bindings for the MMC/SD card clock:
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Required properties:
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- compatible: must be "stericsson,u300-syscon-mclk"
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- #clock-cells: must be <0>
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Optional properties:
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- clocks: parent clock(s)
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mmc_mclk: mmc_mclk {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-mclk";
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clocks = <&mmc_pclk>;
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};
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mmcsd: mmcsd@c0001000 {
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compatible = "arm,pl18x", "arm,primecell";
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clocks = <&mmc_pclk>, <&mmc_mclk>;
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clock-names = "apb_pclk", "mclk";
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(...)
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};
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@ -1,23 +0,0 @@
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* Sigma Designs Tango4 Clock Generator
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The Tango4 clock generator outputs cpu_clk and sys_clk (the latter is used
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for RAM and various peripheral devices). The clock binding described here
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is applicable to all Tango4 SoCs.
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Required Properties:
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- compatible: should be "sigma,tango4-clkgen".
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- reg: physical base address of the device and length of memory mapped region.
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- clocks: phandle of the input clock (crystal oscillator).
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- clock-output-names: should be "cpuclk" and "sysclk".
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- #clock-cells: should be set to 1.
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Example:
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clkgen: clkgen@10000 {
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compatible = "sigma,tango4-clkgen";
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reg = <0x10000 0x40>;
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clocks = <&xtal>;
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clock-output-names = "cpuclk", "sysclk";
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#clock-cells = <1>;
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};
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@ -1,34 +0,0 @@
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Device Tree Clock bindings for ZTE zx296702
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible : shall be one of the following:
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"zte,zx296702-topcrm-clk":
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zx296702 top clock selection, divider and gating
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"zte,zx296702-lsp0crpm-clk" and
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"zte,zx296702-lsp1crpm-clk":
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zx296702 device level clock selection and gating
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- reg: Address and length of the register set
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell. See include/dt-bindings/clock/zx296702-clock.h
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for the full list of zx296702 clock IDs.
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topclk: topcrm@09800000 {
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compatible = "zte,zx296702-topcrm-clk";
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reg = <0x09800000 0x1000>;
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#clock-cells = <1>;
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};
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uart0: serial@09405000 {
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compatible = "zte,zx296702-uart";
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reg = <0x09405000 0x1000>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&lsp1clk ZX296702_UART0_PCLK>;
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};
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@ -1,37 +0,0 @@
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Device Tree Clock bindings for ZTE zx296718
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible : shall be one of the following:
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"zte,zx296718-topcrm":
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zx296718 top clock selection, divider and gating
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"zte,zx296718-lsp0crm" and
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"zte,zx296718-lsp1crm":
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zx296718 device level clock selection and gating
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"zte,zx296718-audiocrm":
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zx296718 audio clock selection, divider and gating
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- reg: Address and length of the register set
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell. See include/dt-bindings/clock/zx296718-clock.h
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for the full list of zx296718 clock IDs.
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topclk: topcrm@1461000 {
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compatible = "zte,zx296718-topcrm-clk";
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reg = <0x01461000 0x1000>;
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#clock-cells = <1>;
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};
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usbphy0:usb-phy0 {
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compatible = "zte,zx296718-usb-phy";
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#phy-cells = <0>;
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clocks = <&topclk USB20_PHY_CLK>;
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clock-names = "phyclk";
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};
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@ -27,7 +27,6 @@ obj-$(CONFIG_COMMON_CLK_CDCE706) += clk-cdce706.o
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obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o
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obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o
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obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o
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obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o
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obj-$(CONFIG_ARCH_SPARX5) += clk-sparx5.o
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obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o
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obj-$(CONFIG_COMMON_CLK_FSL_FLEXSPI) += clk-fsl-flexspi.o
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@ -63,9 +62,7 @@ obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o
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obj-$(CONFIG_COMMON_CLK_STM32F) += clk-stm32f4.o
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obj-$(CONFIG_COMMON_CLK_STM32H7) += clk-stm32h7.o
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obj-$(CONFIG_COMMON_CLK_STM32MP157) += clk-stm32mp1.o
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obj-$(CONFIG_ARCH_TANGO) += clk-tango4.o
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obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o
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obj-$(CONFIG_ARCH_U300) += clk-u300.o
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obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
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obj-$(CONFIG_COMMON_CLK_VC5) += clk-versaclock5.o
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obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
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@ -105,7 +102,6 @@ obj-y += renesas/
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obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
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obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/
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obj-$(CONFIG_CLK_SIFIVE) += sifive/
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obj-$(CONFIG_ARCH_SIRF) += sirf/
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obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/
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obj-$(CONFIG_ARCH_AGILEX) += socfpga/
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obj-$(CONFIG_ARCH_STRATIX10) += socfpga/
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@ -123,6 +119,5 @@ ifeq ($(CONFIG_COMMON_CLK), y)
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obj-$(CONFIG_X86) += x86/
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endif
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obj-y += xilinx/
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obj-$(CONFIG_ARCH_ZX) += zte/
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obj-$(CONFIG_ARCH_ZYNQ) += zynq/
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obj-$(CONFIG_COMMON_CLK_ZYNQMP) += zynqmp/
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@ -1,84 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2013 Pengutronix
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* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
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||||
*/
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#include <linux/io.h>
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <dt-bindings/clock/efm32-cmu.h>
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#define CMU_HFPERCLKEN0 0x44
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#define CMU_MAX_CLKS 37
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static struct clk_hw_onecell_data *clk_data;
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||||
static void __init efm32gg_cmu_init(struct device_node *np)
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||||
{
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||||
int i;
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||||
void __iomem *base;
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||||
struct clk_hw **hws;
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||||
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||||
clk_data = kzalloc(struct_size(clk_data, hws, CMU_MAX_CLKS),
|
||||
GFP_KERNEL);
|
||||
|
||||
if (!clk_data)
|
||||
return;
|
||||
|
||||
hws = clk_data->hws;
|
||||
|
||||
for (i = 0; i < CMU_MAX_CLKS; ++i)
|
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hws[i] = ERR_PTR(-ENOENT);
|
||||
|
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base = of_iomap(np, 0);
|
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if (!base) {
|
||||
pr_warn("Failed to map address range for efm32gg,cmu node\n");
|
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return;
|
||||
}
|
||||
|
||||
hws[clk_HFXO] = clk_hw_register_fixed_rate(NULL, "HFXO", NULL, 0,
|
||||
48000000);
|
||||
|
||||
hws[clk_HFPERCLKUSART0] = clk_hw_register_gate(NULL, "HFPERCLK.USART0",
|
||||
"HFXO", 0, base + CMU_HFPERCLKEN0, 0, 0, NULL);
|
||||
hws[clk_HFPERCLKUSART1] = clk_hw_register_gate(NULL, "HFPERCLK.USART1",
|
||||
"HFXO", 0, base + CMU_HFPERCLKEN0, 1, 0, NULL);
|
||||
hws[clk_HFPERCLKUSART2] = clk_hw_register_gate(NULL, "HFPERCLK.USART2",
|
||||
"HFXO", 0, base + CMU_HFPERCLKEN0, 2, 0, NULL);
|
||||
hws[clk_HFPERCLKUART0] = clk_hw_register_gate(NULL, "HFPERCLK.UART0",
|
||||
"HFXO", 0, base + CMU_HFPERCLKEN0, 3, 0, NULL);
|
||||
hws[clk_HFPERCLKUART1] = clk_hw_register_gate(NULL, "HFPERCLK.UART1",
|
||||
"HFXO", 0, base + CMU_HFPERCLKEN0, 4, 0, NULL);
|
||||
hws[clk_HFPERCLKTIMER0] = clk_hw_register_gate(NULL, "HFPERCLK.TIMER0",
|
||||
"HFXO", 0, base + CMU_HFPERCLKEN0, 5, 0, NULL);
|
||||
hws[clk_HFPERCLKTIMER1] = clk_hw_register_gate(NULL, "HFPERCLK.TIMER1",
|
||||
"HFXO", 0, base + CMU_HFPERCLKEN0, 6, 0, NULL);
|
||||
hws[clk_HFPERCLKTIMER2] = clk_hw_register_gate(NULL, "HFPERCLK.TIMER2",
|
||||
"HFXO", 0, base + CMU_HFPERCLKEN0, 7, 0, NULL);
|
||||
hws[clk_HFPERCLKTIMER3] = clk_hw_register_gate(NULL, "HFPERCLK.TIMER3",
|
||||
"HFXO", 0, base + CMU_HFPERCLKEN0, 8, 0, NULL);
|
||||
hws[clk_HFPERCLKACMP0] = clk_hw_register_gate(NULL, "HFPERCLK.ACMP0",
|
||||
"HFXO", 0, base + CMU_HFPERCLKEN0, 9, 0, NULL);
|
||||
hws[clk_HFPERCLKACMP1] = clk_hw_register_gate(NULL, "HFPERCLK.ACMP1",
|
||||
"HFXO", 0, base + CMU_HFPERCLKEN0, 10, 0, NULL);
|
||||
hws[clk_HFPERCLKI2C0] = clk_hw_register_gate(NULL, "HFPERCLK.I2C0",
|
||||
"HFXO", 0, base + CMU_HFPERCLKEN0, 11, 0, NULL);
|
||||
hws[clk_HFPERCLKI2C1] = clk_hw_register_gate(NULL, "HFPERCLK.I2C1",
|
||||
"HFXO", 0, base + CMU_HFPERCLKEN0, 12, 0, NULL);
|
||||
hws[clk_HFPERCLKGPIO] = clk_hw_register_gate(NULL, "HFPERCLK.GPIO",
|
||||
"HFXO", 0, base + CMU_HFPERCLKEN0, 13, 0, NULL);
|
||||
hws[clk_HFPERCLKVCMP] = clk_hw_register_gate(NULL, "HFPERCLK.VCMP",
|
||||
"HFXO", 0, base + CMU_HFPERCLKEN0, 14, 0, NULL);
|
||||
hws[clk_HFPERCLKPRS] = clk_hw_register_gate(NULL, "HFPERCLK.PRS",
|
||||
"HFXO", 0, base + CMU_HFPERCLKEN0, 15, 0, NULL);
|
||||
hws[clk_HFPERCLKADC0] = clk_hw_register_gate(NULL, "HFPERCLK.ADC0",
|
||||
"HFXO", 0, base + CMU_HFPERCLKEN0, 16, 0, NULL);
|
||||
hws[clk_HFPERCLKDAC0] = clk_hw_register_gate(NULL, "HFPERCLK.DAC0",
|
||||
"HFXO", 0, base + CMU_HFPERCLKEN0, 17, 0, NULL);
|
||||
|
||||
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
|
||||
}
|
||||
CLK_OF_DECLARE(efm32ggcmu, "efm32gg,cmu", efm32gg_cmu_init);
|
||||
@ -1,85 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#define CLK_COUNT 4 /* cpu_clk, sys_clk, usb_clk, sdio_clk */
|
||||
static struct clk *clks[CLK_COUNT];
|
||||
static struct clk_onecell_data clk_data = { clks, CLK_COUNT };
|
||||
|
||||
#define SYSCLK_DIV 0x20
|
||||
#define CPUCLK_DIV 0x24
|
||||
#define DIV_BYPASS BIT(23)
|
||||
|
||||
/*** CLKGEN_PLL ***/
|
||||
#define extract_pll_n(val) ((val >> 0) & ((1u << 7) - 1))
|
||||
#define extract_pll_k(val) ((val >> 13) & ((1u << 3) - 1))
|
||||
#define extract_pll_m(val) ((val >> 16) & ((1u << 3) - 1))
|
||||
#define extract_pll_isel(val) ((val >> 24) & ((1u << 3) - 1))
|
||||
|
||||
static void __init make_pll(int idx, const char *parent, void __iomem *base)
|
||||
{
|
||||
char name[8];
|
||||
u32 val, mul, div;
|
||||
|
||||
sprintf(name, "pll%d", idx);
|
||||
val = readl(base + idx * 8);
|
||||
mul = extract_pll_n(val) + 1;
|
||||
div = (extract_pll_m(val) + 1) << extract_pll_k(val);
|
||||
clk_register_fixed_factor(NULL, name, parent, 0, mul, div);
|
||||
if (extract_pll_isel(val) != 1)
|
||||
panic("%s: input not set to XTAL_IN\n", name);
|
||||
}
|
||||
|
||||
static void __init make_cd(int idx, void __iomem *base)
|
||||
{
|
||||
char name[8];
|
||||
u32 val, mul, div;
|
||||
|
||||
sprintf(name, "cd%d", idx);
|
||||
val = readl(base + idx * 8);
|
||||
mul = 1 << 27;
|
||||
div = (2 << 27) + val;
|
||||
clk_register_fixed_factor(NULL, name, "pll2", 0, mul, div);
|
||||
if (val > 0xf0000000)
|
||||
panic("%s: unsupported divider %x\n", name, val);
|
||||
}
|
||||
|
||||
static void __init tango4_clkgen_setup(struct device_node *np)
|
||||
{
|
||||
struct clk **pp = clk_data.clks;
|
||||
void __iomem *base = of_iomap(np, 0);
|
||||
const char *parent = of_clk_get_parent_name(np, 0);
|
||||
|
||||
if (!base)
|
||||
panic("%pOFn: invalid address\n", np);
|
||||
|
||||
if (readl(base + CPUCLK_DIV) & DIV_BYPASS)
|
||||
panic("%pOFn: unsupported cpuclk setup\n", np);
|
||||
|
||||
if (readl(base + SYSCLK_DIV) & DIV_BYPASS)
|
||||
panic("%pOFn: unsupported sysclk setup\n", np);
|
||||
|
||||
writel(0x100, base + CPUCLK_DIV); /* disable frequency ramping */
|
||||
|
||||
make_pll(0, parent, base);
|
||||
make_pll(1, parent, base);
|
||||
make_pll(2, parent, base);
|
||||
make_cd(2, base + 0x80);
|
||||
make_cd(6, base + 0x80);
|
||||
|
||||
pp[0] = clk_register_divider(NULL, "cpu_clk", "pll0", 0,
|
||||
base + CPUCLK_DIV, 8, 8, CLK_DIVIDER_ONE_BASED, NULL);
|
||||
pp[1] = clk_register_fixed_factor(NULL, "sys_clk", "pll1", 0, 1, 4);
|
||||
pp[2] = clk_register_fixed_factor(NULL, "usb_clk", "cd2", 0, 1, 2);
|
||||
pp[3] = clk_register_fixed_factor(NULL, "sdio_clk", "cd6", 0, 1, 2);
|
||||
|
||||
if (IS_ERR(pp[0]) || IS_ERR(pp[1]) || IS_ERR(pp[2]) || IS_ERR(pp[3]))
|
||||
panic("%pOFn: clk registration failed\n", np);
|
||||
|
||||
if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data))
|
||||
panic("%pOFn: clk provider registration failed\n", np);
|
||||
}
|
||||
CLK_OF_DECLARE(tango4_clkgen, "sigma,tango4-clkgen", tango4_clkgen_setup);
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,6 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
#
|
||||
# Makefile for sirf specific clk
|
||||
#
|
||||
|
||||
obj-$(CONFIG_ARCH_SIRF) += clk-prima2.o clk-atlas6.o clk-atlas7.o
|
||||
@ -1,32 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#define SIRFSOC_CLKC_CLK_EN0 0x0000
|
||||
#define SIRFSOC_CLKC_CLK_EN1 0x0004
|
||||
#define SIRFSOC_CLKC_REF_CFG 0x0020
|
||||
#define SIRFSOC_CLKC_CPU_CFG 0x0024
|
||||
#define SIRFSOC_CLKC_MEM_CFG 0x0028
|
||||
#define SIRFSOC_CLKC_MEMDIV_CFG 0x002C
|
||||
#define SIRFSOC_CLKC_SYS_CFG 0x0030
|
||||
#define SIRFSOC_CLKC_IO_CFG 0x0034
|
||||
#define SIRFSOC_CLKC_DSP_CFG 0x0038
|
||||
#define SIRFSOC_CLKC_GFX_CFG 0x003c
|
||||
#define SIRFSOC_CLKC_MM_CFG 0x0040
|
||||
#define SIRFSOC_CLKC_GFX2D_CFG 0x0040
|
||||
#define SIRFSOC_CLKC_LCD_CFG 0x0044
|
||||
#define SIRFSOC_CLKC_MMC01_CFG 0x0048
|
||||
#define SIRFSOC_CLKC_MMC23_CFG 0x004C
|
||||
#define SIRFSOC_CLKC_MMC45_CFG 0x0050
|
||||
#define SIRFSOC_CLKC_NAND_CFG 0x0054
|
||||
#define SIRFSOC_CLKC_NANDDIV_CFG 0x0058
|
||||
#define SIRFSOC_CLKC_PLL1_CFG0 0x0080
|
||||
#define SIRFSOC_CLKC_PLL2_CFG0 0x0084
|
||||
#define SIRFSOC_CLKC_PLL3_CFG0 0x0088
|
||||
#define SIRFSOC_CLKC_PLL1_CFG1 0x008c
|
||||
#define SIRFSOC_CLKC_PLL2_CFG1 0x0090
|
||||
#define SIRFSOC_CLKC_PLL3_CFG1 0x0094
|
||||
#define SIRFSOC_CLKC_PLL1_CFG2 0x0098
|
||||
#define SIRFSOC_CLKC_PLL2_CFG2 0x009c
|
||||
#define SIRFSOC_CLKC_PLL3_CFG2 0x00A0
|
||||
#define SIRFSOC_USBPHY_PLL_CTRL 0x0008
|
||||
#define SIRFSOC_USBPHY_PLL_POWERDOWN BIT(1)
|
||||
#define SIRFSOC_USBPHY_PLL_BYPASS BIT(2)
|
||||
#define SIRFSOC_USBPHY_PLL_LOCK BIT(3)
|
||||
@ -1,150 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Clock tree for CSR SiRFatlasVI
|
||||
*
|
||||
* Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
|
||||
* company.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
|
||||
#include "atlas6.h"
|
||||
#include "clk-common.c"
|
||||
|
||||
static struct clk_dmn clk_mmc01 = {
|
||||
.regofs = SIRFSOC_CLKC_MMC01_CFG,
|
||||
.enable_bit = 59,
|
||||
.hw = {
|
||||
.init = &clk_mmc01_init,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_dmn clk_mmc23 = {
|
||||
.regofs = SIRFSOC_CLKC_MMC23_CFG,
|
||||
.enable_bit = 60,
|
||||
.hw = {
|
||||
.init = &clk_mmc23_init,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_dmn clk_mmc45 = {
|
||||
.regofs = SIRFSOC_CLKC_MMC45_CFG,
|
||||
.enable_bit = 61,
|
||||
.hw = {
|
||||
.init = &clk_mmc45_init,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct clk_init_data clk_nand_init = {
|
||||
.name = "nand",
|
||||
.ops = &dmn_ops,
|
||||
.parent_names = dmn_clk_parents,
|
||||
.num_parents = ARRAY_SIZE(dmn_clk_parents),
|
||||
};
|
||||
|
||||
static struct clk_dmn clk_nand = {
|
||||
.regofs = SIRFSOC_CLKC_NAND_CFG,
|
||||
.enable_bit = 34,
|
||||
.hw = {
|
||||
.init = &clk_nand_init,
|
||||
},
|
||||
};
|
||||
|
||||
enum atlas6_clk_index {
|
||||
/* 0 1 2 3 4 5 6 7 8 9 */
|
||||
rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps,
|
||||
mf, io, cpu, uart0, uart1, uart2, tsc, i2c0, i2c1, spi0,
|
||||
spi1, pwmc, efuse, pulse, dmac0, dmac1, nand, audio, usp0, usp1,
|
||||
usp2, vip, gfx, gfx2d, lcd, vpp, mmc01, mmc23, mmc45, usbpll,
|
||||
usb0, usb1, cphif, maxclk,
|
||||
};
|
||||
|
||||
static __initdata struct clk_hw *atlas6_clk_hw_array[maxclk] = {
|
||||
NULL, /* dummy */
|
||||
NULL,
|
||||
&clk_pll1.hw,
|
||||
&clk_pll2.hw,
|
||||
&clk_pll3.hw,
|
||||
&clk_mem.hw,
|
||||
&clk_sys.hw,
|
||||
&clk_security.hw,
|
||||
&clk_dsp.hw,
|
||||
&clk_gps.hw,
|
||||
&clk_mf.hw,
|
||||
&clk_io.hw,
|
||||
&clk_cpu.hw,
|
||||
&clk_uart0.hw,
|
||||
&clk_uart1.hw,
|
||||
&clk_uart2.hw,
|
||||
&clk_tsc.hw,
|
||||
&clk_i2c0.hw,
|
||||
&clk_i2c1.hw,
|
||||
&clk_spi0.hw,
|
||||
&clk_spi1.hw,
|
||||
&clk_pwmc.hw,
|
||||
&clk_efuse.hw,
|
||||
&clk_pulse.hw,
|
||||
&clk_dmac0.hw,
|
||||
&clk_dmac1.hw,
|
||||
&clk_nand.hw,
|
||||
&clk_audio.hw,
|
||||
&clk_usp0.hw,
|
||||
&clk_usp1.hw,
|
||||
&clk_usp2.hw,
|
||||
&clk_vip.hw,
|
||||
&clk_gfx.hw,
|
||||
&clk_gfx2d.hw,
|
||||
&clk_lcd.hw,
|
||||
&clk_vpp.hw,
|
||||
&clk_mmc01.hw,
|
||||
&clk_mmc23.hw,
|
||||
&clk_mmc45.hw,
|
||||
&usb_pll_clk_hw,
|
||||
&clk_usb0.hw,
|
||||
&clk_usb1.hw,
|
||||
&clk_cphif.hw,
|
||||
};
|
||||
|
||||
static struct clk *atlas6_clks[maxclk];
|
||||
|
||||
static void __init atlas6_clk_init(struct device_node *np)
|
||||
{
|
||||
struct device_node *rscnp;
|
||||
int i;
|
||||
|
||||
rscnp = of_find_compatible_node(NULL, NULL, "sirf,prima2-rsc");
|
||||
sirfsoc_rsc_vbase = of_iomap(rscnp, 0);
|
||||
if (!sirfsoc_rsc_vbase)
|
||||
panic("unable to map rsc registers\n");
|
||||
of_node_put(rscnp);
|
||||
|
||||
sirfsoc_clk_vbase = of_iomap(np, 0);
|
||||
if (!sirfsoc_clk_vbase)
|
||||
panic("unable to map clkc registers\n");
|
||||
|
||||
/* These are always available (RTC and 26MHz OSC)*/
|
||||
atlas6_clks[rtc] = clk_register_fixed_rate(NULL, "rtc", NULL, 0, 32768);
|
||||
atlas6_clks[osc] = clk_register_fixed_rate(NULL, "osc", NULL, 0,
|
||||
26000000);
|
||||
|
||||
for (i = pll1; i < maxclk; i++) {
|
||||
atlas6_clks[i] = clk_register(NULL, atlas6_clk_hw_array[i]);
|
||||
BUG_ON(IS_ERR(atlas6_clks[i]));
|
||||
}
|
||||
clk_register_clkdev(atlas6_clks[cpu], NULL, "cpu");
|
||||
clk_register_clkdev(atlas6_clks[io], NULL, "io");
|
||||
clk_register_clkdev(atlas6_clks[mem], NULL, "mem");
|
||||
clk_register_clkdev(atlas6_clks[mem], NULL, "osc");
|
||||
|
||||
clk_data.clks = atlas6_clks;
|
||||
clk_data.clk_num = maxclk;
|
||||
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
}
|
||||
CLK_OF_DECLARE(atlas6_clk, "sirf,atlas6-clkc", atlas6_clk_init);
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,149 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Clock tree for CSR SiRFprimaII
|
||||
*
|
||||
* Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
|
||||
* company.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
|
||||
#include "prima2.h"
|
||||
#include "clk-common.c"
|
||||
|
||||
static struct clk_dmn clk_mmc01 = {
|
||||
.regofs = SIRFSOC_CLKC_MMC_CFG,
|
||||
.enable_bit = 59,
|
||||
.hw = {
|
||||
.init = &clk_mmc01_init,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_dmn clk_mmc23 = {
|
||||
.regofs = SIRFSOC_CLKC_MMC_CFG,
|
||||
.enable_bit = 60,
|
||||
.hw = {
|
||||
.init = &clk_mmc23_init,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_dmn clk_mmc45 = {
|
||||
.regofs = SIRFSOC_CLKC_MMC_CFG,
|
||||
.enable_bit = 61,
|
||||
.hw = {
|
||||
.init = &clk_mmc45_init,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct clk_init_data clk_nand_init = {
|
||||
.name = "nand",
|
||||
.ops = &ios_ops,
|
||||
.parent_names = std_clk_io_parents,
|
||||
.num_parents = ARRAY_SIZE(std_clk_io_parents),
|
||||
};
|
||||
|
||||
static struct clk_std clk_nand = {
|
||||
.enable_bit = 34,
|
||||
.hw = {
|
||||
.init = &clk_nand_init,
|
||||
},
|
||||
};
|
||||
|
||||
enum prima2_clk_index {
|
||||
/* 0 1 2 3 4 5 6 7 8 9 */
|
||||
rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps,
|
||||
mf, io, cpu, uart0, uart1, uart2, tsc, i2c0, i2c1, spi0,
|
||||
spi1, pwmc, efuse, pulse, dmac0, dmac1, nand, audio, usp0, usp1,
|
||||
usp2, vip, gfx, mm, lcd, vpp, mmc01, mmc23, mmc45, usbpll,
|
||||
usb0, usb1, cphif, maxclk,
|
||||
};
|
||||
|
||||
static __initdata struct clk_hw *prima2_clk_hw_array[maxclk] = {
|
||||
NULL, /* dummy */
|
||||
NULL,
|
||||
&clk_pll1.hw,
|
||||
&clk_pll2.hw,
|
||||
&clk_pll3.hw,
|
||||
&clk_mem.hw,
|
||||
&clk_sys.hw,
|
||||
&clk_security.hw,
|
||||
&clk_dsp.hw,
|
||||
&clk_gps.hw,
|
||||
&clk_mf.hw,
|
||||
&clk_io.hw,
|
||||
&clk_cpu.hw,
|
||||
&clk_uart0.hw,
|
||||
&clk_uart1.hw,
|
||||
&clk_uart2.hw,
|
||||
&clk_tsc.hw,
|
||||
&clk_i2c0.hw,
|
||||
&clk_i2c1.hw,
|
||||
&clk_spi0.hw,
|
||||
&clk_spi1.hw,
|
||||
&clk_pwmc.hw,
|
||||
&clk_efuse.hw,
|
||||
&clk_pulse.hw,
|
||||
&clk_dmac0.hw,
|
||||
&clk_dmac1.hw,
|
||||
&clk_nand.hw,
|
||||
&clk_audio.hw,
|
||||
&clk_usp0.hw,
|
||||
&clk_usp1.hw,
|
||||
&clk_usp2.hw,
|
||||
&clk_vip.hw,
|
||||
&clk_gfx.hw,
|
||||
&clk_mm.hw,
|
||||
&clk_lcd.hw,
|
||||
&clk_vpp.hw,
|
||||
&clk_mmc01.hw,
|
||||
&clk_mmc23.hw,
|
||||
&clk_mmc45.hw,
|
||||
&usb_pll_clk_hw,
|
||||
&clk_usb0.hw,
|
||||
&clk_usb1.hw,
|
||||
&clk_cphif.hw,
|
||||
};
|
||||
|
||||
static struct clk *prima2_clks[maxclk];
|
||||
|
||||
static void __init prima2_clk_init(struct device_node *np)
|
||||
{
|
||||
struct device_node *rscnp;
|
||||
int i;
|
||||
|
||||
rscnp = of_find_compatible_node(NULL, NULL, "sirf,prima2-rsc");
|
||||
sirfsoc_rsc_vbase = of_iomap(rscnp, 0);
|
||||
if (!sirfsoc_rsc_vbase)
|
||||
panic("unable to map rsc registers\n");
|
||||
of_node_put(rscnp);
|
||||
|
||||
sirfsoc_clk_vbase = of_iomap(np, 0);
|
||||
if (!sirfsoc_clk_vbase)
|
||||
panic("unable to map clkc registers\n");
|
||||
|
||||
/* These are always available (RTC and 26MHz OSC)*/
|
||||
prima2_clks[rtc] = clk_register_fixed_rate(NULL, "rtc", NULL, 0, 32768);
|
||||
prima2_clks[osc] = clk_register_fixed_rate(NULL, "osc", NULL, 0,
|
||||
26000000);
|
||||
|
||||
for (i = pll1; i < maxclk; i++) {
|
||||
prima2_clks[i] = clk_register(NULL, prima2_clk_hw_array[i]);
|
||||
BUG_ON(IS_ERR(prima2_clks[i]));
|
||||
}
|
||||
clk_register_clkdev(prima2_clks[cpu], NULL, "cpu");
|
||||
clk_register_clkdev(prima2_clks[io], NULL, "io");
|
||||
clk_register_clkdev(prima2_clks[mem], NULL, "mem");
|
||||
clk_register_clkdev(prima2_clks[mem], NULL, "osc");
|
||||
|
||||
clk_data.clks = prima2_clks;
|
||||
clk_data.clk_num = maxclk;
|
||||
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
}
|
||||
CLK_OF_DECLARE(prima2_clk, "sirf,prima2-clkc", prima2_clk_init);
|
||||
@ -1,26 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#define SIRFSOC_CLKC_CLK_EN0 0x0000
|
||||
#define SIRFSOC_CLKC_CLK_EN1 0x0004
|
||||
#define SIRFSOC_CLKC_REF_CFG 0x0014
|
||||
#define SIRFSOC_CLKC_CPU_CFG 0x0018
|
||||
#define SIRFSOC_CLKC_MEM_CFG 0x001c
|
||||
#define SIRFSOC_CLKC_SYS_CFG 0x0020
|
||||
#define SIRFSOC_CLKC_IO_CFG 0x0024
|
||||
#define SIRFSOC_CLKC_DSP_CFG 0x0028
|
||||
#define SIRFSOC_CLKC_GFX_CFG 0x002c
|
||||
#define SIRFSOC_CLKC_MM_CFG 0x0030
|
||||
#define SIRFSOC_CLKC_LCD_CFG 0x0034
|
||||
#define SIRFSOC_CLKC_MMC_CFG 0x0038
|
||||
#define SIRFSOC_CLKC_PLL1_CFG0 0x0040
|
||||
#define SIRFSOC_CLKC_PLL2_CFG0 0x0044
|
||||
#define SIRFSOC_CLKC_PLL3_CFG0 0x0048
|
||||
#define SIRFSOC_CLKC_PLL1_CFG1 0x004c
|
||||
#define SIRFSOC_CLKC_PLL2_CFG1 0x0050
|
||||
#define SIRFSOC_CLKC_PLL3_CFG1 0x0054
|
||||
#define SIRFSOC_CLKC_PLL1_CFG2 0x0058
|
||||
#define SIRFSOC_CLKC_PLL2_CFG2 0x005c
|
||||
#define SIRFSOC_CLKC_PLL3_CFG2 0x0060
|
||||
#define SIRFSOC_USBPHY_PLL_CTRL 0x0008
|
||||
#define SIRFSOC_USBPHY_PLL_POWERDOWN BIT(1)
|
||||
#define SIRFSOC_USBPHY_PLL_BYPASS BIT(2)
|
||||
#define SIRFSOC_USBPHY_PLL_LOCK BIT(3)
|
||||
@ -1,4 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
obj-y := clk.o
|
||||
obj-$(CONFIG_SOC_ZX296702) += clk-zx296702.o
|
||||
obj-$(CONFIG_ARCH_ZX) += clk-zx296718.o
|
||||
@ -1,741 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright 2014 Linaro Ltd.
|
||||
* Copyright (C) 2014 ZTE Corporation.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <dt-bindings/clock/zx296702-clock.h>
|
||||
#include "clk.h"
|
||||
|
||||
static DEFINE_SPINLOCK(reg_lock);
|
||||
|
||||
static void __iomem *topcrm_base;
|
||||
static void __iomem *lsp0crpm_base;
|
||||
static void __iomem *lsp1crpm_base;
|
||||
|
||||
static struct clk *topclk[ZX296702_TOPCLK_END];
|
||||
static struct clk *lsp0clk[ZX296702_LSP0CLK_END];
|
||||
static struct clk *lsp1clk[ZX296702_LSP1CLK_END];
|
||||
|
||||
static struct clk_onecell_data topclk_data;
|
||||
static struct clk_onecell_data lsp0clk_data;
|
||||
static struct clk_onecell_data lsp1clk_data;
|
||||
|
||||
#define CLK_MUX (topcrm_base + 0x04)
|
||||
#define CLK_DIV (topcrm_base + 0x08)
|
||||
#define CLK_EN0 (topcrm_base + 0x0c)
|
||||
#define CLK_EN1 (topcrm_base + 0x10)
|
||||
#define VOU_LOCAL_CLKEN (topcrm_base + 0x68)
|
||||
#define VOU_LOCAL_CLKSEL (topcrm_base + 0x70)
|
||||
#define VOU_LOCAL_DIV2_SET (topcrm_base + 0x74)
|
||||
#define CLK_MUX1 (topcrm_base + 0x8c)
|
||||
|
||||
#define CLK_SDMMC1 (lsp0crpm_base + 0x0c)
|
||||
#define CLK_GPIO (lsp0crpm_base + 0x2c)
|
||||
#define CLK_SPDIF0 (lsp0crpm_base + 0x10)
|
||||
#define SPDIF0_DIV (lsp0crpm_base + 0x14)
|
||||
#define CLK_I2S0 (lsp0crpm_base + 0x18)
|
||||
#define I2S0_DIV (lsp0crpm_base + 0x1c)
|
||||
#define CLK_I2S1 (lsp0crpm_base + 0x20)
|
||||
#define I2S1_DIV (lsp0crpm_base + 0x24)
|
||||
#define CLK_I2S2 (lsp0crpm_base + 0x34)
|
||||
#define I2S2_DIV (lsp0crpm_base + 0x38)
|
||||
|
||||
#define CLK_UART0 (lsp1crpm_base + 0x20)
|
||||
#define CLK_UART1 (lsp1crpm_base + 0x24)
|
||||
#define CLK_SDMMC0 (lsp1crpm_base + 0x2c)
|
||||
#define CLK_SPDIF1 (lsp1crpm_base + 0x30)
|
||||
#define SPDIF1_DIV (lsp1crpm_base + 0x34)
|
||||
|
||||
static const struct zx_pll_config pll_a9_config[] = {
|
||||
{ .rate = 700000000, .cfg0 = 0x800405d1, .cfg1 = 0x04555555 },
|
||||
{ .rate = 800000000, .cfg0 = 0x80040691, .cfg1 = 0x04aaaaaa },
|
||||
{ .rate = 900000000, .cfg0 = 0x80040791, .cfg1 = 0x04000000 },
|
||||
{ .rate = 1000000000, .cfg0 = 0x80040851, .cfg1 = 0x04555555 },
|
||||
{ .rate = 1100000000, .cfg0 = 0x80040911, .cfg1 = 0x04aaaaaa },
|
||||
{ .rate = 1200000000, .cfg0 = 0x80040a11, .cfg1 = 0x04000000 },
|
||||
};
|
||||
|
||||
static const struct clk_div_table main_hlk_div[] = {
|
||||
{ .val = 1, .div = 2, },
|
||||
{ .val = 3, .div = 4, },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct clk_div_table a9_as1_aclk_divider[] = {
|
||||
{ .val = 0, .div = 1, },
|
||||
{ .val = 1, .div = 2, },
|
||||
{ .val = 3, .div = 4, },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct clk_div_table sec_wclk_divider[] = {
|
||||
{ .val = 0, .div = 1, },
|
||||
{ .val = 1, .div = 2, },
|
||||
{ .val = 3, .div = 4, },
|
||||
{ .val = 5, .div = 6, },
|
||||
{ .val = 7, .div = 8, },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const char * const matrix_aclk_sel[] = {
|
||||
"pll_mm0_198M",
|
||||
"osc",
|
||||
"clk_148M5",
|
||||
"pll_lsp_104M",
|
||||
};
|
||||
|
||||
static const char * const a9_wclk_sel[] = {
|
||||
"pll_a9",
|
||||
"osc",
|
||||
"clk_500",
|
||||
"clk_250",
|
||||
};
|
||||
|
||||
static const char * const a9_as1_aclk_sel[] = {
|
||||
"clk_250",
|
||||
"osc",
|
||||
"pll_mm0_396M",
|
||||
"pll_mac_333M",
|
||||
};
|
||||
|
||||
static const char * const a9_trace_clkin_sel[] = {
|
||||
"clk_74M25",
|
||||
"pll_mm1_108M",
|
||||
"clk_125",
|
||||
"clk_148M5",
|
||||
};
|
||||
|
||||
static const char * const decppu_aclk_sel[] = {
|
||||
"clk_250",
|
||||
"pll_mm0_198M",
|
||||
"pll_lsp_104M",
|
||||
"pll_audio_294M912",
|
||||
};
|
||||
|
||||
static const char * const vou_main_wclk_sel[] = {
|
||||
"clk_148M5",
|
||||
"clk_74M25",
|
||||
"clk_27",
|
||||
"pll_mm1_54M",
|
||||
};
|
||||
|
||||
static const char * const vou_scaler_wclk_sel[] = {
|
||||
"clk_250",
|
||||
"pll_mac_333M",
|
||||
"pll_audio_294M912",
|
||||
"pll_mm0_198M",
|
||||
};
|
||||
|
||||
static const char * const r2d_wclk_sel[] = {
|
||||
"pll_audio_294M912",
|
||||
"pll_mac_333M",
|
||||
"pll_a9_350M",
|
||||
"pll_mm0_396M",
|
||||
};
|
||||
|
||||
static const char * const ddr_wclk_sel[] = {
|
||||
"pll_mac_333M",
|
||||
"pll_ddr_266M",
|
||||
"pll_audio_294M912",
|
||||
"pll_mm0_198M",
|
||||
};
|
||||
|
||||
static const char * const nand_wclk_sel[] = {
|
||||
"pll_lsp_104M",
|
||||
"osc",
|
||||
};
|
||||
|
||||
static const char * const lsp_26_wclk_sel[] = {
|
||||
"pll_lsp_26M",
|
||||
"osc",
|
||||
};
|
||||
|
||||
static const char * const vl0_sel[] = {
|
||||
"vou_main_channel_div",
|
||||
"vou_aux_channel_div",
|
||||
};
|
||||
|
||||
static const char * const hdmi_sel[] = {
|
||||
"vou_main_channel_wclk",
|
||||
"vou_aux_channel_wclk",
|
||||
};
|
||||
|
||||
static const char * const sdmmc0_wclk_sel[] = {
|
||||
"lsp1_104M_wclk",
|
||||
"lsp1_26M_wclk",
|
||||
};
|
||||
|
||||
static const char * const sdmmc1_wclk_sel[] = {
|
||||
"lsp0_104M_wclk",
|
||||
"lsp0_26M_wclk",
|
||||
};
|
||||
|
||||
static const char * const uart_wclk_sel[] = {
|
||||
"lsp1_104M_wclk",
|
||||
"lsp1_26M_wclk",
|
||||
};
|
||||
|
||||
static const char * const spdif0_wclk_sel[] = {
|
||||
"lsp0_104M_wclk",
|
||||
"lsp0_26M_wclk",
|
||||
};
|
||||
|
||||
static const char * const spdif1_wclk_sel[] = {
|
||||
"lsp1_104M_wclk",
|
||||
"lsp1_26M_wclk",
|
||||
};
|
||||
|
||||
static const char * const i2s_wclk_sel[] = {
|
||||
"lsp0_104M_wclk",
|
||||
"lsp0_26M_wclk",
|
||||
};
|
||||
|
||||
static inline struct clk *zx_divtbl(const char *name, const char *parent,
|
||||
void __iomem *reg, u8 shift, u8 width,
|
||||
const struct clk_div_table *table)
|
||||
{
|
||||
return clk_register_divider_table(NULL, name, parent, 0, reg, shift,
|
||||
width, 0, table, ®_lock);
|
||||
}
|
||||
|
||||
static inline struct clk *zx_div(const char *name, const char *parent,
|
||||
void __iomem *reg, u8 shift, u8 width)
|
||||
{
|
||||
return clk_register_divider(NULL, name, parent, 0,
|
||||
reg, shift, width, 0, ®_lock);
|
||||
}
|
||||
|
||||
static inline struct clk *zx_mux(const char *name, const char * const *parents,
|
||||
int num_parents, void __iomem *reg, u8 shift, u8 width)
|
||||
{
|
||||
return clk_register_mux(NULL, name, parents, num_parents,
|
||||
0, reg, shift, width, 0, ®_lock);
|
||||
}
|
||||
|
||||
static inline struct clk *zx_gate(const char *name, const char *parent,
|
||||
void __iomem *reg, u8 shift)
|
||||
{
|
||||
return clk_register_gate(NULL, name, parent, CLK_IGNORE_UNUSED,
|
||||
reg, shift, CLK_SET_RATE_PARENT, ®_lock);
|
||||
}
|
||||
|
||||
static void __init zx296702_top_clocks_init(struct device_node *np)
|
||||
{
|
||||
struct clk **clk = topclk;
|
||||
int i;
|
||||
|
||||
topcrm_base = of_iomap(np, 0);
|
||||
WARN_ON(!topcrm_base);
|
||||
|
||||
clk[ZX296702_OSC] =
|
||||
clk_register_fixed_rate(NULL, "osc", NULL, 0, 30000000);
|
||||
clk[ZX296702_PLL_A9] =
|
||||
clk_register_zx_pll("pll_a9", "osc", 0, topcrm_base
|
||||
+ 0x01c, pll_a9_config,
|
||||
ARRAY_SIZE(pll_a9_config), ®_lock);
|
||||
|
||||
/* TODO: pll_a9_350M look like changeble follow a9 pll */
|
||||
clk[ZX296702_PLL_A9_350M] =
|
||||
clk_register_fixed_rate(NULL, "pll_a9_350M", "osc", 0,
|
||||
350000000);
|
||||
clk[ZX296702_PLL_MAC_1000M] =
|
||||
clk_register_fixed_rate(NULL, "pll_mac_1000M", "osc", 0,
|
||||
1000000000);
|
||||
clk[ZX296702_PLL_MAC_333M] =
|
||||
clk_register_fixed_rate(NULL, "pll_mac_333M", "osc", 0,
|
||||
333000000);
|
||||
clk[ZX296702_PLL_MM0_1188M] =
|
||||
clk_register_fixed_rate(NULL, "pll_mm0_1188M", "osc", 0,
|
||||
1188000000);
|
||||
clk[ZX296702_PLL_MM0_396M] =
|
||||
clk_register_fixed_rate(NULL, "pll_mm0_396M", "osc", 0,
|
||||
396000000);
|
||||
clk[ZX296702_PLL_MM0_198M] =
|
||||
clk_register_fixed_rate(NULL, "pll_mm0_198M", "osc", 0,
|
||||
198000000);
|
||||
clk[ZX296702_PLL_MM1_108M] =
|
||||
clk_register_fixed_rate(NULL, "pll_mm1_108M", "osc", 0,
|
||||
108000000);
|
||||
clk[ZX296702_PLL_MM1_72M] =
|
||||
clk_register_fixed_rate(NULL, "pll_mm1_72M", "osc", 0,
|
||||
72000000);
|
||||
clk[ZX296702_PLL_MM1_54M] =
|
||||
clk_register_fixed_rate(NULL, "pll_mm1_54M", "osc", 0,
|
||||
54000000);
|
||||
clk[ZX296702_PLL_LSP_104M] =
|
||||
clk_register_fixed_rate(NULL, "pll_lsp_104M", "osc", 0,
|
||||
104000000);
|
||||
clk[ZX296702_PLL_LSP_26M] =
|
||||
clk_register_fixed_rate(NULL, "pll_lsp_26M", "osc", 0,
|
||||
26000000);
|
||||
clk[ZX296702_PLL_DDR_266M] =
|
||||
clk_register_fixed_rate(NULL, "pll_ddr_266M", "osc", 0,
|
||||
266000000);
|
||||
clk[ZX296702_PLL_AUDIO_294M912] =
|
||||
clk_register_fixed_rate(NULL, "pll_audio_294M912", "osc", 0,
|
||||
294912000);
|
||||
|
||||
/* bus clock */
|
||||
clk[ZX296702_MATRIX_ACLK] =
|
||||
zx_mux("matrix_aclk", matrix_aclk_sel,
|
||||
ARRAY_SIZE(matrix_aclk_sel), CLK_MUX, 2, 2);
|
||||
clk[ZX296702_MAIN_HCLK] =
|
||||
zx_divtbl("main_hclk", "matrix_aclk", CLK_DIV, 0, 2,
|
||||
main_hlk_div);
|
||||
clk[ZX296702_MAIN_PCLK] =
|
||||
zx_divtbl("main_pclk", "matrix_aclk", CLK_DIV, 2, 2,
|
||||
main_hlk_div);
|
||||
|
||||
/* cpu clock */
|
||||
clk[ZX296702_CLK_500] =
|
||||
clk_register_fixed_factor(NULL, "clk_500", "pll_mac_1000M", 0,
|
||||
1, 2);
|
||||
clk[ZX296702_CLK_250] =
|
||||
clk_register_fixed_factor(NULL, "clk_250", "pll_mac_1000M", 0,
|
||||
1, 4);
|
||||
clk[ZX296702_CLK_125] =
|
||||
clk_register_fixed_factor(NULL, "clk_125", "clk_250", 0, 1, 2);
|
||||
clk[ZX296702_CLK_148M5] =
|
||||
clk_register_fixed_factor(NULL, "clk_148M5", "pll_mm0_1188M", 0,
|
||||
1, 8);
|
||||
clk[ZX296702_CLK_74M25] =
|
||||
clk_register_fixed_factor(NULL, "clk_74M25", "pll_mm0_1188M", 0,
|
||||
1, 16);
|
||||
clk[ZX296702_A9_WCLK] =
|
||||
zx_mux("a9_wclk", a9_wclk_sel, ARRAY_SIZE(a9_wclk_sel), CLK_MUX,
|
||||
0, 2);
|
||||
clk[ZX296702_A9_AS1_ACLK_MUX] =
|
||||
zx_mux("a9_as1_aclk_mux", a9_as1_aclk_sel,
|
||||
ARRAY_SIZE(a9_as1_aclk_sel), CLK_MUX, 4, 2);
|
||||
clk[ZX296702_A9_TRACE_CLKIN_MUX] =
|
||||
zx_mux("a9_trace_clkin_mux", a9_trace_clkin_sel,
|
||||
ARRAY_SIZE(a9_trace_clkin_sel), CLK_MUX1, 0, 2);
|
||||
clk[ZX296702_A9_AS1_ACLK_DIV] =
|
||||
zx_divtbl("a9_as1_aclk_div", "a9_as1_aclk_mux", CLK_DIV, 4, 2,
|
||||
a9_as1_aclk_divider);
|
||||
|
||||
/* multi-media clock */
|
||||
clk[ZX296702_CLK_2] =
|
||||
clk_register_fixed_factor(NULL, "clk_2", "pll_mm1_72M", 0,
|
||||
1, 36);
|
||||
clk[ZX296702_CLK_27] =
|
||||
clk_register_fixed_factor(NULL, "clk_27", "pll_mm1_54M", 0,
|
||||
1, 2);
|
||||
clk[ZX296702_DECPPU_ACLK_MUX] =
|
||||
zx_mux("decppu_aclk_mux", decppu_aclk_sel,
|
||||
ARRAY_SIZE(decppu_aclk_sel), CLK_MUX, 6, 2);
|
||||
clk[ZX296702_PPU_ACLK_MUX] =
|
||||
zx_mux("ppu_aclk_mux", decppu_aclk_sel,
|
||||
ARRAY_SIZE(decppu_aclk_sel), CLK_MUX, 8, 2);
|
||||
clk[ZX296702_MALI400_ACLK_MUX] =
|
||||
zx_mux("mali400_aclk_mux", decppu_aclk_sel,
|
||||
ARRAY_SIZE(decppu_aclk_sel), CLK_MUX, 12, 2);
|
||||
clk[ZX296702_VOU_ACLK_MUX] =
|
||||
zx_mux("vou_aclk_mux", decppu_aclk_sel,
|
||||
ARRAY_SIZE(decppu_aclk_sel), CLK_MUX, 10, 2);
|
||||
clk[ZX296702_VOU_MAIN_WCLK_MUX] =
|
||||
zx_mux("vou_main_wclk_mux", vou_main_wclk_sel,
|
||||
ARRAY_SIZE(vou_main_wclk_sel), CLK_MUX, 14, 2);
|
||||
clk[ZX296702_VOU_AUX_WCLK_MUX] =
|
||||
zx_mux("vou_aux_wclk_mux", vou_main_wclk_sel,
|
||||
ARRAY_SIZE(vou_main_wclk_sel), CLK_MUX, 16, 2);
|
||||
clk[ZX296702_VOU_SCALER_WCLK_MUX] =
|
||||
zx_mux("vou_scaler_wclk_mux", vou_scaler_wclk_sel,
|
||||
ARRAY_SIZE(vou_scaler_wclk_sel), CLK_MUX,
|
||||
18, 2);
|
||||
clk[ZX296702_R2D_ACLK_MUX] =
|
||||
zx_mux("r2d_aclk_mux", decppu_aclk_sel,
|
||||
ARRAY_SIZE(decppu_aclk_sel), CLK_MUX, 20, 2);
|
||||
clk[ZX296702_R2D_WCLK_MUX] =
|
||||
zx_mux("r2d_wclk_mux", r2d_wclk_sel,
|
||||
ARRAY_SIZE(r2d_wclk_sel), CLK_MUX, 22, 2);
|
||||
|
||||
/* other clock */
|
||||
clk[ZX296702_CLK_50] =
|
||||
clk_register_fixed_factor(NULL, "clk_50", "pll_mac_1000M",
|
||||
0, 1, 20);
|
||||
clk[ZX296702_CLK_25] =
|
||||
clk_register_fixed_factor(NULL, "clk_25", "pll_mac_1000M",
|
||||
0, 1, 40);
|
||||
clk[ZX296702_CLK_12] =
|
||||
clk_register_fixed_factor(NULL, "clk_12", "pll_mm1_72M",
|
||||
0, 1, 6);
|
||||
clk[ZX296702_CLK_16M384] =
|
||||
clk_register_fixed_factor(NULL, "clk_16M384",
|
||||
"pll_audio_294M912", 0, 1, 18);
|
||||
clk[ZX296702_CLK_32K768] =
|
||||
clk_register_fixed_factor(NULL, "clk_32K768", "clk_16M384",
|
||||
0, 1, 500);
|
||||
clk[ZX296702_SEC_WCLK_DIV] =
|
||||
zx_divtbl("sec_wclk_div", "pll_lsp_104M", CLK_DIV, 6, 3,
|
||||
sec_wclk_divider);
|
||||
clk[ZX296702_DDR_WCLK_MUX] =
|
||||
zx_mux("ddr_wclk_mux", ddr_wclk_sel,
|
||||
ARRAY_SIZE(ddr_wclk_sel), CLK_MUX, 24, 2);
|
||||
clk[ZX296702_NAND_WCLK_MUX] =
|
||||
zx_mux("nand_wclk_mux", nand_wclk_sel,
|
||||
ARRAY_SIZE(nand_wclk_sel), CLK_MUX, 24, 2);
|
||||
clk[ZX296702_LSP_26_WCLK_MUX] =
|
||||
zx_mux("lsp_26_wclk_mux", lsp_26_wclk_sel,
|
||||
ARRAY_SIZE(lsp_26_wclk_sel), CLK_MUX, 27, 1);
|
||||
|
||||
/* gates */
|
||||
clk[ZX296702_A9_AS0_ACLK] =
|
||||
zx_gate("a9_as0_aclk", "matrix_aclk", CLK_EN0, 0);
|
||||
clk[ZX296702_A9_AS1_ACLK] =
|
||||
zx_gate("a9_as1_aclk", "a9_as1_aclk_div", CLK_EN0, 1);
|
||||
clk[ZX296702_A9_TRACE_CLKIN] =
|
||||
zx_gate("a9_trace_clkin", "a9_trace_clkin_mux", CLK_EN0, 2);
|
||||
clk[ZX296702_DECPPU_AXI_M_ACLK] =
|
||||
zx_gate("decppu_axi_m_aclk", "decppu_aclk_mux", CLK_EN0, 3);
|
||||
clk[ZX296702_DECPPU_AHB_S_HCLK] =
|
||||
zx_gate("decppu_ahb_s_hclk", "main_hclk", CLK_EN0, 4);
|
||||
clk[ZX296702_PPU_AXI_M_ACLK] =
|
||||
zx_gate("ppu_axi_m_aclk", "ppu_aclk_mux", CLK_EN0, 5);
|
||||
clk[ZX296702_PPU_AHB_S_HCLK] =
|
||||
zx_gate("ppu_ahb_s_hclk", "main_hclk", CLK_EN0, 6);
|
||||
clk[ZX296702_VOU_AXI_M_ACLK] =
|
||||
zx_gate("vou_axi_m_aclk", "vou_aclk_mux", CLK_EN0, 7);
|
||||
clk[ZX296702_VOU_APB_PCLK] =
|
||||
zx_gate("vou_apb_pclk", "main_pclk", CLK_EN0, 8);
|
||||
clk[ZX296702_VOU_MAIN_CHANNEL_WCLK] =
|
||||
zx_gate("vou_main_channel_wclk", "vou_main_wclk_mux",
|
||||
CLK_EN0, 9);
|
||||
clk[ZX296702_VOU_AUX_CHANNEL_WCLK] =
|
||||
zx_gate("vou_aux_channel_wclk", "vou_aux_wclk_mux",
|
||||
CLK_EN0, 10);
|
||||
clk[ZX296702_VOU_HDMI_OSCLK_CEC] =
|
||||
zx_gate("vou_hdmi_osclk_cec", "clk_2", CLK_EN0, 11);
|
||||
clk[ZX296702_VOU_SCALER_WCLK] =
|
||||
zx_gate("vou_scaler_wclk", "vou_scaler_wclk_mux", CLK_EN0, 12);
|
||||
clk[ZX296702_MALI400_AXI_M_ACLK] =
|
||||
zx_gate("mali400_axi_m_aclk", "mali400_aclk_mux", CLK_EN0, 13);
|
||||
clk[ZX296702_MALI400_APB_PCLK] =
|
||||
zx_gate("mali400_apb_pclk", "main_pclk", CLK_EN0, 14);
|
||||
clk[ZX296702_R2D_WCLK] =
|
||||
zx_gate("r2d_wclk", "r2d_wclk_mux", CLK_EN0, 15);
|
||||
clk[ZX296702_R2D_AXI_M_ACLK] =
|
||||
zx_gate("r2d_axi_m_aclk", "r2d_aclk_mux", CLK_EN0, 16);
|
||||
clk[ZX296702_R2D_AHB_HCLK] =
|
||||
zx_gate("r2d_ahb_hclk", "main_hclk", CLK_EN0, 17);
|
||||
clk[ZX296702_DDR3_AXI_S0_ACLK] =
|
||||
zx_gate("ddr3_axi_s0_aclk", "matrix_aclk", CLK_EN0, 18);
|
||||
clk[ZX296702_DDR3_APB_PCLK] =
|
||||
zx_gate("ddr3_apb_pclk", "main_pclk", CLK_EN0, 19);
|
||||
clk[ZX296702_DDR3_WCLK] =
|
||||
zx_gate("ddr3_wclk", "ddr_wclk_mux", CLK_EN0, 20);
|
||||
clk[ZX296702_USB20_0_AHB_HCLK] =
|
||||
zx_gate("usb20_0_ahb_hclk", "main_hclk", CLK_EN0, 21);
|
||||
clk[ZX296702_USB20_0_EXTREFCLK] =
|
||||
zx_gate("usb20_0_extrefclk", "clk_12", CLK_EN0, 22);
|
||||
clk[ZX296702_USB20_1_AHB_HCLK] =
|
||||
zx_gate("usb20_1_ahb_hclk", "main_hclk", CLK_EN0, 23);
|
||||
clk[ZX296702_USB20_1_EXTREFCLK] =
|
||||
zx_gate("usb20_1_extrefclk", "clk_12", CLK_EN0, 24);
|
||||
clk[ZX296702_USB20_2_AHB_HCLK] =
|
||||
zx_gate("usb20_2_ahb_hclk", "main_hclk", CLK_EN0, 25);
|
||||
clk[ZX296702_USB20_2_EXTREFCLK] =
|
||||
zx_gate("usb20_2_extrefclk", "clk_12", CLK_EN0, 26);
|
||||
clk[ZX296702_GMAC_AXI_M_ACLK] =
|
||||
zx_gate("gmac_axi_m_aclk", "matrix_aclk", CLK_EN0, 27);
|
||||
clk[ZX296702_GMAC_APB_PCLK] =
|
||||
zx_gate("gmac_apb_pclk", "main_pclk", CLK_EN0, 28);
|
||||
clk[ZX296702_GMAC_125_CLKIN] =
|
||||
zx_gate("gmac_125_clkin", "clk_125", CLK_EN0, 29);
|
||||
clk[ZX296702_GMAC_RMII_CLKIN] =
|
||||
zx_gate("gmac_rmii_clkin", "clk_50", CLK_EN0, 30);
|
||||
clk[ZX296702_GMAC_25M_CLK] =
|
||||
zx_gate("gmac_25M_clk", "clk_25", CLK_EN0, 31);
|
||||
clk[ZX296702_NANDFLASH_AHB_HCLK] =
|
||||
zx_gate("nandflash_ahb_hclk", "main_hclk", CLK_EN1, 0);
|
||||
clk[ZX296702_NANDFLASH_WCLK] =
|
||||
zx_gate("nandflash_wclk", "nand_wclk_mux", CLK_EN1, 1);
|
||||
clk[ZX296702_LSP0_APB_PCLK] =
|
||||
zx_gate("lsp0_apb_pclk", "main_pclk", CLK_EN1, 2);
|
||||
clk[ZX296702_LSP0_AHB_HCLK] =
|
||||
zx_gate("lsp0_ahb_hclk", "main_hclk", CLK_EN1, 3);
|
||||
clk[ZX296702_LSP0_26M_WCLK] =
|
||||
zx_gate("lsp0_26M_wclk", "lsp_26_wclk_mux", CLK_EN1, 4);
|
||||
clk[ZX296702_LSP0_104M_WCLK] =
|
||||
zx_gate("lsp0_104M_wclk", "pll_lsp_104M", CLK_EN1, 5);
|
||||
clk[ZX296702_LSP0_16M384_WCLK] =
|
||||
zx_gate("lsp0_16M384_wclk", "clk_16M384", CLK_EN1, 6);
|
||||
clk[ZX296702_LSP1_APB_PCLK] =
|
||||
zx_gate("lsp1_apb_pclk", "main_pclk", CLK_EN1, 7);
|
||||
/* FIXME: wclk enable bit is bit8. We hack it as reserved 31 for
|
||||
* UART does not work after parent clk is disabled/enabled */
|
||||
clk[ZX296702_LSP1_26M_WCLK] =
|
||||
zx_gate("lsp1_26M_wclk", "lsp_26_wclk_mux", CLK_EN1, 31);
|
||||
clk[ZX296702_LSP1_104M_WCLK] =
|
||||
zx_gate("lsp1_104M_wclk", "pll_lsp_104M", CLK_EN1, 9);
|
||||
clk[ZX296702_LSP1_32K_CLK] =
|
||||
zx_gate("lsp1_32K_clk", "clk_32K768", CLK_EN1, 10);
|
||||
clk[ZX296702_AON_HCLK] =
|
||||
zx_gate("aon_hclk", "main_hclk", CLK_EN1, 11);
|
||||
clk[ZX296702_SYS_CTRL_PCLK] =
|
||||
zx_gate("sys_ctrl_pclk", "main_pclk", CLK_EN1, 12);
|
||||
clk[ZX296702_DMA_PCLK] =
|
||||
zx_gate("dma_pclk", "main_pclk", CLK_EN1, 13);
|
||||
clk[ZX296702_DMA_ACLK] =
|
||||
zx_gate("dma_aclk", "matrix_aclk", CLK_EN1, 14);
|
||||
clk[ZX296702_SEC_HCLK] =
|
||||
zx_gate("sec_hclk", "main_hclk", CLK_EN1, 15);
|
||||
clk[ZX296702_AES_WCLK] =
|
||||
zx_gate("aes_wclk", "sec_wclk_div", CLK_EN1, 16);
|
||||
clk[ZX296702_DES_WCLK] =
|
||||
zx_gate("des_wclk", "sec_wclk_div", CLK_EN1, 17);
|
||||
clk[ZX296702_IRAM_ACLK] =
|
||||
zx_gate("iram_aclk", "matrix_aclk", CLK_EN1, 18);
|
||||
clk[ZX296702_IROM_ACLK] =
|
||||
zx_gate("irom_aclk", "matrix_aclk", CLK_EN1, 19);
|
||||
clk[ZX296702_BOOT_CTRL_HCLK] =
|
||||
zx_gate("boot_ctrl_hclk", "main_hclk", CLK_EN1, 20);
|
||||
clk[ZX296702_EFUSE_CLK_30] =
|
||||
zx_gate("efuse_clk_30", "osc", CLK_EN1, 21);
|
||||
|
||||
/* TODO: add VOU Local clocks */
|
||||
clk[ZX296702_VOU_MAIN_CHANNEL_DIV] =
|
||||
zx_div("vou_main_channel_div", "vou_main_channel_wclk",
|
||||
VOU_LOCAL_DIV2_SET, 1, 1);
|
||||
clk[ZX296702_VOU_AUX_CHANNEL_DIV] =
|
||||
zx_div("vou_aux_channel_div", "vou_aux_channel_wclk",
|
||||
VOU_LOCAL_DIV2_SET, 0, 1);
|
||||
clk[ZX296702_VOU_TV_ENC_HD_DIV] =
|
||||
zx_div("vou_tv_enc_hd_div", "vou_tv_enc_hd_mux",
|
||||
VOU_LOCAL_DIV2_SET, 3, 1);
|
||||
clk[ZX296702_VOU_TV_ENC_SD_DIV] =
|
||||
zx_div("vou_tv_enc_sd_div", "vou_tv_enc_sd_mux",
|
||||
VOU_LOCAL_DIV2_SET, 2, 1);
|
||||
clk[ZX296702_VL0_MUX] =
|
||||
zx_mux("vl0_mux", vl0_sel, ARRAY_SIZE(vl0_sel),
|
||||
VOU_LOCAL_CLKSEL, 8, 1);
|
||||
clk[ZX296702_VL1_MUX] =
|
||||
zx_mux("vl1_mux", vl0_sel, ARRAY_SIZE(vl0_sel),
|
||||
VOU_LOCAL_CLKSEL, 9, 1);
|
||||
clk[ZX296702_VL2_MUX] =
|
||||
zx_mux("vl2_mux", vl0_sel, ARRAY_SIZE(vl0_sel),
|
||||
VOU_LOCAL_CLKSEL, 10, 1);
|
||||
clk[ZX296702_GL0_MUX] =
|
||||
zx_mux("gl0_mux", vl0_sel, ARRAY_SIZE(vl0_sel),
|
||||
VOU_LOCAL_CLKSEL, 5, 1);
|
||||
clk[ZX296702_GL1_MUX] =
|
||||
zx_mux("gl1_mux", vl0_sel, ARRAY_SIZE(vl0_sel),
|
||||
VOU_LOCAL_CLKSEL, 6, 1);
|
||||
clk[ZX296702_GL2_MUX] =
|
||||
zx_mux("gl2_mux", vl0_sel, ARRAY_SIZE(vl0_sel),
|
||||
VOU_LOCAL_CLKSEL, 7, 1);
|
||||
clk[ZX296702_WB_MUX] =
|
||||
zx_mux("wb_mux", vl0_sel, ARRAY_SIZE(vl0_sel),
|
||||
VOU_LOCAL_CLKSEL, 11, 1);
|
||||
clk[ZX296702_HDMI_MUX] =
|
||||
zx_mux("hdmi_mux", hdmi_sel, ARRAY_SIZE(hdmi_sel),
|
||||
VOU_LOCAL_CLKSEL, 4, 1);
|
||||
clk[ZX296702_VOU_TV_ENC_HD_MUX] =
|
||||
zx_mux("vou_tv_enc_hd_mux", hdmi_sel, ARRAY_SIZE(hdmi_sel),
|
||||
VOU_LOCAL_CLKSEL, 3, 1);
|
||||
clk[ZX296702_VOU_TV_ENC_SD_MUX] =
|
||||
zx_mux("vou_tv_enc_sd_mux", hdmi_sel, ARRAY_SIZE(hdmi_sel),
|
||||
VOU_LOCAL_CLKSEL, 2, 1);
|
||||
clk[ZX296702_VL0_CLK] =
|
||||
zx_gate("vl0_clk", "vl0_mux", VOU_LOCAL_CLKEN, 8);
|
||||
clk[ZX296702_VL1_CLK] =
|
||||
zx_gate("vl1_clk", "vl1_mux", VOU_LOCAL_CLKEN, 9);
|
||||
clk[ZX296702_VL2_CLK] =
|
||||
zx_gate("vl2_clk", "vl2_mux", VOU_LOCAL_CLKEN, 10);
|
||||
clk[ZX296702_GL0_CLK] =
|
||||
zx_gate("gl0_clk", "gl0_mux", VOU_LOCAL_CLKEN, 5);
|
||||
clk[ZX296702_GL1_CLK] =
|
||||
zx_gate("gl1_clk", "gl1_mux", VOU_LOCAL_CLKEN, 6);
|
||||
clk[ZX296702_GL2_CLK] =
|
||||
zx_gate("gl2_clk", "gl2_mux", VOU_LOCAL_CLKEN, 7);
|
||||
clk[ZX296702_WB_CLK] =
|
||||
zx_gate("wb_clk", "wb_mux", VOU_LOCAL_CLKEN, 11);
|
||||
clk[ZX296702_CL_CLK] =
|
||||
zx_gate("cl_clk", "vou_main_channel_div", VOU_LOCAL_CLKEN, 12);
|
||||
clk[ZX296702_MAIN_MIX_CLK] =
|
||||
zx_gate("main_mix_clk", "vou_main_channel_div",
|
||||
VOU_LOCAL_CLKEN, 4);
|
||||
clk[ZX296702_AUX_MIX_CLK] =
|
||||
zx_gate("aux_mix_clk", "vou_aux_channel_div",
|
||||
VOU_LOCAL_CLKEN, 3);
|
||||
clk[ZX296702_HDMI_CLK] =
|
||||
zx_gate("hdmi_clk", "hdmi_mux", VOU_LOCAL_CLKEN, 2);
|
||||
clk[ZX296702_VOU_TV_ENC_HD_DAC_CLK] =
|
||||
zx_gate("vou_tv_enc_hd_dac_clk", "vou_tv_enc_hd_div",
|
||||
VOU_LOCAL_CLKEN, 1);
|
||||
clk[ZX296702_VOU_TV_ENC_SD_DAC_CLK] =
|
||||
zx_gate("vou_tv_enc_sd_dac_clk", "vou_tv_enc_sd_div",
|
||||
VOU_LOCAL_CLKEN, 0);
|
||||
|
||||
/* CA9 PERIPHCLK = a9_wclk / 2 */
|
||||
clk[ZX296702_A9_PERIPHCLK] =
|
||||
clk_register_fixed_factor(NULL, "a9_periphclk", "a9_wclk",
|
||||
0, 1, 2);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(topclk); i++) {
|
||||
if (IS_ERR(clk[i])) {
|
||||
pr_err("zx296702 clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clk[i]));
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
topclk_data.clks = topclk;
|
||||
topclk_data.clk_num = ARRAY_SIZE(topclk);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &topclk_data);
|
||||
}
|
||||
CLK_OF_DECLARE(zx296702_top_clk, "zte,zx296702-topcrm-clk",
|
||||
zx296702_top_clocks_init);
|
||||
|
||||
static void __init zx296702_lsp0_clocks_init(struct device_node *np)
|
||||
{
|
||||
struct clk **clk = lsp0clk;
|
||||
int i;
|
||||
|
||||
lsp0crpm_base = of_iomap(np, 0);
|
||||
WARN_ON(!lsp0crpm_base);
|
||||
|
||||
/* SDMMC1 */
|
||||
clk[ZX296702_SDMMC1_WCLK_MUX] =
|
||||
zx_mux("sdmmc1_wclk_mux", sdmmc1_wclk_sel,
|
||||
ARRAY_SIZE(sdmmc1_wclk_sel), CLK_SDMMC1, 4, 1);
|
||||
clk[ZX296702_SDMMC1_WCLK_DIV] =
|
||||
zx_div("sdmmc1_wclk_div", "sdmmc1_wclk_mux", CLK_SDMMC1, 12, 4);
|
||||
clk[ZX296702_SDMMC1_WCLK] =
|
||||
zx_gate("sdmmc1_wclk", "sdmmc1_wclk_div", CLK_SDMMC1, 1);
|
||||
clk[ZX296702_SDMMC1_PCLK] =
|
||||
zx_gate("sdmmc1_pclk", "lsp0_apb_pclk", CLK_SDMMC1, 0);
|
||||
|
||||
clk[ZX296702_GPIO_CLK] =
|
||||
zx_gate("gpio_clk", "lsp0_apb_pclk", CLK_GPIO, 0);
|
||||
|
||||
/* SPDIF */
|
||||
clk[ZX296702_SPDIF0_WCLK_MUX] =
|
||||
zx_mux("spdif0_wclk_mux", spdif0_wclk_sel,
|
||||
ARRAY_SIZE(spdif0_wclk_sel), CLK_SPDIF0, 4, 1);
|
||||
clk[ZX296702_SPDIF0_WCLK] =
|
||||
zx_gate("spdif0_wclk", "spdif0_wclk_mux", CLK_SPDIF0, 1);
|
||||
clk[ZX296702_SPDIF0_PCLK] =
|
||||
zx_gate("spdif0_pclk", "lsp0_apb_pclk", CLK_SPDIF0, 0);
|
||||
|
||||
clk[ZX296702_SPDIF0_DIV] =
|
||||
clk_register_zx_audio("spdif0_div", "spdif0_wclk", 0,
|
||||
SPDIF0_DIV);
|
||||
|
||||
/* I2S */
|
||||
clk[ZX296702_I2S0_WCLK_MUX] =
|
||||
zx_mux("i2s0_wclk_mux", i2s_wclk_sel,
|
||||
ARRAY_SIZE(i2s_wclk_sel), CLK_I2S0, 4, 1);
|
||||
clk[ZX296702_I2S0_WCLK] =
|
||||
zx_gate("i2s0_wclk", "i2s0_wclk_mux", CLK_I2S0, 1);
|
||||
clk[ZX296702_I2S0_PCLK] =
|
||||
zx_gate("i2s0_pclk", "lsp0_apb_pclk", CLK_I2S0, 0);
|
||||
|
||||
clk[ZX296702_I2S0_DIV] =
|
||||
clk_register_zx_audio("i2s0_div", "i2s0_wclk", 0, I2S0_DIV);
|
||||
|
||||
clk[ZX296702_I2S1_WCLK_MUX] =
|
||||
zx_mux("i2s1_wclk_mux", i2s_wclk_sel,
|
||||
ARRAY_SIZE(i2s_wclk_sel), CLK_I2S1, 4, 1);
|
||||
clk[ZX296702_I2S1_WCLK] =
|
||||
zx_gate("i2s1_wclk", "i2s1_wclk_mux", CLK_I2S1, 1);
|
||||
clk[ZX296702_I2S1_PCLK] =
|
||||
zx_gate("i2s1_pclk", "lsp0_apb_pclk", CLK_I2S1, 0);
|
||||
|
||||
clk[ZX296702_I2S1_DIV] =
|
||||
clk_register_zx_audio("i2s1_div", "i2s1_wclk", 0, I2S1_DIV);
|
||||
|
||||
clk[ZX296702_I2S2_WCLK_MUX] =
|
||||
zx_mux("i2s2_wclk_mux", i2s_wclk_sel,
|
||||
ARRAY_SIZE(i2s_wclk_sel), CLK_I2S2, 4, 1);
|
||||
clk[ZX296702_I2S2_WCLK] =
|
||||
zx_gate("i2s2_wclk", "i2s2_wclk_mux", CLK_I2S2, 1);
|
||||
clk[ZX296702_I2S2_PCLK] =
|
||||
zx_gate("i2s2_pclk", "lsp0_apb_pclk", CLK_I2S2, 0);
|
||||
|
||||
clk[ZX296702_I2S2_DIV] =
|
||||
clk_register_zx_audio("i2s2_div", "i2s2_wclk", 0, I2S2_DIV);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(lsp0clk); i++) {
|
||||
if (IS_ERR(clk[i])) {
|
||||
pr_err("zx296702 clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clk[i]));
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
lsp0clk_data.clks = lsp0clk;
|
||||
lsp0clk_data.clk_num = ARRAY_SIZE(lsp0clk);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &lsp0clk_data);
|
||||
}
|
||||
CLK_OF_DECLARE(zx296702_lsp0_clk, "zte,zx296702-lsp0crpm-clk",
|
||||
zx296702_lsp0_clocks_init);
|
||||
|
||||
static void __init zx296702_lsp1_clocks_init(struct device_node *np)
|
||||
{
|
||||
struct clk **clk = lsp1clk;
|
||||
int i;
|
||||
|
||||
lsp1crpm_base = of_iomap(np, 0);
|
||||
WARN_ON(!lsp1crpm_base);
|
||||
|
||||
/* UART0 */
|
||||
clk[ZX296702_UART0_WCLK_MUX] =
|
||||
zx_mux("uart0_wclk_mux", uart_wclk_sel,
|
||||
ARRAY_SIZE(uart_wclk_sel), CLK_UART0, 4, 1);
|
||||
/* FIXME: uart wclk enable bit is bit1 in. We hack it as reserved 31 for
|
||||
* UART does not work after parent clk is disabled/enabled */
|
||||
clk[ZX296702_UART0_WCLK] =
|
||||
zx_gate("uart0_wclk", "uart0_wclk_mux", CLK_UART0, 31);
|
||||
clk[ZX296702_UART0_PCLK] =
|
||||
zx_gate("uart0_pclk", "lsp1_apb_pclk", CLK_UART0, 0);
|
||||
|
||||
/* UART1 */
|
||||
clk[ZX296702_UART1_WCLK_MUX] =
|
||||
zx_mux("uart1_wclk_mux", uart_wclk_sel,
|
||||
ARRAY_SIZE(uart_wclk_sel), CLK_UART1, 4, 1);
|
||||
clk[ZX296702_UART1_WCLK] =
|
||||
zx_gate("uart1_wclk", "uart1_wclk_mux", CLK_UART1, 1);
|
||||
clk[ZX296702_UART1_PCLK] =
|
||||
zx_gate("uart1_pclk", "lsp1_apb_pclk", CLK_UART1, 0);
|
||||
|
||||
/* SDMMC0 */
|
||||
clk[ZX296702_SDMMC0_WCLK_MUX] =
|
||||
zx_mux("sdmmc0_wclk_mux", sdmmc0_wclk_sel,
|
||||
ARRAY_SIZE(sdmmc0_wclk_sel), CLK_SDMMC0, 4, 1);
|
||||
clk[ZX296702_SDMMC0_WCLK_DIV] =
|
||||
zx_div("sdmmc0_wclk_div", "sdmmc0_wclk_mux", CLK_SDMMC0, 12, 4);
|
||||
clk[ZX296702_SDMMC0_WCLK] =
|
||||
zx_gate("sdmmc0_wclk", "sdmmc0_wclk_div", CLK_SDMMC0, 1);
|
||||
clk[ZX296702_SDMMC0_PCLK] =
|
||||
zx_gate("sdmmc0_pclk", "lsp1_apb_pclk", CLK_SDMMC0, 0);
|
||||
|
||||
clk[ZX296702_SPDIF1_WCLK_MUX] =
|
||||
zx_mux("spdif1_wclk_mux", spdif1_wclk_sel,
|
||||
ARRAY_SIZE(spdif1_wclk_sel), CLK_SPDIF1, 4, 1);
|
||||
clk[ZX296702_SPDIF1_WCLK] =
|
||||
zx_gate("spdif1_wclk", "spdif1_wclk_mux", CLK_SPDIF1, 1);
|
||||
clk[ZX296702_SPDIF1_PCLK] =
|
||||
zx_gate("spdif1_pclk", "lsp1_apb_pclk", CLK_SPDIF1, 0);
|
||||
|
||||
clk[ZX296702_SPDIF1_DIV] =
|
||||
clk_register_zx_audio("spdif1_div", "spdif1_wclk", 0,
|
||||
SPDIF1_DIV);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(lsp1clk); i++) {
|
||||
if (IS_ERR(clk[i])) {
|
||||
pr_err("zx296702 clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clk[i]));
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
lsp1clk_data.clks = lsp1clk;
|
||||
lsp1clk_data.clk_num = ARRAY_SIZE(lsp1clk);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &lsp1clk_data);
|
||||
}
|
||||
CLK_OF_DECLARE(zx296702_lsp1_clk, "zte,zx296702-lsp1crpm-clk",
|
||||
zx296702_lsp1_clocks_init);
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,446 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright 2014 Linaro Ltd.
|
||||
* Copyright (C) 2014 ZTE Corporation.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/gcd.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/iopoll.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <asm/div64.h>
|
||||
|
||||
#include "clk.h"
|
||||
|
||||
#define to_clk_zx_pll(_hw) container_of(_hw, struct clk_zx_pll, hw)
|
||||
#define to_clk_zx_audio(_hw) container_of(_hw, struct clk_zx_audio, hw)
|
||||
|
||||
#define CFG0_CFG1_OFFSET 4
|
||||
#define LOCK_FLAG 30
|
||||
#define POWER_DOWN 31
|
||||
|
||||
static int rate_to_idx(struct clk_zx_pll *zx_pll, unsigned long rate)
|
||||
{
|
||||
const struct zx_pll_config *config = zx_pll->lookup_table;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < zx_pll->count; i++) {
|
||||
if (config[i].rate > rate)
|
||||
return i > 0 ? i - 1 : 0;
|
||||
|
||||
if (config[i].rate == rate)
|
||||
return i;
|
||||
}
|
||||
|
||||
return i - 1;
|
||||
}
|
||||
|
||||
static int hw_to_idx(struct clk_zx_pll *zx_pll)
|
||||
{
|
||||
const struct zx_pll_config *config = zx_pll->lookup_table;
|
||||
u32 hw_cfg0, hw_cfg1;
|
||||
int i;
|
||||
|
||||
hw_cfg0 = readl_relaxed(zx_pll->reg_base);
|
||||
hw_cfg1 = readl_relaxed(zx_pll->reg_base + CFG0_CFG1_OFFSET);
|
||||
|
||||
/* For matching the value in lookup table */
|
||||
hw_cfg0 &= ~BIT(zx_pll->lock_bit);
|
||||
|
||||
/* Check availability of pd_bit */
|
||||
if (zx_pll->pd_bit < 32)
|
||||
hw_cfg0 |= BIT(zx_pll->pd_bit);
|
||||
|
||||
for (i = 0; i < zx_pll->count; i++) {
|
||||
if (hw_cfg0 == config[i].cfg0 && hw_cfg1 == config[i].cfg1)
|
||||
return i;
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static unsigned long zx_pll_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);
|
||||
int idx;
|
||||
|
||||
idx = hw_to_idx(zx_pll);
|
||||
if (unlikely(idx == -EINVAL))
|
||||
return 0;
|
||||
|
||||
return zx_pll->lookup_table[idx].rate;
|
||||
}
|
||||
|
||||
static long zx_pll_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *prate)
|
||||
{
|
||||
struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);
|
||||
int idx;
|
||||
|
||||
idx = rate_to_idx(zx_pll, rate);
|
||||
|
||||
return zx_pll->lookup_table[idx].rate;
|
||||
}
|
||||
|
||||
static int zx_pll_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
/* Assume current cpu is not running on current PLL */
|
||||
struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);
|
||||
const struct zx_pll_config *config;
|
||||
int idx;
|
||||
|
||||
idx = rate_to_idx(zx_pll, rate);
|
||||
config = &zx_pll->lookup_table[idx];
|
||||
|
||||
writel_relaxed(config->cfg0, zx_pll->reg_base);
|
||||
writel_relaxed(config->cfg1, zx_pll->reg_base + CFG0_CFG1_OFFSET);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int zx_pll_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);
|
||||
u32 reg;
|
||||
|
||||
/* If pd_bit is not available, simply return success. */
|
||||
if (zx_pll->pd_bit > 31)
|
||||
return 0;
|
||||
|
||||
reg = readl_relaxed(zx_pll->reg_base);
|
||||
writel_relaxed(reg & ~BIT(zx_pll->pd_bit), zx_pll->reg_base);
|
||||
|
||||
return readl_relaxed_poll_timeout(zx_pll->reg_base, reg,
|
||||
reg & BIT(zx_pll->lock_bit), 0, 100);
|
||||
}
|
||||
|
||||
static void zx_pll_disable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);
|
||||
u32 reg;
|
||||
|
||||
if (zx_pll->pd_bit > 31)
|
||||
return;
|
||||
|
||||
reg = readl_relaxed(zx_pll->reg_base);
|
||||
writel_relaxed(reg | BIT(zx_pll->pd_bit), zx_pll->reg_base);
|
||||
}
|
||||
|
||||
static int zx_pll_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);
|
||||
u32 reg;
|
||||
|
||||
reg = readl_relaxed(zx_pll->reg_base);
|
||||
|
||||
return !(reg & BIT(zx_pll->pd_bit));
|
||||
}
|
||||
|
||||
const struct clk_ops zx_pll_ops = {
|
||||
.recalc_rate = zx_pll_recalc_rate,
|
||||
.round_rate = zx_pll_round_rate,
|
||||
.set_rate = zx_pll_set_rate,
|
||||
.enable = zx_pll_enable,
|
||||
.disable = zx_pll_disable,
|
||||
.is_enabled = zx_pll_is_enabled,
|
||||
};
|
||||
EXPORT_SYMBOL(zx_pll_ops);
|
||||
|
||||
struct clk *clk_register_zx_pll(const char *name, const char *parent_name,
|
||||
unsigned long flags, void __iomem *reg_base,
|
||||
const struct zx_pll_config *lookup_table,
|
||||
int count, spinlock_t *lock)
|
||||
{
|
||||
struct clk_zx_pll *zx_pll;
|
||||
struct clk *clk;
|
||||
struct clk_init_data init;
|
||||
|
||||
zx_pll = kzalloc(sizeof(*zx_pll), GFP_KERNEL);
|
||||
if (!zx_pll)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
init.name = name;
|
||||
init.ops = &zx_pll_ops;
|
||||
init.flags = flags;
|
||||
init.parent_names = parent_name ? &parent_name : NULL;
|
||||
init.num_parents = parent_name ? 1 : 0;
|
||||
|
||||
zx_pll->reg_base = reg_base;
|
||||
zx_pll->lookup_table = lookup_table;
|
||||
zx_pll->count = count;
|
||||
zx_pll->lock_bit = LOCK_FLAG;
|
||||
zx_pll->pd_bit = POWER_DOWN;
|
||||
zx_pll->lock = lock;
|
||||
zx_pll->hw.init = &init;
|
||||
|
||||
clk = clk_register(NULL, &zx_pll->hw);
|
||||
if (IS_ERR(clk))
|
||||
kfree(zx_pll);
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
#define BPAR 1000000
|
||||
static u32 calc_reg(u32 parent_rate, u32 rate)
|
||||
{
|
||||
u32 sel, integ, fra_div, tmp;
|
||||
u64 tmp64 = (u64)parent_rate * BPAR;
|
||||
|
||||
do_div(tmp64, rate);
|
||||
integ = (u32)tmp64 / BPAR;
|
||||
integ = integ >> 1;
|
||||
|
||||
tmp = (u32)tmp64 % BPAR;
|
||||
sel = tmp / BPAR;
|
||||
|
||||
tmp = tmp % BPAR;
|
||||
fra_div = tmp * 0xff / BPAR;
|
||||
tmp = (sel << 24) | (integ << 16) | (0xff << 8) | fra_div;
|
||||
|
||||
/* Set I2S integer divider as 1. This bit is reserved for SPDIF
|
||||
* and do no harm.
|
||||
*/
|
||||
tmp |= BIT(28);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
static u32 calc_rate(u32 reg, u32 parent_rate)
|
||||
{
|
||||
u32 sel, integ, fra_div, tmp;
|
||||
u64 tmp64 = (u64)parent_rate * BPAR;
|
||||
|
||||
tmp = reg;
|
||||
sel = (tmp >> 24) & BIT(0);
|
||||
integ = (tmp >> 16) & 0xff;
|
||||
fra_div = tmp & 0xff;
|
||||
|
||||
tmp = fra_div * BPAR;
|
||||
tmp = tmp / 0xff;
|
||||
tmp += sel * BPAR;
|
||||
tmp += 2 * integ * BPAR;
|
||||
do_div(tmp64, tmp);
|
||||
|
||||
return (u32)tmp64;
|
||||
}
|
||||
|
||||
static unsigned long zx_audio_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_zx_audio *zx_audio = to_clk_zx_audio(hw);
|
||||
u32 reg;
|
||||
|
||||
reg = readl_relaxed(zx_audio->reg_base);
|
||||
return calc_rate(reg, parent_rate);
|
||||
}
|
||||
|
||||
static long zx_audio_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *prate)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
if (rate * 2 > *prate)
|
||||
return -EINVAL;
|
||||
|
||||
reg = calc_reg(*prate, rate);
|
||||
return calc_rate(reg, *prate);
|
||||
}
|
||||
|
||||
static int zx_audio_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_zx_audio *zx_audio = to_clk_zx_audio(hw);
|
||||
u32 reg;
|
||||
|
||||
reg = calc_reg(parent_rate, rate);
|
||||
writel_relaxed(reg, zx_audio->reg_base);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define ZX_AUDIO_EN BIT(25)
|
||||
static int zx_audio_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_zx_audio *zx_audio = to_clk_zx_audio(hw);
|
||||
u32 reg;
|
||||
|
||||
reg = readl_relaxed(zx_audio->reg_base);
|
||||
writel_relaxed(reg & ~ZX_AUDIO_EN, zx_audio->reg_base);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void zx_audio_disable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_zx_audio *zx_audio = to_clk_zx_audio(hw);
|
||||
u32 reg;
|
||||
|
||||
reg = readl_relaxed(zx_audio->reg_base);
|
||||
writel_relaxed(reg | ZX_AUDIO_EN, zx_audio->reg_base);
|
||||
}
|
||||
|
||||
static const struct clk_ops zx_audio_ops = {
|
||||
.recalc_rate = zx_audio_recalc_rate,
|
||||
.round_rate = zx_audio_round_rate,
|
||||
.set_rate = zx_audio_set_rate,
|
||||
.enable = zx_audio_enable,
|
||||
.disable = zx_audio_disable,
|
||||
};
|
||||
|
||||
struct clk *clk_register_zx_audio(const char *name,
|
||||
const char * const parent_name,
|
||||
unsigned long flags,
|
||||
void __iomem *reg_base)
|
||||
{
|
||||
struct clk_zx_audio *zx_audio;
|
||||
struct clk *clk;
|
||||
struct clk_init_data init;
|
||||
|
||||
zx_audio = kzalloc(sizeof(*zx_audio), GFP_KERNEL);
|
||||
if (!zx_audio)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
init.name = name;
|
||||
init.ops = &zx_audio_ops;
|
||||
init.flags = flags;
|
||||
init.parent_names = parent_name ? &parent_name : NULL;
|
||||
init.num_parents = parent_name ? 1 : 0;
|
||||
|
||||
zx_audio->reg_base = reg_base;
|
||||
zx_audio->hw.init = &init;
|
||||
|
||||
clk = clk_register(NULL, &zx_audio->hw);
|
||||
if (IS_ERR(clk))
|
||||
kfree(zx_audio);
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
#define CLK_AUDIO_DIV_FRAC BIT(0)
|
||||
#define CLK_AUDIO_DIV_INT BIT(1)
|
||||
#define CLK_AUDIO_DIV_UNCOMMON BIT(1)
|
||||
|
||||
#define CLK_AUDIO_DIV_FRAC_NSHIFT 16
|
||||
#define CLK_AUDIO_DIV_INT_FRAC_RE BIT(16)
|
||||
#define CLK_AUDIO_DIV_INT_FRAC_MAX (0xffff)
|
||||
#define CLK_AUDIO_DIV_INT_FRAC_MIN (0x2)
|
||||
#define CLK_AUDIO_DIV_INT_INT_SHIFT 24
|
||||
#define CLK_AUDIO_DIV_INT_INT_WIDTH 4
|
||||
|
||||
struct zx_clk_audio_div_table {
|
||||
unsigned long rate;
|
||||
unsigned int int_reg;
|
||||
unsigned int frac_reg;
|
||||
};
|
||||
|
||||
#define to_clk_zx_audio_div(_hw) container_of(_hw, struct clk_zx_audio_divider, hw)
|
||||
|
||||
static unsigned long audio_calc_rate(struct clk_zx_audio_divider *audio_div,
|
||||
u32 reg_frac, u32 reg_int,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
unsigned long rate, m, n;
|
||||
|
||||
m = reg_frac & 0xffff;
|
||||
n = (reg_frac >> 16) & 0xffff;
|
||||
|
||||
m = (reg_int & 0xffff) * n + m;
|
||||
rate = (parent_rate * n) / m;
|
||||
|
||||
return rate;
|
||||
}
|
||||
|
||||
static void audio_calc_reg(struct clk_zx_audio_divider *audio_div,
|
||||
struct zx_clk_audio_div_table *div_table,
|
||||
unsigned long rate, unsigned long parent_rate)
|
||||
{
|
||||
unsigned int reg_int, reg_frac;
|
||||
unsigned long m, n, div;
|
||||
|
||||
reg_int = parent_rate / rate;
|
||||
|
||||
if (reg_int > CLK_AUDIO_DIV_INT_FRAC_MAX)
|
||||
reg_int = CLK_AUDIO_DIV_INT_FRAC_MAX;
|
||||
else if (reg_int < CLK_AUDIO_DIV_INT_FRAC_MIN)
|
||||
reg_int = 0;
|
||||
m = parent_rate - rate * reg_int;
|
||||
n = rate;
|
||||
|
||||
div = gcd(m, n);
|
||||
m = m / div;
|
||||
n = n / div;
|
||||
|
||||
if ((m >> 16) || (n >> 16)) {
|
||||
if (m > n) {
|
||||
n = n * 0xffff / m;
|
||||
m = 0xffff;
|
||||
} else {
|
||||
m = m * 0xffff / n;
|
||||
n = 0xffff;
|
||||
}
|
||||
}
|
||||
reg_frac = m | (n << 16);
|
||||
|
||||
div_table->rate = parent_rate * n / (reg_int * n + m);
|
||||
div_table->int_reg = reg_int;
|
||||
div_table->frac_reg = reg_frac;
|
||||
}
|
||||
|
||||
static unsigned long zx_audio_div_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_zx_audio_divider *zx_audio_div = to_clk_zx_audio_div(hw);
|
||||
u32 reg_frac, reg_int;
|
||||
|
||||
reg_frac = readl_relaxed(zx_audio_div->reg_base);
|
||||
reg_int = readl_relaxed(zx_audio_div->reg_base + 0x4);
|
||||
|
||||
return audio_calc_rate(zx_audio_div, reg_frac, reg_int, parent_rate);
|
||||
}
|
||||
|
||||
static long zx_audio_div_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *prate)
|
||||
{
|
||||
struct clk_zx_audio_divider *zx_audio_div = to_clk_zx_audio_div(hw);
|
||||
struct zx_clk_audio_div_table divt;
|
||||
|
||||
audio_calc_reg(zx_audio_div, &divt, rate, *prate);
|
||||
|
||||
return audio_calc_rate(zx_audio_div, divt.frac_reg, divt.int_reg, *prate);
|
||||
}
|
||||
|
||||
static int zx_audio_div_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_zx_audio_divider *zx_audio_div = to_clk_zx_audio_div(hw);
|
||||
struct zx_clk_audio_div_table divt;
|
||||
unsigned int val;
|
||||
|
||||
audio_calc_reg(zx_audio_div, &divt, rate, parent_rate);
|
||||
if (divt.rate != rate)
|
||||
pr_debug("the real rate is:%ld", divt.rate);
|
||||
|
||||
writel_relaxed(divt.frac_reg, zx_audio_div->reg_base);
|
||||
|
||||
val = readl_relaxed(zx_audio_div->reg_base + 0x4);
|
||||
val &= ~0xffff;
|
||||
val |= divt.int_reg | CLK_AUDIO_DIV_INT_FRAC_RE;
|
||||
writel_relaxed(val, zx_audio_div->reg_base + 0x4);
|
||||
|
||||
mdelay(1);
|
||||
|
||||
val = readl_relaxed(zx_audio_div->reg_base + 0x4);
|
||||
val &= ~CLK_AUDIO_DIV_INT_FRAC_RE;
|
||||
writel_relaxed(val, zx_audio_div->reg_base + 0x4);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct clk_ops zx_audio_div_ops = {
|
||||
.recalc_rate = zx_audio_div_recalc_rate,
|
||||
.round_rate = zx_audio_div_round_rate,
|
||||
.set_rate = zx_audio_div_set_rate,
|
||||
};
|
||||
@ -1,174 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright 2015 Linaro Ltd.
|
||||
* Copyright (C) 2014 ZTE Corporation.
|
||||
*/
|
||||
|
||||
#ifndef __ZTE_CLK_H
|
||||
#define __ZTE_CLK_H
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
#define PNAME(x) static const char *x[]
|
||||
|
||||
struct zx_pll_config {
|
||||
unsigned long rate;
|
||||
u32 cfg0;
|
||||
u32 cfg1;
|
||||
};
|
||||
|
||||
struct clk_zx_pll {
|
||||
struct clk_hw hw;
|
||||
void __iomem *reg_base;
|
||||
const struct zx_pll_config *lookup_table; /* order by rate asc */
|
||||
int count;
|
||||
spinlock_t *lock;
|
||||
u8 pd_bit; /* power down bit */
|
||||
u8 lock_bit; /* pll lock flag bit */
|
||||
};
|
||||
|
||||
#define PLL_RATE(_rate, _cfg0, _cfg1) \
|
||||
{ \
|
||||
.rate = _rate, \
|
||||
.cfg0 = _cfg0, \
|
||||
.cfg1 = _cfg1, \
|
||||
}
|
||||
|
||||
#define ZX_PLL(_name, _parent, _reg, _table, _pd, _lock) \
|
||||
{ \
|
||||
.reg_base = (void __iomem *) _reg, \
|
||||
.lookup_table = _table, \
|
||||
.count = ARRAY_SIZE(_table), \
|
||||
.pd_bit = _pd, \
|
||||
.lock_bit = _lock, \
|
||||
.hw.init = CLK_HW_INIT(_name, _parent, &zx_pll_ops, \
|
||||
CLK_GET_RATE_NOCACHE), \
|
||||
}
|
||||
|
||||
/*
|
||||
* The pd_bit is not available on ZX296718, so let's pass something
|
||||
* bigger than 31, e.g. 0xff, to indicate that.
|
||||
*/
|
||||
#define ZX296718_PLL(_name, _parent, _reg, _table) \
|
||||
ZX_PLL(_name, _parent, _reg, _table, 0xff, 30)
|
||||
|
||||
struct zx_clk_gate {
|
||||
struct clk_gate gate;
|
||||
u16 id;
|
||||
};
|
||||
|
||||
#define GATE(_id, _name, _parent, _reg, _bit, _flag, _gflags) \
|
||||
{ \
|
||||
.gate = { \
|
||||
.reg = (void __iomem *) _reg, \
|
||||
.bit_idx = (_bit), \
|
||||
.flags = _gflags, \
|
||||
.lock = &clk_lock, \
|
||||
.hw.init = CLK_HW_INIT(_name, \
|
||||
_parent, \
|
||||
&clk_gate_ops, \
|
||||
_flag | CLK_IGNORE_UNUSED), \
|
||||
}, \
|
||||
.id = _id, \
|
||||
}
|
||||
|
||||
struct zx_clk_fixed_factor {
|
||||
struct clk_fixed_factor factor;
|
||||
u16 id;
|
||||
};
|
||||
|
||||
#define FFACTOR(_id, _name, _parent, _mult, _div, _flag) \
|
||||
{ \
|
||||
.factor = { \
|
||||
.div = _div, \
|
||||
.mult = _mult, \
|
||||
.hw.init = CLK_HW_INIT(_name, \
|
||||
_parent, \
|
||||
&clk_fixed_factor_ops, \
|
||||
_flag), \
|
||||
}, \
|
||||
.id = _id, \
|
||||
}
|
||||
|
||||
struct zx_clk_mux {
|
||||
struct clk_mux mux;
|
||||
u16 id;
|
||||
};
|
||||
|
||||
#define MUX_F(_id, _name, _parent, _reg, _shift, _width, _flag, _mflag) \
|
||||
{ \
|
||||
.mux = { \
|
||||
.reg = (void __iomem *) _reg, \
|
||||
.mask = BIT(_width) - 1, \
|
||||
.shift = _shift, \
|
||||
.flags = _mflag, \
|
||||
.lock = &clk_lock, \
|
||||
.hw.init = CLK_HW_INIT_PARENTS(_name, \
|
||||
_parent, \
|
||||
&clk_mux_ops, \
|
||||
_flag), \
|
||||
}, \
|
||||
.id = _id, \
|
||||
}
|
||||
|
||||
#define MUX(_id, _name, _parent, _reg, _shift, _width) \
|
||||
MUX_F(_id, _name, _parent, _reg, _shift, _width, 0, 0)
|
||||
|
||||
struct zx_clk_div {
|
||||
struct clk_divider div;
|
||||
u16 id;
|
||||
};
|
||||
|
||||
#define DIV_T(_id, _name, _parent, _reg, _shift, _width, _flag, _table) \
|
||||
{ \
|
||||
.div = { \
|
||||
.reg = (void __iomem *) _reg, \
|
||||
.shift = _shift, \
|
||||
.width = _width, \
|
||||
.flags = 0, \
|
||||
.table = _table, \
|
||||
.lock = &clk_lock, \
|
||||
.hw.init = CLK_HW_INIT(_name, \
|
||||
_parent, \
|
||||
&clk_divider_ops, \
|
||||
_flag), \
|
||||
}, \
|
||||
.id = _id, \
|
||||
}
|
||||
|
||||
struct clk_zx_audio_divider {
|
||||
struct clk_hw hw;
|
||||
void __iomem *reg_base;
|
||||
unsigned int rate_count;
|
||||
spinlock_t *lock;
|
||||
u16 id;
|
||||
};
|
||||
|
||||
#define AUDIO_DIV(_id, _name, _parent, _reg) \
|
||||
{ \
|
||||
.reg_base = (void __iomem *) _reg, \
|
||||
.lock = &clk_lock, \
|
||||
.hw.init = CLK_HW_INIT(_name, \
|
||||
_parent, \
|
||||
&zx_audio_div_ops, \
|
||||
0), \
|
||||
.id = _id, \
|
||||
}
|
||||
|
||||
struct clk *clk_register_zx_pll(const char *name, const char *parent_name,
|
||||
unsigned long flags, void __iomem *reg_base,
|
||||
const struct zx_pll_config *lookup_table, int count, spinlock_t *lock);
|
||||
|
||||
struct clk_zx_audio {
|
||||
struct clk_hw hw;
|
||||
void __iomem *reg_base;
|
||||
};
|
||||
|
||||
struct clk *clk_register_zx_audio(const char *name,
|
||||
const char * const parent_name,
|
||||
unsigned long flags, void __iomem *reg_base);
|
||||
|
||||
extern const struct clk_ops zx_pll_ops;
|
||||
extern const struct clk_ops zx_audio_div_ops;
|
||||
|
||||
#endif
|
||||
@ -1,180 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright 2014 Linaro Ltd.
|
||||
* Copyright (C) 2014 ZTE Corporation.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_ZX296702_H
|
||||
#define __DT_BINDINGS_CLOCK_ZX296702_H
|
||||
|
||||
#define ZX296702_OSC 0
|
||||
#define ZX296702_PLL_A9 1
|
||||
#define ZX296702_PLL_A9_350M 2
|
||||
#define ZX296702_PLL_MAC_1000M 3
|
||||
#define ZX296702_PLL_MAC_333M 4
|
||||
#define ZX296702_PLL_MM0_1188M 5
|
||||
#define ZX296702_PLL_MM0_396M 6
|
||||
#define ZX296702_PLL_MM0_198M 7
|
||||
#define ZX296702_PLL_MM1_108M 8
|
||||
#define ZX296702_PLL_MM1_72M 9
|
||||
#define ZX296702_PLL_MM1_54M 10
|
||||
#define ZX296702_PLL_LSP_104M 11
|
||||
#define ZX296702_PLL_LSP_26M 12
|
||||
#define ZX296702_PLL_AUDIO_294M912 13
|
||||
#define ZX296702_PLL_DDR_266M 14
|
||||
#define ZX296702_CLK_148M5 15
|
||||
#define ZX296702_MATRIX_ACLK 16
|
||||
#define ZX296702_MAIN_HCLK 17
|
||||
#define ZX296702_MAIN_PCLK 18
|
||||
#define ZX296702_CLK_500 19
|
||||
#define ZX296702_CLK_250 20
|
||||
#define ZX296702_CLK_125 21
|
||||
#define ZX296702_CLK_74M25 22
|
||||
#define ZX296702_A9_WCLK 23
|
||||
#define ZX296702_A9_AS1_ACLK_MUX 24
|
||||
#define ZX296702_A9_TRACE_CLKIN_MUX 25
|
||||
#define ZX296702_A9_AS1_ACLK_DIV 26
|
||||
#define ZX296702_CLK_2 27
|
||||
#define ZX296702_CLK_27 28
|
||||
#define ZX296702_DECPPU_ACLK_MUX 29
|
||||
#define ZX296702_PPU_ACLK_MUX 30
|
||||
#define ZX296702_MALI400_ACLK_MUX 31
|
||||
#define ZX296702_VOU_ACLK_MUX 32
|
||||
#define ZX296702_VOU_MAIN_WCLK_MUX 33
|
||||
#define ZX296702_VOU_AUX_WCLK_MUX 34
|
||||
#define ZX296702_VOU_SCALER_WCLK_MUX 35
|
||||
#define ZX296702_R2D_ACLK_MUX 36
|
||||
#define ZX296702_R2D_WCLK_MUX 37
|
||||
#define ZX296702_CLK_50 38
|
||||
#define ZX296702_CLK_25 39
|
||||
#define ZX296702_CLK_12 40
|
||||
#define ZX296702_CLK_16M384 41
|
||||
#define ZX296702_CLK_32K768 42
|
||||
#define ZX296702_SEC_WCLK_DIV 43
|
||||
#define ZX296702_DDR_WCLK_MUX 44
|
||||
#define ZX296702_NAND_WCLK_MUX 45
|
||||
#define ZX296702_LSP_26_WCLK_MUX 46
|
||||
#define ZX296702_A9_AS0_ACLK 47
|
||||
#define ZX296702_A9_AS1_ACLK 48
|
||||
#define ZX296702_A9_TRACE_CLKIN 49
|
||||
#define ZX296702_DECPPU_AXI_M_ACLK 50
|
||||
#define ZX296702_DECPPU_AHB_S_HCLK 51
|
||||
#define ZX296702_PPU_AXI_M_ACLK 52
|
||||
#define ZX296702_PPU_AHB_S_HCLK 53
|
||||
#define ZX296702_VOU_AXI_M_ACLK 54
|
||||
#define ZX296702_VOU_APB_PCLK 55
|
||||
#define ZX296702_VOU_MAIN_CHANNEL_WCLK 56
|
||||
#define ZX296702_VOU_AUX_CHANNEL_WCLK 57
|
||||
#define ZX296702_VOU_HDMI_OSCLK_CEC 58
|
||||
#define ZX296702_VOU_SCALER_WCLK 59
|
||||
#define ZX296702_MALI400_AXI_M_ACLK 60
|
||||
#define ZX296702_MALI400_APB_PCLK 61
|
||||
#define ZX296702_R2D_WCLK 62
|
||||
#define ZX296702_R2D_AXI_M_ACLK 63
|
||||
#define ZX296702_R2D_AHB_HCLK 64
|
||||
#define ZX296702_DDR3_AXI_S0_ACLK 65
|
||||
#define ZX296702_DDR3_APB_PCLK 66
|
||||
#define ZX296702_DDR3_WCLK 67
|
||||
#define ZX296702_USB20_0_AHB_HCLK 68
|
||||
#define ZX296702_USB20_0_EXTREFCLK 69
|
||||
#define ZX296702_USB20_1_AHB_HCLK 70
|
||||
#define ZX296702_USB20_1_EXTREFCLK 71
|
||||
#define ZX296702_USB20_2_AHB_HCLK 72
|
||||
#define ZX296702_USB20_2_EXTREFCLK 73
|
||||
#define ZX296702_GMAC_AXI_M_ACLK 74
|
||||
#define ZX296702_GMAC_APB_PCLK 75
|
||||
#define ZX296702_GMAC_125_CLKIN 76
|
||||
#define ZX296702_GMAC_RMII_CLKIN 77
|
||||
#define ZX296702_GMAC_25M_CLK 78
|
||||
#define ZX296702_NANDFLASH_AHB_HCLK 79
|
||||
#define ZX296702_NANDFLASH_WCLK 80
|
||||
#define ZX296702_LSP0_APB_PCLK 81
|
||||
#define ZX296702_LSP0_AHB_HCLK 82
|
||||
#define ZX296702_LSP0_26M_WCLK 83
|
||||
#define ZX296702_LSP0_104M_WCLK 84
|
||||
#define ZX296702_LSP0_16M384_WCLK 85
|
||||
#define ZX296702_LSP1_APB_PCLK 86
|
||||
#define ZX296702_LSP1_26M_WCLK 87
|
||||
#define ZX296702_LSP1_104M_WCLK 88
|
||||
#define ZX296702_LSP1_32K_CLK 89
|
||||
#define ZX296702_AON_HCLK 90
|
||||
#define ZX296702_SYS_CTRL_PCLK 91
|
||||
#define ZX296702_DMA_PCLK 92
|
||||
#define ZX296702_DMA_ACLK 93
|
||||
#define ZX296702_SEC_HCLK 94
|
||||
#define ZX296702_AES_WCLK 95
|
||||
#define ZX296702_DES_WCLK 96
|
||||
#define ZX296702_IRAM_ACLK 97
|
||||
#define ZX296702_IROM_ACLK 98
|
||||
#define ZX296702_BOOT_CTRL_HCLK 99
|
||||
#define ZX296702_EFUSE_CLK_30 100
|
||||
#define ZX296702_VOU_MAIN_CHANNEL_DIV 101
|
||||
#define ZX296702_VOU_AUX_CHANNEL_DIV 102
|
||||
#define ZX296702_VOU_TV_ENC_HD_DIV 103
|
||||
#define ZX296702_VOU_TV_ENC_SD_DIV 104
|
||||
#define ZX296702_VL0_MUX 105
|
||||
#define ZX296702_VL1_MUX 106
|
||||
#define ZX296702_VL2_MUX 107
|
||||
#define ZX296702_GL0_MUX 108
|
||||
#define ZX296702_GL1_MUX 109
|
||||
#define ZX296702_GL2_MUX 110
|
||||
#define ZX296702_WB_MUX 111
|
||||
#define ZX296702_HDMI_MUX 112
|
||||
#define ZX296702_VOU_TV_ENC_HD_MUX 113
|
||||
#define ZX296702_VOU_TV_ENC_SD_MUX 114
|
||||
#define ZX296702_VL0_CLK 115
|
||||
#define ZX296702_VL1_CLK 116
|
||||
#define ZX296702_VL2_CLK 117
|
||||
#define ZX296702_GL0_CLK 118
|
||||
#define ZX296702_GL1_CLK 119
|
||||
#define ZX296702_GL2_CLK 120
|
||||
#define ZX296702_WB_CLK 121
|
||||
#define ZX296702_CL_CLK 122
|
||||
#define ZX296702_MAIN_MIX_CLK 123
|
||||
#define ZX296702_AUX_MIX_CLK 124
|
||||
#define ZX296702_HDMI_CLK 125
|
||||
#define ZX296702_VOU_TV_ENC_HD_DAC_CLK 126
|
||||
#define ZX296702_VOU_TV_ENC_SD_DAC_CLK 127
|
||||
#define ZX296702_A9_PERIPHCLK 128
|
||||
#define ZX296702_TOPCLK_END 129
|
||||
|
||||
#define ZX296702_SDMMC1_WCLK_MUX 0
|
||||
#define ZX296702_SDMMC1_WCLK_DIV 1
|
||||
#define ZX296702_SDMMC1_WCLK 2
|
||||
#define ZX296702_SDMMC1_PCLK 3
|
||||
#define ZX296702_SPDIF0_WCLK_MUX 4
|
||||
#define ZX296702_SPDIF0_WCLK 5
|
||||
#define ZX296702_SPDIF0_PCLK 6
|
||||
#define ZX296702_SPDIF0_DIV 7
|
||||
#define ZX296702_I2S0_WCLK_MUX 8
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#define ZX296702_I2S0_WCLK 9
|
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#define ZX296702_I2S0_PCLK 10
|
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#define ZX296702_I2S0_DIV 11
|
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#define ZX296702_I2S1_WCLK_MUX 12
|
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#define ZX296702_I2S1_WCLK 13
|
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#define ZX296702_I2S1_PCLK 14
|
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#define ZX296702_I2S1_DIV 15
|
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#define ZX296702_I2S2_WCLK_MUX 16
|
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#define ZX296702_I2S2_WCLK 17
|
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#define ZX296702_I2S2_PCLK 18
|
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#define ZX296702_I2S2_DIV 19
|
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#define ZX296702_GPIO_CLK 20
|
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#define ZX296702_LSP0CLK_END 21
|
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|
||||
#define ZX296702_UART0_WCLK_MUX 0
|
||||
#define ZX296702_UART0_WCLK 1
|
||||
#define ZX296702_UART0_PCLK 2
|
||||
#define ZX296702_UART1_WCLK_MUX 3
|
||||
#define ZX296702_UART1_WCLK 4
|
||||
#define ZX296702_UART1_PCLK 5
|
||||
#define ZX296702_SDMMC0_WCLK_MUX 6
|
||||
#define ZX296702_SDMMC0_WCLK_DIV 7
|
||||
#define ZX296702_SDMMC0_WCLK 8
|
||||
#define ZX296702_SDMMC0_PCLK 9
|
||||
#define ZX296702_SPDIF1_WCLK_MUX 10
|
||||
#define ZX296702_SPDIF1_WCLK 11
|
||||
#define ZX296702_SPDIF1_PCLK 12
|
||||
#define ZX296702_SPDIF1_DIV 13
|
||||
#define ZX296702_LSP1CLK_END 14
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_ZX296702_H */
|
||||
@ -1 +0,0 @@
|
||||
void __init u300_clk_init(void __iomem *base);
|
||||
Loading…
Reference in New Issue
Block a user