forked from Minki/linux
[SPARC]: Convert clock drivers to of_driver framework.
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
David S. Miller
parent
36a59bd89c
commit
ee5caf0ee1
@ -42,6 +42,7 @@
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#include <asm/sun4paddr.h>
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#include <asm/page.h>
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#include <asm/pcic.h>
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#include <asm/of_device.h>
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extern unsigned long wall_jiffies;
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@ -273,83 +274,31 @@ static __inline__ void sun4_clock_probe(void)
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#endif
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}
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/* Probe for the mostek real time clock chip. */
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static __inline__ void clock_probe(void)
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static int __devinit clock_probe(struct of_device *op, const struct of_device_id *match)
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{
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struct linux_prom_registers clk_reg[2];
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char model[128];
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register int node, cpuunit, bootbus;
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struct resource r;
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struct device_node *dp = op->node;
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char *model = of_get_property(dp, "model", NULL);
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cpuunit = bootbus = 0;
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memset(&r, 0, sizeof(r));
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if (!model)
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return -ENODEV;
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/* Determine the correct starting PROM node for the probe. */
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node = prom_getchild(prom_root_node);
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switch (sparc_cpu_model) {
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case sun4c:
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break;
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case sun4m:
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node = prom_getchild(prom_searchsiblings(node, "obio"));
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break;
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case sun4d:
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node = prom_getchild(bootbus = prom_searchsiblings(prom_getchild(cpuunit = prom_searchsiblings(node, "cpu-unit")), "bootbus"));
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break;
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default:
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prom_printf("CLOCK: Unsupported architecture!\n");
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prom_halt();
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}
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/* Find the PROM node describing the real time clock. */
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sp_clock_typ = MSTK_INVALID;
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node = prom_searchsiblings(node,"eeprom");
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if (!node) {
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prom_printf("CLOCK: No clock found!\n");
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prom_halt();
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}
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/* Get the model name and setup everything up. */
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model[0] = '\0';
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prom_getstring(node, "model", model, sizeof(model));
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if (strcmp(model, "mk48t02") == 0) {
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if (!strcmp(model, "mk48t02")) {
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sp_clock_typ = MSTK48T02;
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if (prom_getproperty(node, "reg", (char *) clk_reg, sizeof(clk_reg)) == -1) {
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prom_printf("clock_probe: FAILED!\n");
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prom_halt();
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}
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if (sparc_cpu_model == sun4d)
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prom_apply_generic_ranges (bootbus, cpuunit, clk_reg, 1);
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else
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prom_apply_obio_ranges(clk_reg, 1);
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/* Map the clock register io area read-only */
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r.flags = clk_reg[0].which_io;
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r.start = clk_reg[0].phys_addr;
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mstk48t02_regs = sbus_ioremap(&r, 0,
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sizeof(struct mostek48t02), "mk48t02");
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mstk48t02_regs = of_ioremap(&op->resource[0], 0,
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sizeof(struct mostek48t02),
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"mk48t02");
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mstk48t08_regs = NULL; /* To catch weirdness */
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} else if (strcmp(model, "mk48t08") == 0) {
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} else if (!strcmp(model, "mk48t08")) {
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sp_clock_typ = MSTK48T08;
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if(prom_getproperty(node, "reg", (char *) clk_reg,
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sizeof(clk_reg)) == -1) {
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prom_printf("clock_probe: FAILED!\n");
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prom_halt();
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}
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if (sparc_cpu_model == sun4d)
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prom_apply_generic_ranges (bootbus, cpuunit, clk_reg, 1);
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else
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prom_apply_obio_ranges(clk_reg, 1);
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/* Map the clock register io area read-only */
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/* XXX r/o attribute is somewhere in r.flags */
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r.flags = clk_reg[0].which_io;
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r.start = clk_reg[0].phys_addr;
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mstk48t08_regs = sbus_ioremap(&r, 0,
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sizeof(struct mostek48t08), "mk48t08");
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mstk48t08_regs = of_ioremap(&op->resource[0], 0,
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sizeof(struct mostek48t08),
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"mk48t08");
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mstk48t02_regs = &mstk48t08_regs->regs;
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} else {
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prom_printf("CLOCK: Unknown model name '%s'\n",model);
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prom_halt();
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}
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} else
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return -ENODEV;
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/* Report a low battery voltage condition. */
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if (has_low_battery())
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@ -358,6 +307,28 @@ static __inline__ void clock_probe(void)
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/* Kick start the clock if it is completely stopped. */
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if (mostek_read(mstk48t02_regs + MOSTEK_SEC) & MSTK_STOP)
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kick_start_clock();
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return 0;
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}
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static struct of_device_id clock_match[] = {
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{
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.name = "eeprom",
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},
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{},
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};
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static struct of_platform_driver clock_driver = {
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.name = "clock",
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.match_table = clock_match,
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.probe = clock_probe,
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};
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/* Probe for the mostek real time clock chip. */
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static void clock_init(void)
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{
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of_register_driver(&clock_driver, &of_bus_type);
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}
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void __init sbus_time_init(void)
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@ -376,7 +347,7 @@ void __init sbus_time_init(void)
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if (ARCH_SUN4)
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sun4_clock_probe();
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else
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clock_probe();
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clock_init();
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sparc_init_timers(timer_interrupt);
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@ -307,7 +307,6 @@ static void __init pci_scan_each_controller_bus(void)
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p->scan_bus(p);
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}
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extern void clock_probe(void);
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extern void power_init(void);
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static int __init pcibios_init(void)
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@ -320,7 +319,6 @@ static int __init pcibios_init(void)
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isa_init();
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ebus_init();
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clock_probe();
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power_init();
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return 0;
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@ -1267,8 +1267,6 @@ int __init sbus_arch_preinit(void)
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void __init sbus_arch_postinit(void)
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{
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extern void firetruck_init(void);
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extern void clock_probe(void);
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firetruck_init();
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clock_probe();
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}
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@ -770,219 +770,37 @@ static int __init clock_model_matches(char *model)
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return 1;
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}
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static void __init __clock_assign_common(void __iomem *addr, char *model)
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static int __devinit clock_probe(struct of_device *op, const struct of_device_id *match)
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{
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if (model[5] == '0' && model[6] == '2') {
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mstk48t02_regs = addr;
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} else if(model[5] == '0' && model[6] == '8') {
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mstk48t08_regs = addr;
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mstk48t02_regs = mstk48t08_regs + MOSTEK_48T08_48T02;
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} else {
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mstk48t59_regs = addr;
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mstk48t02_regs = mstk48t59_regs + MOSTEK_48T59_48T02;
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}
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}
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struct device_node *dp = op->node;
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char *model = of_get_property(dp, "model", NULL);
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unsigned long size, flags;
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void __iomem *regs;
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static void __init clock_assign_clk_reg(struct linux_prom_registers *clk_reg,
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char *model)
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{
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unsigned long addr;
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if (!model || !clock_model_matches(model))
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return -ENODEV;
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addr = ((unsigned long) clk_reg[0].phys_addr |
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(((unsigned long) clk_reg[0].which_io) << 32UL));
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size = (op->resource[0].end - op->resource[0].start) + 1;
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regs = of_ioremap(&op->resource[0], 0, size, "clock");
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if (!regs)
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return -ENOMEM;
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__clock_assign_common((void __iomem *) addr, model);
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}
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static int __init clock_probe_central(void)
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{
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struct linux_prom_registers clk_reg[2], *pr;
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struct device_node *dp;
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char *model;
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if (!central_bus)
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return 0;
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/* Get Central FHC's prom node. */
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dp = central_bus->child->prom_node;
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/* Then get the first child device below it. */
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dp = dp->child;
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while (dp) {
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model = of_get_property(dp, "model", NULL);
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if (!model || !clock_model_matches(model))
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goto next_sibling;
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pr = of_get_property(dp, "reg", NULL);
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memcpy(clk_reg, pr, sizeof(clk_reg));
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apply_fhc_ranges(central_bus->child, clk_reg, 1);
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apply_central_ranges(central_bus, clk_reg, 1);
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clock_assign_clk_reg(clk_reg, model);
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return 1;
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next_sibling:
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dp = dp->sibling;
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}
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return 0;
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}
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#ifdef CONFIG_PCI
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static void __init clock_isa_ebus_assign_regs(struct resource *res, char *model)
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{
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if (!strcmp(model, "ds1287") ||
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!strcmp(model, "m5819") ||
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!strcmp(model, "m5819p") ||
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!strcmp(model, "m5823")) {
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ds1287_regs = res->start;
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ds1287_regs = (unsigned long) regs;
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} else if (model[5] == '0' && model[6] == '2') {
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mstk48t02_regs = regs;
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} else if(model[5] == '0' && model[6] == '8') {
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mstk48t08_regs = regs;
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mstk48t02_regs = mstk48t08_regs + MOSTEK_48T08_48T02;
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} else {
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mstk48t59_regs = (void __iomem *) res->start;
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mstk48t59_regs = regs;
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mstk48t02_regs = mstk48t59_regs + MOSTEK_48T59_48T02;
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}
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}
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static int __init clock_probe_one_ebus_dev(struct linux_ebus_device *edev)
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{
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struct device_node *dp = edev->prom_node;
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char *model;
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model = of_get_property(dp, "model", NULL);
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if (!clock_model_matches(model))
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return 0;
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clock_isa_ebus_assign_regs(&edev->resource[0], model);
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return 1;
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}
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static int __init clock_probe_ebus(void)
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{
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struct linux_ebus *ebus;
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for_each_ebus(ebus) {
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struct linux_ebus_device *edev;
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for_each_ebusdev(edev, ebus) {
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if (clock_probe_one_ebus_dev(edev))
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return 1;
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}
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}
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return 0;
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}
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static int __init clock_probe_one_isa_dev(struct sparc_isa_device *idev)
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{
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struct device_node *dp = idev->prom_node;
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char *model;
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model = of_get_property(dp, "model", NULL);
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if (!clock_model_matches(model))
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return 0;
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clock_isa_ebus_assign_regs(&idev->resource, model);
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return 1;
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}
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static int __init clock_probe_isa(void)
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{
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struct sparc_isa_bridge *isa_br;
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for_each_isa(isa_br) {
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struct sparc_isa_device *isa_dev;
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for_each_isadev(isa_dev, isa_br) {
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if (clock_probe_one_isa_dev(isa_dev))
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return 1;
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}
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}
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return 0;
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}
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#endif /* CONFIG_PCI */
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#ifdef CONFIG_SBUS
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static int __init clock_probe_one_sbus_dev(struct sbus_bus *sbus, struct sbus_dev *sdev)
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{
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struct resource *res;
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char model[64];
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void __iomem *addr;
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prom_getstring(sdev->prom_node, "model", model, sizeof(model));
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if (!clock_model_matches(model))
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return 0;
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res = &sdev->resource[0];
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addr = sbus_ioremap(res, 0, 0x800UL, "eeprom");
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__clock_assign_common(addr, model);
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return 1;
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}
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static int __init clock_probe_sbus(void)
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{
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struct sbus_bus *sbus;
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for_each_sbus(sbus) {
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struct sbus_dev *sdev;
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for_each_sbusdev(sdev, sbus) {
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if (clock_probe_one_sbus_dev(sbus, sdev))
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return 1;
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}
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}
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return 0;
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}
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#endif
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void __init clock_probe(void)
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{
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static int invoked;
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unsigned long flags;
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if (invoked)
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return;
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invoked = 1;
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if (this_is_starfire) {
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xtime.tv_sec = starfire_get_time();
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xtime.tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ);
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set_normalized_timespec(&wall_to_monotonic,
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-xtime.tv_sec, -xtime.tv_nsec);
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return;
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}
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if (tlb_type == hypervisor) {
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xtime.tv_sec = hypervisor_get_time();
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xtime.tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ);
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set_normalized_timespec(&wall_to_monotonic,
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-xtime.tv_sec, -xtime.tv_nsec);
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return;
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}
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/* Check FHC Central then EBUSs then ISA bridges then SBUSs.
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* That way we handle the presence of multiple properly.
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*
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* As a special case, machines with Central must provide the
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* timer chip there.
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*/
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if (!clock_probe_central() &&
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#ifdef CONFIG_PCI
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!clock_probe_ebus() &&
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!clock_probe_isa() &&
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#endif
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#ifdef CONFIG_SBUS
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!clock_probe_sbus()
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#endif
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) {
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printk(KERN_WARNING "No clock chip found.\n");
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return;
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}
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printk(KERN_INFO "%s: Clock regs at %p\n", dp->full_name, regs);
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local_irq_save(flags);
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@ -999,8 +817,52 @@ void __init clock_probe(void)
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set_system_time();
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local_irq_restore(flags);
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return 0;
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}
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static struct of_device_id clock_match[] = {
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{
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.name = "eeprom",
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},
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{
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.name = "rtc",
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},
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{},
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};
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static struct of_platform_driver clock_driver = {
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.name = "clock",
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.match_table = clock_match,
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.probe = clock_probe,
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};
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static int __init clock_init(void)
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{
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if (this_is_starfire) {
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xtime.tv_sec = starfire_get_time();
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xtime.tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ);
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set_normalized_timespec(&wall_to_monotonic,
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-xtime.tv_sec, -xtime.tv_nsec);
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return 0;
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}
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if (tlb_type == hypervisor) {
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xtime.tv_sec = hypervisor_get_time();
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xtime.tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ);
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set_normalized_timespec(&wall_to_monotonic,
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-xtime.tv_sec, -xtime.tv_nsec);
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return 0;
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}
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return of_register_driver(&clock_driver, &of_bus_type);
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}
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/* Must be after subsys_initcall() so that busses are probed. Must
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* be before device_initcall() because things like the RTC driver
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* need to see the clock registers.
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*/
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fs_initcall(clock_init);
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/* This is gets the master TICK_INT timer going. */
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static unsigned long sparc64_init_timers(void)
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{
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