forked from Minki/linux
Merge branch 'kvm-ppc-next' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc into HEAD
This brings in two fixes for potential host crashes, from Ben Herrenschmidt and Nick Piggin.
This commit is contained in:
commit
ee10689117
@ -236,6 +236,11 @@ END_FTR_SECTION_NESTED(ftr,ftr,943)
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mtctr reg; \
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bctr
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#define BRANCH_LINK_TO_FAR(reg, label) \
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__LOAD_FAR_HANDLER(reg, label); \
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mtctr reg; \
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bctrl
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/*
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* KVM requires __LOAD_FAR_HANDLER.
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*
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@ -260,6 +265,9 @@ END_FTR_SECTION_NESTED(ftr,ftr,943)
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#define BRANCH_TO_COMMON(reg, label) \
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b label
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#define BRANCH_LINK_TO_FAR(reg, label) \
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bl label
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#define BRANCH_TO_KVM(reg, label) \
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b label
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@ -67,7 +67,6 @@ int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func,
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int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func,
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uint64_t offset, uint32_t data);
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int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority);
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int64_t opal_rm_set_xive(uint32_t isn, uint16_t server, uint8_t priority);
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int64_t opal_get_xive(uint32_t isn, __be16 *server, uint8_t *priority);
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int64_t opal_register_exception_handler(uint64_t opal_exception,
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uint64_t handler_address,
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@ -220,18 +219,12 @@ int64_t opal_pci_set_power_state(uint64_t async_token, uint64_t id,
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int64_t opal_pci_poll2(uint64_t id, uint64_t data);
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int64_t opal_int_get_xirr(uint32_t *out_xirr, bool just_poll);
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int64_t opal_rm_int_get_xirr(__be32 *out_xirr, bool just_poll);
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int64_t opal_int_set_cppr(uint8_t cppr);
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int64_t opal_int_eoi(uint32_t xirr);
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int64_t opal_rm_int_eoi(uint32_t xirr);
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int64_t opal_int_set_mfrr(uint32_t cpu, uint8_t mfrr);
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int64_t opal_rm_int_set_mfrr(uint32_t cpu, uint8_t mfrr);
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int64_t opal_pci_tce_kill(uint64_t phb_id, uint32_t kill_type,
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uint32_t pe_num, uint32_t tce_size,
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uint64_t dma_addr, uint32_t npages);
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int64_t opal_rm_pci_tce_kill(uint64_t phb_id, uint32_t kill_type,
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uint32_t pe_num, uint32_t tce_size,
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uint64_t dma_addr, uint32_t npages);
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/* Internal functions */
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extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
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@ -982,7 +982,7 @@ TRAMP_REAL_BEGIN(hmi_exception_early)
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EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN)
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EXCEPTION_PROLOG_COMMON_3(0xe60)
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addi r3,r1,STACK_FRAME_OVERHEAD
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bl hmi_exception_realmode
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BRANCH_LINK_TO_FAR(r4, hmi_exception_realmode)
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/* Windup the stack. */
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/* Move original HSRR0 and HSRR1 into the respective regs */
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ld r9,_MSR(r1)
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@ -250,7 +250,7 @@ fastsleep_workaround_at_entry:
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/* Fast sleep workaround */
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li r3,1
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li r4,1
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bl opal_rm_config_cpu_idle_state
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bl opal_config_cpu_idle_state
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/* Clear Lock bit */
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li r0,0
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@ -544,7 +544,7 @@ timebase_resync:
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*/
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ble cr3,clear_lock
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/* Time base re-sync */
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bl opal_rm_resync_timebase;
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bl opal_resync_timebase;
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/*
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* If waking up from sleep, per core state is not lost, skip to
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* clear_lock.
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@ -633,7 +633,7 @@ hypervisor_state_restored:
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fastsleep_workaround_at_exit:
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li r3,1
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li r4,0
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bl opal_rm_config_cpu_idle_state
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bl opal_config_cpu_idle_state
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b timebase_resync
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/*
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@ -171,6 +171,7 @@ long kvm_vm_ioctl_create_spapr_tce(struct kvm *kvm,
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goto fail;
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}
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ret = -ENOMEM;
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stt = kzalloc(sizeof(*stt) + npages * sizeof(struct page *),
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GFP_KERNEL);
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if (!stt)
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@ -29,11 +29,6 @@
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#include <asm/opal.h>
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#include <asm/smp.h>
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static bool in_realmode(void)
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{
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return !(mfmsr() & MSR_IR);
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}
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#define KVM_CMA_CHUNK_ORDER 18
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/*
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@ -230,13 +225,10 @@ void kvmhv_rm_send_ipi(int cpu)
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/* Else poke the target with an IPI */
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xics_phys = paca[cpu].kvm_hstate.xics_phys;
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if (!in_realmode())
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opal_int_set_mfrr(get_hard_smp_processor_id(cpu), IPI_PRIORITY);
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else if (xics_phys)
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if (xics_phys)
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rm_writeb(xics_phys + XICS_MFRR, IPI_PRIORITY);
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else
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opal_rm_int_set_mfrr(get_hard_smp_processor_id(cpu),
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IPI_PRIORITY);
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opal_int_set_mfrr(get_hard_smp_processor_id(cpu), IPI_PRIORITY);
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}
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/*
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@ -419,10 +411,8 @@ static long kvmppc_read_one_intr(bool *again)
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/* Now read the interrupt from the ICP */
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xics_phys = local_paca->kvm_hstate.xics_phys;
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rc = 0;
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if (!in_realmode())
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if (!xics_phys)
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rc = opal_int_get_xirr(&xirr, false);
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else if (!xics_phys)
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rc = opal_rm_int_get_xirr(&xirr, false);
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else
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xirr = _lwzcix(xics_phys + XICS_XIRR);
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if (rc < 0)
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@ -453,15 +443,12 @@ static long kvmppc_read_one_intr(bool *again)
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*/
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if (xisr == XICS_IPI) {
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rc = 0;
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if (!in_realmode()) {
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opal_int_set_mfrr(hard_smp_processor_id(), 0xff);
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rc = opal_int_eoi(h_xirr);
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} else if (xics_phys) {
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if (xics_phys) {
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_stbcix(xics_phys + XICS_MFRR, 0xff);
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_stwcix(xics_phys + XICS_XIRR, xirr);
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} else {
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opal_rm_int_set_mfrr(hard_smp_processor_id(), 0xff);
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rc = opal_rm_int_eoi(h_xirr);
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opal_int_set_mfrr(hard_smp_processor_id(), 0xff);
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rc = opal_int_eoi(h_xirr);
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}
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/* If rc > 0, there is another interrupt pending */
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*again = rc > 0;
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@ -482,14 +469,11 @@ static long kvmppc_read_one_intr(bool *again)
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/* We raced with the host,
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* we need to resend that IPI, bummer
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*/
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if (!in_realmode())
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opal_int_set_mfrr(hard_smp_processor_id(),
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IPI_PRIORITY);
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else if (xics_phys)
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if (xics_phys)
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_stbcix(xics_phys + XICS_MFRR, IPI_PRIORITY);
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else
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opal_rm_int_set_mfrr(hard_smp_processor_id(),
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IPI_PRIORITY);
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opal_int_set_mfrr(hard_smp_processor_id(),
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IPI_PRIORITY);
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/* Let side effects complete */
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smp_mb();
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return 1;
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@ -36,7 +36,7 @@ EXPORT_SYMBOL(kvm_irq_bypass);
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static void icp_rm_deliver_irq(struct kvmppc_xics *xics, struct kvmppc_icp *icp,
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u32 new_irq, bool check_resend);
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static int xics_opal_rm_set_server(unsigned int hw_irq, int server_cpu);
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static int xics_opal_set_server(unsigned int hw_irq, int server_cpu);
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/* -- ICS routines -- */
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static void ics_rm_check_resend(struct kvmppc_xics *xics,
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@ -720,7 +720,7 @@ static int ics_rm_eoi(struct kvm_vcpu *vcpu, u32 irq)
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++vcpu->stat.pthru_host;
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if (state->intr_cpu != pcpu) {
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++vcpu->stat.pthru_bad_aff;
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xics_opal_rm_set_server(state->host_irq, pcpu);
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xics_opal_set_server(state->host_irq, pcpu);
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}
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state->intr_cpu = -1;
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}
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@ -781,16 +781,16 @@ static void icp_eoi(struct irq_chip *c, u32 hwirq, __be32 xirr, bool *again)
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if (xics_phys) {
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_stwcix(xics_phys + XICS_XIRR, xirr);
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} else {
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rc = opal_rm_int_eoi(be32_to_cpu(xirr));
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rc = opal_int_eoi(be32_to_cpu(xirr));
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*again = rc > 0;
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}
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}
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static int xics_opal_rm_set_server(unsigned int hw_irq, int server_cpu)
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static int xics_opal_set_server(unsigned int hw_irq, int server_cpu)
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{
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unsigned int mangle_cpu = get_hard_smp_processor_id(server_cpu) << 2;
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return opal_rm_set_xive(hw_irq, mangle_cpu, DEFAULT_PRIORITY);
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return opal_set_xive(hw_irq, mangle_cpu, DEFAULT_PRIORITY);
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}
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/*
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@ -58,14 +58,16 @@ END_FTR_SECTION(0, 1); \
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#define OPAL_CALL(name, token) \
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_GLOBAL_TOC(name); \
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mfmsr r12; \
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mflr r0; \
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andi. r11,r12,MSR_IR|MSR_DR; \
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std r0,PPC_LR_STKOFF(r1); \
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li r0,token; \
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beq opal_real_call; \
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OPAL_BRANCH(opal_tracepoint_entry) \
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mfcr r12; \
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stw r12,8(r1); \
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mfcr r11; \
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stw r11,8(r1); \
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li r11,0; \
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mfmsr r12; \
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ori r11,r11,MSR_EE; \
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std r12,PACASAVEDMSR(r13); \
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andc r12,r12,r11; \
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@ -98,6 +100,30 @@ opal_return:
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mtcr r4;
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rfid
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opal_real_call:
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mfcr r11
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stw r11,8(r1)
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/* Set opal return address */
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LOAD_REG_ADDR(r11, opal_return_realmode)
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mtlr r11
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li r11,MSR_LE
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andc r12,r12,r11
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mtspr SPRN_HSRR1,r12
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LOAD_REG_ADDR(r11,opal)
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ld r12,8(r11)
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ld r2,0(r11)
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mtspr SPRN_HSRR0,r12
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hrfid
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opal_return_realmode:
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FIXUP_ENDIAN
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ld r2,PACATOC(r13);
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lwz r11,8(r1);
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ld r12,PPC_LR_STKOFF(r1)
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mtcr r11;
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mtlr r12
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blr
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#ifdef CONFIG_TRACEPOINTS
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opal_tracepoint_entry:
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stdu r1,-STACKFRAMESIZE(r1)
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@ -155,36 +181,6 @@ opal_tracepoint_return:
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blr
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#endif
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#define OPAL_CALL_REAL(name, token) \
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_GLOBAL_TOC(name); \
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mflr r0; \
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std r0,PPC_LR_STKOFF(r1); \
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li r0,token; \
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mfcr r12; \
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stw r12,8(r1); \
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\
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/* Set opal return address */ \
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LOAD_REG_ADDR(r11, opal_return_realmode); \
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mtlr r11; \
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mfmsr r12; \
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li r11,MSR_LE; \
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andc r12,r12,r11; \
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mtspr SPRN_HSRR1,r12; \
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LOAD_REG_ADDR(r11,opal); \
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ld r12,8(r11); \
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ld r2,0(r11); \
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mtspr SPRN_HSRR0,r12; \
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hrfid
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opal_return_realmode:
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FIXUP_ENDIAN
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ld r2,PACATOC(r13);
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lwz r11,8(r1);
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ld r12,PPC_LR_STKOFF(r1)
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mtcr r11;
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mtlr r12
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blr
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OPAL_CALL(opal_invalid_call, OPAL_INVALID_CALL);
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OPAL_CALL(opal_console_write, OPAL_CONSOLE_WRITE);
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@ -208,7 +204,6 @@ OPAL_CALL(opal_pci_config_write_byte, OPAL_PCI_CONFIG_WRITE_BYTE);
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OPAL_CALL(opal_pci_config_write_half_word, OPAL_PCI_CONFIG_WRITE_HALF_WORD);
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OPAL_CALL(opal_pci_config_write_word, OPAL_PCI_CONFIG_WRITE_WORD);
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OPAL_CALL(opal_set_xive, OPAL_SET_XIVE);
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OPAL_CALL_REAL(opal_rm_set_xive, OPAL_SET_XIVE);
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OPAL_CALL(opal_get_xive, OPAL_GET_XIVE);
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OPAL_CALL(opal_register_exception_handler, OPAL_REGISTER_OPAL_EXCEPTION_HANDLER);
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OPAL_CALL(opal_pci_eeh_freeze_status, OPAL_PCI_EEH_FREEZE_STATUS);
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@ -264,7 +259,6 @@ OPAL_CALL(opal_validate_flash, OPAL_FLASH_VALIDATE);
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OPAL_CALL(opal_manage_flash, OPAL_FLASH_MANAGE);
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OPAL_CALL(opal_update_flash, OPAL_FLASH_UPDATE);
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OPAL_CALL(opal_resync_timebase, OPAL_RESYNC_TIMEBASE);
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OPAL_CALL_REAL(opal_rm_resync_timebase, OPAL_RESYNC_TIMEBASE);
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OPAL_CALL(opal_check_token, OPAL_CHECK_TOKEN);
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OPAL_CALL(opal_dump_init, OPAL_DUMP_INIT);
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OPAL_CALL(opal_dump_info, OPAL_DUMP_INFO);
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@ -280,9 +274,7 @@ OPAL_CALL(opal_sensor_read, OPAL_SENSOR_READ);
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OPAL_CALL(opal_get_param, OPAL_GET_PARAM);
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OPAL_CALL(opal_set_param, OPAL_SET_PARAM);
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OPAL_CALL(opal_handle_hmi, OPAL_HANDLE_HMI);
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OPAL_CALL_REAL(opal_rm_handle_hmi, OPAL_HANDLE_HMI);
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OPAL_CALL(opal_config_cpu_idle_state, OPAL_CONFIG_CPU_IDLE_STATE);
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OPAL_CALL_REAL(opal_rm_config_cpu_idle_state, OPAL_CONFIG_CPU_IDLE_STATE);
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OPAL_CALL(opal_slw_set_reg, OPAL_SLW_SET_REG);
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OPAL_CALL(opal_register_dump_region, OPAL_REGISTER_DUMP_REGION);
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OPAL_CALL(opal_unregister_dump_region, OPAL_UNREGISTER_DUMP_REGION);
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@ -304,11 +296,7 @@ OPAL_CALL(opal_pci_get_presence_state, OPAL_PCI_GET_PRESENCE_STATE);
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OPAL_CALL(opal_pci_get_power_state, OPAL_PCI_GET_POWER_STATE);
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OPAL_CALL(opal_pci_set_power_state, OPAL_PCI_SET_POWER_STATE);
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OPAL_CALL(opal_int_get_xirr, OPAL_INT_GET_XIRR);
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OPAL_CALL_REAL(opal_rm_int_get_xirr, OPAL_INT_GET_XIRR);
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OPAL_CALL(opal_int_set_cppr, OPAL_INT_SET_CPPR);
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OPAL_CALL(opal_int_eoi, OPAL_INT_EOI);
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OPAL_CALL_REAL(opal_rm_int_eoi, OPAL_INT_EOI);
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OPAL_CALL(opal_int_set_mfrr, OPAL_INT_SET_MFRR);
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OPAL_CALL_REAL(opal_rm_int_set_mfrr, OPAL_INT_SET_MFRR);
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OPAL_CALL(opal_pci_tce_kill, OPAL_PCI_TCE_KILL);
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OPAL_CALL_REAL(opal_rm_pci_tce_kill, OPAL_PCI_TCE_KILL);
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@ -1962,11 +1962,6 @@ static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
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if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
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pnv_pci_phb3_tce_invalidate(pe, rm, shift,
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index, npages);
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else if (rm)
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opal_rm_pci_tce_kill(phb->opal_id,
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OPAL_PCI_TCE_KILL_PAGES,
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pe->pe_number, 1u << shift,
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index << shift, npages);
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else
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opal_pci_tce_kill(phb->opal_id,
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OPAL_PCI_TCE_KILL_PAGES,
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