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SoCFPGA DTS updates for v4.7

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- Update SD/MMC node for Arria10
 - Update Arria10 with clock and interrupt fields for DMA
 - Remove 'phy-addr' from stmmac node
 - Remove ethernet node from Cyclone5 DTSI
 - Add LEDs/KEYs/SWs support on Sockit
 - Add L2 and OCRAM EDAC dts entries
 - Add reset control for USB
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Merge tag 'socfpga_dts_for_v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dt

SoCFPGA DTS updates for v4.7
- Update SD/MMC node for Arria10
- Update Arria10 with clock and interrupt fields for DMA
- Remove 'phy-addr' from stmmac node
- Remove ethernet node from Cyclone5 DTSI
- Add LEDs/KEYs/SWs support on Sockit
- Add L2 and OCRAM EDAC dts entries
- Add reset control for USB

* tag 'socfpga_dts_for_v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  ARM: dts: socfpga: add reset control for USB
  ARM: dts: socfpga: Add Altera Arria10 OCRAM EDAC devicetree entry
  ARM: dts: socfpga: Add Altera Arria10 L2 Cache EDAC devicetree entry
  ARM: dts: socfpga: Add support for HPS KEYs/SWs on SoCKit
  ARM: dts: socfpga: Add support for HPS LEDs on SoCKit
  ARM: dts: socfpga: Drop gmac0 from CV dtsi
  ARM: dts: socfpga: Drop phy-addr OF property from CV dtsi
  ARM: dts: socfpga: Add missing clock and interrupt fields for Arria10 DMA
  ARM: dts: socfpga: add the clk-phase property for sd/mmc clock
  ARM: dts: socfpga: add cap-sd-highspeed for SD/MMC node

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2016-04-13 15:17:42 -07:00
commit ed53ecbea7
6 changed files with 129 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/boot/dts/socfpga.dtsi
View File

@ -831,6 +831,8 @@
interrupts = <0 125 4>;
clocks = <&usb_mp_clk>;
clock-names = "otg";
resets = <&rst USB0_RESET>;
reset-names = "dwc2";
phys = <&usbphy0>;
phy-names = "usb2-phy";
status = "disabled";
@ -842,6 +844,8 @@
interrupts = <0 128 4>;
clocks = <&usb_mp_clk>;
clock-names = "otg";
resets = <&rst USB1_RESET>;
reset-names = "dwc2";
phys = <&usbphy0>;
phy-names = "usb2-phy";
status = "disabled";

32
arch/arm/boot/dts/socfpga_arria10.dtsi
View File

@ -78,10 +78,13 @@
<0 87 IRQ_TYPE_LEVEL_HIGH>,
<0 88 IRQ_TYPE_LEVEL_HIGH>,
<0 89 IRQ_TYPE_LEVEL_HIGH>,
<0 90 IRQ_TYPE_LEVEL_HIGH>;
<0 90 IRQ_TYPE_LEVEL_HIGH>,
<0 91 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
clocks = <&l4_main_clk>;
clock-names = "apb_pclk";
};
};
@ -362,6 +365,7 @@
compatible = "altr,socfpga-a10-gate-clk";
clocks = <&sdmmc_free_clk>;
clk-gate = <0xC8 5>;
clk-phase = <0 135>;
};
qspi_clk: qspi_clk {
@ -589,7 +593,7 @@
reg = <0xff808000 0x1000>;
interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
fifo-depth = <0x400>;
clocks = <&l4_mp_clk>, <&sdmmc_free_clk>;
clocks = <&l4_mp_clk>, <&sdmmc_clk>;
clock-names = "biu", "ciu";
status = "disabled";
};
@ -599,6 +603,26 @@
reg = <0xffe00000 0x40000>;
};
eccmgr: eccmgr@ffd06000 {
compatible = "altr,socfpga-a10-ecc-manager";
altr,sysmgr-syscon = <&sysmgr>;
#address-cells = <1>;
#size-cells = <1>;
interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
<0 0 IRQ_TYPE_LEVEL_HIGH>;
ranges;
l2-ecc@ffd06010 {
compatible = "altr,socfpga-a10-l2-ecc";
reg = <0xffd06010 0x4>;
};
ocram-ecc@ff8c3000 {
compatible = "altr,socfpga-a10-ocram-ecc";
reg = <0xff8c3000 0x400>;
};
};
rst: rstmgr@ffd05000 {
#reset-cells = <1>;
compatible = "altr,rst-mgr";
@ -689,6 +713,8 @@
interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&usb_clk>;
clock-names = "otg";
resets = <&rst USB0_RESET>;
reset-names = "dwc2";
phys = <&usbphy0>;
phy-names = "usb2-phy";
status = "disabled";
@ -700,6 +726,8 @@
interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&usb_clk>;
clock-names = "otg";
resets = <&rst USB1_RESET>;
reset-names = "dwc2";
phys = <&usbphy0>;
phy-names = "usb2-phy";
status = "disabled";

1
arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts
View File

@ -21,6 +21,7 @@
&mmc {
status = "okay";
num-slots = <1>;
cap-sd-highspeed;
broken-cd;
bus-width = <4>;
};

6
arch/arm/boot/dts/socfpga_cyclone5.dtsi
View File

@ -38,12 +38,6 @@
cap-sd-highspeed;
};
ethernet@ff702000 {
phy-mode = "rgmii";
phy-addr = <0xffffffff>; /* probe for phy addr */
status = "okay";
};
sysmgr@ffd08000 {
cpu1-start-addr = <0xffd080c4>;
};

94
arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
View File

@ -39,6 +39,90 @@
ethernet0 = &gmac1;
};
leds {
compatible = "gpio-leds";
hps_led0 {
label = "hps:blue:led0";
gpios = <&portb 24 0>; /* HPS_GPIO53 */
linux,default-trigger = "heartbeat";
};
hps_led1 {
label = "hps:blue:led1";
gpios = <&portb 25 0>; /* HPS_GPIO54 */
linux,default-trigger = "heartbeat";
};
hps_led2 {
label = "hps:blue:led2";
gpios = <&portb 26 0>; /* HPS_GPIO55 */
linux,default-trigger = "heartbeat";
};
hps_led3 {
label = "hps:blue:led3";
gpios = <&portb 27 0>; /* HPS_GPIO56 */
linux,default-trigger = "heartbeat";
};
};
gpio-keys {
compatible = "gpio-keys";
hps_sw0 {
label = "hps_sw0";
gpios = <&portc 20 0>; /* HPS_GPI7 */
linux,input-type = <5>; /* EV_SW */
linux,code = <0x0>; /* SW_LID */
};
hps_sw1 {
label = "hps_sw1";
gpios = <&portc 19 0>; /* HPS_GPI6 */
linux,input-type = <5>; /* EV_SW */
linux,code = <0x5>; /* SW_DOCK */
};
hps_sw2 {
label = "hps_sw2";
gpios = <&portc 18 0>; /* HPS_GPI5 */
linux,input-type = <5>; /* EV_SW */
linux,code = <0xa>; /* SW_KEYPAD_SLIDE */
};
hps_sw3 {
label = "hps_sw3";
gpios = <&portc 17 0>; /* HPS_GPI4 */
linux,input-type = <5>; /* EV_SW */
linux,code = <0xc>; /* SW_ROTATE_LOCK */
};
hps_hkey0 {
label = "hps_hkey0";
gpios = <&portc 21 1>; /* HPS_GPI8 */
linux,code = <187>; /* KEY_F17 */
};
hps_hkey1 {
label = "hps_hkey1";
gpios = <&portc 22 1>; /* HPS_GPI9 */
linux,code = <188>; /* KEY_F18 */
};
hps_hkey2 {
label = "hps_hkey2";
gpios = <&portc 23 1>; /* HPS_GPI10 */
linux,code = <189>; /* KEY_F19 */
};
hps_hkey3 {
label = "hps_hkey3";
gpios = <&portc 24 1>; /* HPS_GPI11 */
linux,code = <190>; /* KEY_F20 */
};
};
regulator_3_3v: vcc3p3-regulator {
compatible = "regulator-fixed";
regulator-name = "VCC3P3";
@ -61,7 +145,15 @@
rxc-skew-ps = <2000>;
};
&gpio2 {
&gpio0 { /* GPIO 0..29 */
status = "okay";
};
&gpio1 { /* GPIO 30..57 */
status = "okay";
};
&gpio2 { /* GPIO 58..66 (HLGPI 0..13 at offset 13) */
status = "okay";
};

1
arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
View File

@ -36,6 +36,7 @@
};
&gmac1 {
phy-mode = "rgmii";
status = "okay";
};