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drm/i915: Fix MST link rate handling

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Now that intel_dp_max_link_bw() no longer considers the source
restrictions we may try to enable MST with 5.4GHz even when the source
doesn't support it. To fix that switch the code over to handle the link
rate in the same way as the SST code handles it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Sonika Jindal <sonika.jindal@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ville Syrjälä 2015-03-12 17:10:36 +02:00 committed by Daniel Vetter
parent bc27b7d3f0
commit ed4e9c1d46
3 changed files with 22 additions and 8 deletions
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10
drivers/gpu/drm/i915/intel_dp.c
View File

@ -122,7 +122,7 @@ static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
static void vlv_steal_power_sequencer(struct drm_device *dev,
enum pipe pipe);
int
static int
intel_dp_max_link_bw(struct intel_dp *intel_dp)
{
int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
@ -1255,6 +1255,11 @@ intel_dp_max_link_rate(struct intel_dp *intel_dp)
return rates[rate_to_index(0, rates) - 1];
}
int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
{
return rate_to_index(rate, intel_dp->supported_rates);
}
bool
intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
@ -1374,8 +1379,7 @@ found:
if (intel_dp->num_supported_rates) {
intel_dp->link_bw = 0;
intel_dp->rate_select =
rate_to_index(supported_rates[clock],
intel_dp->supported_rates);
intel_dp_rate_select(intel_dp, supported_rates[clock]);
} else {
intel_dp->link_bw =
drm_dp_link_rate_to_bw_code(supported_rates[clock]);

16
drivers/gpu/drm/i915/intel_dp_mst.c
View File

@ -38,7 +38,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
struct intel_dp *intel_dp = &intel_dig_port->dp;
struct drm_device *dev = encoder->base.dev;
int bpp;
int lane_count, slots;
int lane_count, slots, rate;
struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
struct intel_connector *found = NULL, *intel_connector;
int mst_pbn;
@ -52,11 +52,21 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
* seem to suggest we should do otherwise.
*/
lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
intel_dp->link_bw = intel_dp_max_link_bw(intel_dp);
rate = intel_dp_max_link_rate(intel_dp);
if (intel_dp->num_supported_rates) {
intel_dp->link_bw = 0;
intel_dp->rate_select = intel_dp_rate_select(intel_dp, rate);
} else {
intel_dp->link_bw = drm_dp_link_rate_to_bw_code(rate);
intel_dp->rate_select = 0;
}
intel_dp->lane_count = lane_count;
pipe_config->pipe_bpp = 24;
pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
pipe_config->port_clock = rate;
for_each_intel_connector(dev, intel_connector) {
if (intel_connector->new_encoder == encoder) {

2
drivers/gpu/drm/i915/intel_drv.h
View File

@ -1061,8 +1061,8 @@ void intel_edp_panel_off(struct intel_dp *intel_dp);
void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
void intel_dp_mst_suspend(struct drm_device *dev);
void intel_dp_mst_resume(struct drm_device *dev);
int intel_dp_max_link_bw(struct intel_dp *intel_dp);
int intel_dp_max_link_rate(struct intel_dp *intel_dp);
int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);