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ARM: tegra: cardhu: Support CPU frequency and voltage scaling on all board variants

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Enable CPU frequency and voltage scaling on all Tegra30 Cardhu board
variants.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Dmitry Osipenko 2021-03-02 15:09:52 +03:00 committed by Thierry Reding
parent 3744c7d88c
commit ed34855b81
2 changed files with 37 additions and 51 deletions
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48
arch/arm/boot/dts/tegra30-cardhu-a04.dts
View File

@ -2,8 +2,6 @@
/dts-v1/;
#include "tegra30-cardhu.dtsi"
#include "tegra30-cpu-opp.dtsi"
#include "tegra30-cpu-opp-microvolt.dtsi"
/* This dts file support the cardhu A04 and later versions of board */
@ -92,50 +90,4 @@
enable-active-high;
gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>;
};
i2c@7000d000 {
pmic: tps65911@2d {
regulators {
vddctrl_reg: vddctrl {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1125000>;
regulator-coupled-with = <&vddcore_reg>;
regulator-coupled-max-spread = <300000>;
regulator-max-step-microvolt = <100000>;
nvidia,tegra-cpu-regulator;
};
};
};
vddcore_reg: tps62361@60 {
regulator-coupled-with = <&vddctrl_reg>;
regulator-coupled-max-spread = <300000>;
regulator-max-step-microvolt = <100000>;
nvidia,tegra-core-regulator;
};
};
cpus {
cpu0: cpu@0 {
cpu-supply = <&vddctrl_reg>;
operating-points-v2 = <&cpu0_opp_table>;
};
cpu@1 {
cpu-supply = <&vddctrl_reg>;
operating-points-v2 = <&cpu0_opp_table>;
};
cpu@2 {
cpu-supply = <&vddctrl_reg>;
operating-points-v2 = <&cpu0_opp_table>;
};
cpu@3 {
cpu-supply = <&vddctrl_reg>;
operating-points-v2 = <&cpu0_opp_table>;
};
};
};

40
arch/arm/boot/dts/tegra30-cardhu.dtsi
View File

@ -1,6 +1,8 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/input/input.h>
#include "tegra30.dtsi"
#include "tegra30-cpu-opp.dtsi"
#include "tegra30-cpu-opp-microvolt.dtsi"
/**
* This file contains common DT entry for all fab version of Cardhu.
@ -272,9 +274,14 @@
vddctrl_reg: vddctrl {
regulator-name = "vdd_cpu,vdd_sys";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1250000>;
regulator-coupled-with = <&vdd_core>;
regulator-coupled-max-spread = <300000>;
regulator-max-step-microvolt = <100000>;
regulator-always-on;
nvidia,tegra-cpu-regulator;
};
vio_reg: vio {
@ -342,17 +349,22 @@
interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>;
};
tps62361@60 {
vdd_core: tps62361@60 {
compatible = "ti,tps62361";
reg = <0x60>;
regulator-name = "tps62361-vout";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1500000>;
regulator-coupled-with = <&vddctrl_reg>;
regulator-coupled-max-spread = <300000>;
regulator-max-step-microvolt = <100000>;
regulator-boot-on;
regulator-always-on;
ti,vsel0-state-high;
ti,vsel1-state-high;
nvidia,tegra-core-regulator;
};
};
@ -424,6 +436,28 @@
#clock-cells = <0>;
};
cpus {
cpu0: cpu@0 {
cpu-supply = <&vddctrl_reg>;
operating-points-v2 = <&cpu0_opp_table>;
};
cpu1: cpu@1 {
cpu-supply = <&vddctrl_reg>;
operating-points-v2 = <&cpu0_opp_table>;
};
cpu2: cpu@2 {
cpu-supply = <&vddctrl_reg>;
operating-points-v2 = <&cpu0_opp_table>;
};
cpu3: cpu@3 {
cpu-supply = <&vddctrl_reg>;
operating-points-v2 = <&cpu0_opp_table>;
};
};
panel: panel {
compatible = "chunghwa,claa101wb01";
ddc-i2c-bus = <&panelddc>;