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Merge tag 'omap-for-v4.5/81xx-soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc

Browse Source 
Pull "reworked soc changes for ti81xx devices and minimal dra62x
j5ec-evm support" from Tony Lindgren:

Add minimal SoC support for dra62x also known as j5eco. As it's closely
related to dm814x, we can treat it as a dm814x variant for now and do
rest of the configuration with DTS just files. And let's add hwmod
support for MMC and USB on dm814x and dra62x.

* tag 'omap-for-v4.5/81xx-soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP2+: Add support for dm814x and dra62x usb
  ARM: OMAP2+: Add mmc hwmod entries for dm814x
  ARM: OMAP2+: Update 81xx clock and power domains for default, active and sgx
  ARM: OMAP2+: Fix SoC detection for dra62x j5-eco
This commit is contained in:
Arnd Bergmann 2015-12-31 16:24:09 +01:00
commit ed1c7848dc
5 changed files with 140 additions and 42 deletions
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29
arch/arm/mach-omap2/clockdomains81xx_data.c
View File

@ -83,6 +83,14 @@ static struct clockdomain mmu_cfg_81xx_clkdm = {
.flags = CLKDM_CAN_SWSUP, .flags = CLKDM_CAN_SWSUP,
}; };
static struct clockdomain default_l3_slow_81xx_clkdm = {
.name = "default_l3_slow_clkdm",
.pwrdm = { .name = "default_pwrdm" },
.cm_inst = TI81XX_CM_DEFAULT_MOD,
.clkdm_offs = TI816X_CM_DEFAULT_L3_SLOW_CLKDM,
.flags = CLKDM_CAN_SWSUP,
};
/* 816x only */ /* 816x only */
static struct clockdomain alwon_mpu_816x_clkdm = { static struct clockdomain alwon_mpu_816x_clkdm = {
@ -96,7 +104,7 @@ static struct clockdomain alwon_mpu_816x_clkdm = {
static struct clockdomain active_gem_816x_clkdm = { static struct clockdomain active_gem_816x_clkdm = {
.name = "active_gem_clkdm", .name = "active_gem_clkdm",
.pwrdm = { .name = "active_pwrdm" }, .pwrdm = { .name = "active_pwrdm" },
.cm_inst = TI816X_CM_ACTIVE_MOD, .cm_inst = TI81XX_CM_ACTIVE_MOD,
.clkdm_offs = TI816X_CM_ACTIVE_GEM_CLKDM, .clkdm_offs = TI816X_CM_ACTIVE_GEM_CLKDM,
.flags = CLKDM_CAN_SWSUP, .flags = CLKDM_CAN_SWSUP,
}; };
@ -128,7 +136,7 @@ static struct clockdomain ivahd2_816x_clkdm = {
static struct clockdomain sgx_816x_clkdm = { static struct clockdomain sgx_816x_clkdm = {
.name = "sgx_clkdm", .name = "sgx_clkdm",
.pwrdm = { .name = "sgx_pwrdm" }, .pwrdm = { .name = "sgx_pwrdm" },
.cm_inst = TI816X_CM_SGX_MOD, .cm_inst = TI81XX_CM_SGX_MOD,
.clkdm_offs = TI816X_CM_SGX_CLKDM, .clkdm_offs = TI816X_CM_SGX_CLKDM,
.flags = CLKDM_CAN_SWSUP, .flags = CLKDM_CAN_SWSUP,
}; };
@ -136,7 +144,7 @@ static struct clockdomain sgx_816x_clkdm = {
static struct clockdomain default_l3_med_816x_clkdm = { static struct clockdomain default_l3_med_816x_clkdm = {
.name = "default_l3_med_clkdm", .name = "default_l3_med_clkdm",
.pwrdm = { .name = "default_pwrdm" }, .pwrdm = { .name = "default_pwrdm" },
.cm_inst = TI816X_CM_DEFAULT_MOD, .cm_inst = TI81XX_CM_DEFAULT_MOD,
.clkdm_offs = TI816X_CM_DEFAULT_L3_MED_CLKDM, .clkdm_offs = TI816X_CM_DEFAULT_L3_MED_CLKDM,
.flags = CLKDM_CAN_SWSUP, .flags = CLKDM_CAN_SWSUP,
}; };
@ -144,7 +152,7 @@ static struct clockdomain default_l3_med_816x_clkdm = {
static struct clockdomain default_ducati_816x_clkdm = { static struct clockdomain default_ducati_816x_clkdm = {
.name = "default_ducati_clkdm", .name = "default_ducati_clkdm",
.pwrdm = { .name = "default_pwrdm" }, .pwrdm = { .name = "default_pwrdm" },
.cm_inst = TI816X_CM_DEFAULT_MOD, .cm_inst = TI81XX_CM_DEFAULT_MOD,
.clkdm_offs = TI816X_CM_DEFAULT_DUCATI_CLKDM, .clkdm_offs = TI816X_CM_DEFAULT_DUCATI_CLKDM,
.flags = CLKDM_CAN_SWSUP, .flags = CLKDM_CAN_SWSUP,
}; };
@ -152,19 +160,11 @@ static struct clockdomain default_ducati_816x_clkdm = {
static struct clockdomain default_pci_816x_clkdm = { static struct clockdomain default_pci_816x_clkdm = {
.name = "default_pci_clkdm", .name = "default_pci_clkdm",
.pwrdm = { .name = "default_pwrdm" }, .pwrdm = { .name = "default_pwrdm" },
.cm_inst = TI816X_CM_DEFAULT_MOD, .cm_inst = TI81XX_CM_DEFAULT_MOD,
.clkdm_offs = TI816X_CM_DEFAULT_PCI_CLKDM, .clkdm_offs = TI816X_CM_DEFAULT_PCI_CLKDM,
.flags = CLKDM_CAN_SWSUP, .flags = CLKDM_CAN_SWSUP,
}; };
static struct clockdomain default_l3_slow_816x_clkdm = {
.name = "default_l3_slow_clkdm",
.pwrdm = { .name = "default_pwrdm" },
.cm_inst = TI816X_CM_DEFAULT_MOD,
.clkdm_offs = TI816X_CM_DEFAULT_L3_SLOW_CLKDM,
.flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain *clockdomains_ti814x[] __initdata = { static struct clockdomain *clockdomains_ti814x[] __initdata = {
&alwon_l3_slow_81xx_clkdm, &alwon_l3_slow_81xx_clkdm,
&alwon_l3_med_81xx_clkdm, &alwon_l3_med_81xx_clkdm,
@ -172,6 +172,7 @@ static struct clockdomain *clockdomains_ti814x[] __initdata = {
&alwon_ethernet_81xx_clkdm, &alwon_ethernet_81xx_clkdm,
&mmu_81xx_clkdm, &mmu_81xx_clkdm,
&mmu_cfg_81xx_clkdm, &mmu_cfg_81xx_clkdm,
&default_l3_slow_81xx_clkdm,
NULL, NULL,
}; };
@ -198,7 +199,7 @@ static struct clockdomain *clockdomains_ti816x[] __initdata = {
&default_l3_med_816x_clkdm, &default_l3_med_816x_clkdm,
&default_ducati_816x_clkdm, &default_ducati_816x_clkdm,
&default_pci_816x_clkdm, &default_pci_816x_clkdm,
&default_l3_slow_816x_clkdm, &default_l3_slow_81xx_clkdm,
NULL, NULL,
}; };

6
arch/arm/mach-omap2/cm81xx.h
View File

@ -18,15 +18,15 @@
#define __ARCH_ARM_MACH_OMAP2_CM_TI81XX_H #define __ARCH_ARM_MACH_OMAP2_CM_TI81XX_H
/* TI81XX common CM module offsets */ /* TI81XX common CM module offsets */
#define TI81XX_CM_ACTIVE_MOD 0x0400 /* 256B */
#define TI81XX_CM_DEFAULT_MOD 0x0500 /* 256B */
#define TI81XX_CM_ALWON_MOD 0x1400 /* 1KB */ #define TI81XX_CM_ALWON_MOD 0x1400 /* 1KB */
#define TI81XX_CM_SGX_MOD 0x0900 /* 256B */
/* TI816X CM module offsets */ /* TI816X CM module offsets */
#define TI816X_CM_ACTIVE_MOD 0x0400 /* 256B */
#define TI816X_CM_DEFAULT_MOD 0x0500 /* 256B */
#define TI816X_CM_IVAHD0_MOD 0x0600 /* 256B */ #define TI816X_CM_IVAHD0_MOD 0x0600 /* 256B */
#define TI816X_CM_IVAHD1_MOD 0x0700 /* 256B */ #define TI816X_CM_IVAHD1_MOD 0x0700 /* 256B */
#define TI816X_CM_IVAHD2_MOD 0x0800 /* 256B */ #define TI816X_CM_IVAHD2_MOD 0x0800 /* 256B */
#define TI816X_CM_SGX_MOD 0x0900 /* 256B */
/* ALWON */ /* ALWON */
#define TI81XX_CM_ALWON_L3_SLOW_CLKDM 0x0000 #define TI81XX_CM_ALWON_L3_SLOW_CLKDM 0x0000

4
arch/arm/mach-omap2/id.c
View File

@ -488,6 +488,7 @@ void __init omap3xxx_check_revision(void)
} }
break; break;
case 0xb8f2: case 0xb8f2:
case 0xb968:
switch (rev) { switch (rev) {
case 0: case 0:
/* FALLTHROUGH */ /* FALLTHROUGH */
@ -511,7 +512,8 @@ void __init omap3xxx_check_revision(void)
/* Unknown default to latest silicon rev as default */ /* Unknown default to latest silicon rev as default */
omap_revision = OMAP3630_REV_ES1_2; omap_revision = OMAP3630_REV_ES1_2;
cpu_rev = "1.2"; cpu_rev = "1.2";
pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n"); pr_warn("Warning: unknown chip type: hawkeye %04x, assuming OMAP3630ES1.2\n",
hawkeye);
} }
sprintf(soc_rev, "ES%s", cpu_rev); sprintf(soc_rev, "ES%s", cpu_rev);
} }

133
arch/arm/mach-omap2/omap_hwmod_81xx_data.c
View File

@ -104,8 +104,8 @@
* The default .clkctrl_offs field is offset from CM_DEFAULT, that's * The default .clkctrl_offs field is offset from CM_DEFAULT, that's
* TRM 18.7.6 CM_DEFAULT device register values minus 0x500 * TRM 18.7.6 CM_DEFAULT device register values minus 0x500
*/ */
#define DM816X_CM_DEFAULT_OFFSET 0x500 #define DM81XX_CM_DEFAULT_OFFSET 0x500
#define DM816X_CM_DEFAULT_USB_CLKCTRL (0x558 - DM816X_CM_DEFAULT_OFFSET) #define DM81XX_CM_DEFAULT_USB_CLKCTRL (0x558 - DM81XX_CM_DEFAULT_OFFSET)
/* L3 Interconnect entries clocked at 125, 250 and 500MHz */ /* L3 Interconnect entries clocked at 125, 250 and 500MHz */
static struct omap_hwmod dm81xx_alwon_l3_slow_hwmod = { static struct omap_hwmod dm81xx_alwon_l3_slow_hwmod = {
@ -557,22 +557,42 @@ static struct omap_hwmod_class dm81xx_usbotg_class = {
.sysc = &dm81xx_usbhsotg_sysc, .sysc = &dm81xx_usbhsotg_sysc,
}; };
static struct omap_hwmod dm81xx_usbss_hwmod = { static struct omap_hwmod dm814x_usbss_hwmod = {
.name = "usb_otg_hs", .name = "usb_otg_hs",
.clkdm_name = "default_l3_slow_clkdm", .clkdm_name = "default_l3_slow_clkdm",
.main_clk = "sysclk6_ck", .main_clk = "pll260dcoclkldo", /* 481c5260.adpll.dcoclkldo */
.prcm = { .prcm = {
.omap4 = { .omap4 = {
.clkctrl_offs = DM816X_CM_DEFAULT_USB_CLKCTRL, .clkctrl_offs = DM81XX_CM_DEFAULT_USB_CLKCTRL,
.modulemode = MODULEMODE_SWCTRL, .modulemode = MODULEMODE_SWCTRL,
}, },
}, },
.class = &dm81xx_usbotg_class, .class = &dm81xx_usbotg_class,
}; };
static struct omap_hwmod_ocp_if dm81xx_default_l3_slow__usbss = { static struct omap_hwmod_ocp_if dm814x_default_l3_slow__usbss = {
.master = &dm81xx_default_l3_slow_hwmod, .master = &dm81xx_default_l3_slow_hwmod,
.slave = &dm81xx_usbss_hwmod, .slave = &dm814x_usbss_hwmod,
.clk = "sysclk6_ck",
.user = OCP_USER_MPU,
};
static struct omap_hwmod dm816x_usbss_hwmod = {
.name = "usb_otg_hs",
.clkdm_name = "default_l3_slow_clkdm",
.main_clk = "sysclk6_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = DM81XX_CM_DEFAULT_USB_CLKCTRL,
.modulemode = MODULEMODE_SWCTRL,
},
},
.class = &dm81xx_usbotg_class,
};
static struct omap_hwmod_ocp_if dm816x_default_l3_slow__usbss = {
.master = &dm81xx_default_l3_slow_hwmod,
.slave = &dm816x_usbss_hwmod,
.clk = "sysclk6_ck", .clk = "sysclk6_ck",
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
@ -912,7 +932,7 @@ static struct omap_hwmod_ocp_if dm816x_l4_hs__emac1 = {
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
static struct omap_hwmod_class_sysconfig dm816x_mmc_sysc = { static struct omap_hwmod_class_sysconfig dm81xx_mmc_sysc = {
.rev_offs = 0x0, .rev_offs = 0x0,
.sysc_offs = 0x110, .sysc_offs = 0x110,
.syss_offs = 0x114, .syss_offs = 0x114,
@ -923,24 +943,94 @@ static struct omap_hwmod_class_sysconfig dm816x_mmc_sysc = {
.sysc_fields = &omap_hwmod_sysc_type1, .sysc_fields = &omap_hwmod_sysc_type1,
}; };
static struct omap_hwmod_class dm816x_mmc_class = { static struct omap_hwmod_class dm81xx_mmc_class = {
.name = "mmc", .name = "mmc",
.sysc = &dm816x_mmc_sysc, .sysc = &dm81xx_mmc_sysc,
}; };
static struct omap_hwmod_opt_clk dm816x_mmc1_opt_clks[] = { static struct omap_hwmod_opt_clk dm81xx_mmc_opt_clks[] = {
{ .role = "dbck", .clk = "sysclk18_ck", }, { .role = "dbck", .clk = "sysclk18_ck", },
}; };
static struct omap_hsmmc_dev_attr mmc1_dev_attr = { static struct omap_hsmmc_dev_attr mmc_dev_attr = {
.flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, };
static struct omap_hwmod dm814x_mmc1_hwmod = {
.name = "mmc1",
.clkdm_name = "alwon_l3s_clkdm",
.opt_clks = dm81xx_mmc_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks),
.main_clk = "sysclk8_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = DM814X_CM_ALWON_MMCHS_0_CLKCTRL,
.modulemode = MODULEMODE_SWCTRL,
},
},
.dev_attr = &mmc_dev_attr,
.class = &dm81xx_mmc_class,
};
static struct omap_hwmod_ocp_if dm814x_l4_ls__mmc1 = {
.master = &dm81xx_l4_ls_hwmod,
.slave = &dm814x_mmc1_hwmod,
.clk = "sysclk6_ck",
.user = OCP_USER_MPU,
.flags = OMAP_FIREWALL_L4
};
static struct omap_hwmod dm814x_mmc2_hwmod = {
.name = "mmc2",
.clkdm_name = "alwon_l3s_clkdm",
.opt_clks = dm81xx_mmc_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks),
.main_clk = "sysclk8_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = DM814X_CM_ALWON_MMCHS_1_CLKCTRL,
.modulemode = MODULEMODE_SWCTRL,
},
},
.dev_attr = &mmc_dev_attr,
.class = &dm81xx_mmc_class,
};
static struct omap_hwmod_ocp_if dm814x_l4_ls__mmc2 = {
.master = &dm81xx_l4_ls_hwmod,
.slave = &dm814x_mmc2_hwmod,
.clk = "sysclk6_ck",
.user = OCP_USER_MPU,
.flags = OMAP_FIREWALL_L4
};
static struct omap_hwmod dm814x_mmc3_hwmod = {
.name = "mmc3",
.clkdm_name = "alwon_l3_med_clkdm",
.opt_clks = dm81xx_mmc_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks),
.main_clk = "sysclk8_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = DM814X_CM_ALWON_MMCHS_2_CLKCTRL,
.modulemode = MODULEMODE_SWCTRL,
},
},
.dev_attr = &mmc_dev_attr,
.class = &dm81xx_mmc_class,
};
static struct omap_hwmod_ocp_if dm814x_alwon_l3_med__mmc3 = {
.master = &dm81xx_alwon_l3_med_hwmod,
.slave = &dm814x_mmc3_hwmod,
.clk = "sysclk4_ck",
.user = OCP_USER_MPU,
}; };
static struct omap_hwmod dm816x_mmc1_hwmod = { static struct omap_hwmod dm816x_mmc1_hwmod = {
.name = "mmc1", .name = "mmc1",
.clkdm_name = "alwon_l3s_clkdm", .clkdm_name = "alwon_l3s_clkdm",
.opt_clks = dm816x_mmc1_opt_clks, .opt_clks = dm81xx_mmc_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(dm816x_mmc1_opt_clks), .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks),
.main_clk = "sysclk10_ck", .main_clk = "sysclk10_ck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
@ -948,8 +1038,8 @@ static struct omap_hwmod dm816x_mmc1_hwmod = {
.modulemode = MODULEMODE_SWCTRL, .modulemode = MODULEMODE_SWCTRL,
}, },
}, },
.dev_attr = &mmc1_dev_attr, .dev_attr = &mmc_dev_attr,
.class = &dm816x_mmc_class, .class = &dm81xx_mmc_class,
}; };
static struct omap_hwmod_ocp_if dm816x_l4_ls__mmc1 = { static struct omap_hwmod_ocp_if dm816x_l4_ls__mmc1 = {
@ -1267,8 +1357,6 @@ static struct omap_hwmod_ocp_if dm81xx_tptc3__alwon_l3_fast = {
* dm81xx_l4_ls__gpio1 * dm81xx_l4_ls__gpio1
* dm81xx_l4_ls__gpio2 * dm81xx_l4_ls__gpio2
* dm81xx_l4_ls__mailbox * dm81xx_l4_ls__mailbox
* dm81xx_alwon_l3_slow__gpmc
* dm81xx_default_l3_slow__usbss
* *
* Also note that some devices share a single clkctrl_offs.. * Also note that some devices share a single clkctrl_offs..
* For example, i2c1 and 3 share one, and i2c2 and 4 share one. * For example, i2c1 and 3 share one, and i2c2 and 4 share one.
@ -1286,6 +1374,8 @@ static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = {
&dm81xx_l4_ls__i2c2, &dm81xx_l4_ls__i2c2,
&dm81xx_l4_ls__elm, &dm81xx_l4_ls__elm,
&dm81xx_l4_ls__mcspi1, &dm81xx_l4_ls__mcspi1,
&dm814x_l4_ls__mmc1,
&dm814x_l4_ls__mmc2,
&dm81xx_alwon_l3_fast__tpcc, &dm81xx_alwon_l3_fast__tpcc,
&dm81xx_alwon_l3_fast__tptc0, &dm81xx_alwon_l3_fast__tptc0,
&dm81xx_alwon_l3_fast__tptc1, &dm81xx_alwon_l3_fast__tptc1,
@ -1299,6 +1389,9 @@ static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = {
&dm814x_l4_ls__timer2, &dm814x_l4_ls__timer2,
&dm814x_l4_hs__cpgmac0, &dm814x_l4_hs__cpgmac0,
&dm814x_cpgmac0__mdio, &dm814x_cpgmac0__mdio,
&dm81xx_alwon_l3_slow__gpmc,
&dm814x_default_l3_slow__usbss,
&dm814x_alwon_l3_med__mmc3,
NULL, NULL,
}; };
@ -1346,7 +1439,7 @@ static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = {
&dm81xx_tptc2__alwon_l3_fast, &dm81xx_tptc2__alwon_l3_fast,
&dm81xx_tptc3__alwon_l3_fast, &dm81xx_tptc3__alwon_l3_fast,
&dm81xx_alwon_l3_slow__gpmc, &dm81xx_alwon_l3_slow__gpmc,
&dm81xx_default_l3_slow__usbss, &dm816x_default_l3_slow__usbss,
NULL, NULL,
}; };

10
arch/arm/mach-omap2/powerdomains3xxx_data.c
View File

@ -384,14 +384,14 @@ static struct powerdomain isp_814x_pwrdm = {
.voltdm = { .name = "core" }, .voltdm = { .name = "core" },
}; };
static struct powerdomain active_816x_pwrdm = { static struct powerdomain active_81xx_pwrdm = {
.name = "active_pwrdm", .name = "active_pwrdm",
.prcm_offs = TI816X_PRM_ACTIVE_MOD, .prcm_offs = TI816X_PRM_ACTIVE_MOD,
.pwrsts = PWRSTS_OFF_ON, .pwrsts = PWRSTS_OFF_ON,
.voltdm = { .name = "core" }, .voltdm = { .name = "core" },
}; };
static struct powerdomain default_816x_pwrdm = { static struct powerdomain default_81xx_pwrdm = {
.name = "default_pwrdm", .name = "default_pwrdm",
.prcm_offs = TI81XX_PRM_DEFAULT_MOD, .prcm_offs = TI81XX_PRM_DEFAULT_MOD,
.pwrsts = PWRSTS_OFF_ON, .pwrsts = PWRSTS_OFF_ON,
@ -486,6 +486,8 @@ static struct powerdomain *powerdomains_am35x[] __initdata = {
static struct powerdomain *powerdomains_ti814x[] __initdata = { static struct powerdomain *powerdomains_ti814x[] __initdata = {
&alwon_81xx_pwrdm, &alwon_81xx_pwrdm,
&device_81xx_pwrdm, &device_81xx_pwrdm,
&active_81xx_pwrdm,
&default_81xx_pwrdm,
&gem_814x_pwrdm, &gem_814x_pwrdm,
&ivahd_814x_pwrdm, &ivahd_814x_pwrdm,
&hdvpss_814x_pwrdm, &hdvpss_814x_pwrdm,
@ -497,8 +499,8 @@ static struct powerdomain *powerdomains_ti814x[] __initdata = {
static struct powerdomain *powerdomains_ti816x[] __initdata = { static struct powerdomain *powerdomains_ti816x[] __initdata = {
&alwon_81xx_pwrdm, &alwon_81xx_pwrdm,
&device_81xx_pwrdm, &device_81xx_pwrdm,
&active_816x_pwrdm, &active_81xx_pwrdm,
&default_816x_pwrdm, &default_81xx_pwrdm,
&ivahd0_816x_pwrdm, &ivahd0_816x_pwrdm,
&ivahd1_816x_pwrdm, &ivahd1_816x_pwrdm,
&ivahd2_816x_pwrdm, &ivahd2_816x_pwrdm,