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Merge branch 'for-3.4/cleanup-and-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra into tegra/cleanups

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* 'for-3.4/cleanup-and-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra:
  ARM: tegra: select USB_ULPI if USB is selected
  arm/tegra: pcie: fix return value of function
  arm/tegra: add timeout to PCIe PLL lock detection loop
  arm/tegra: fix harmony pinmux for PCIe
This commit is contained in:
Arnd Bergmann 2012-03-19 21:00:48 +00:00
commit ed1b4acc43
3 changed files with 17 additions and 9 deletions
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4
arch/arm/mach-tegra/Kconfig
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@ -8,7 +8,7 @@ config ARCH_TEGRA_2x_SOC
select ARM_GIC select ARM_GIC
select ARCH_REQUIRE_GPIOLIB select ARCH_REQUIRE_GPIOLIB
select USB_ARCH_HAS_EHCI if USB_SUPPORT select USB_ARCH_HAS_EHCI if USB_SUPPORT
select USB_ULPI if USB_SUPPORT select USB_ULPI if USB
select USB_ULPI_VIEWPORT if USB_SUPPORT select USB_ULPI_VIEWPORT if USB_SUPPORT
select ARM_ERRATA_720789 select ARM_ERRATA_720789
select ARM_ERRATA_742230 select ARM_ERRATA_742230
@ -28,7 +28,7 @@ config ARCH_TEGRA_3x_SOC
select ARM_GIC select ARM_GIC
select ARCH_REQUIRE_GPIOLIB select ARCH_REQUIRE_GPIOLIB
select USB_ARCH_HAS_EHCI if USB_SUPPORT select USB_ARCH_HAS_EHCI if USB_SUPPORT
select USB_ULPI if USB_SUPPORT select USB_ULPI if USB
select USB_ULPI_VIEWPORT if USB_SUPPORT select USB_ULPI_VIEWPORT if USB_SUPPORT
select USE_OF select USE_OF
select ARM_ERRATA_743622 select ARM_ERRATA_743622

6
arch/arm/mach-tegra/board-harmony-pinmux.c
View File

@ -53,7 +53,7 @@ static struct tegra_pingroup_config harmony_pinmux[] = {
{TEGRA_PINGROUP_GME, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_GME, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_GPU, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_GPU, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
@ -112,10 +112,10 @@ static struct tegra_pingroup_config harmony_pinmux[] = {
{TEGRA_PINGROUP_SDC, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_SDC, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_SDD, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_SDD, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_SLXC, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_SLXD, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_SLXD, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_SPDI, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_SPDI, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_SPDO, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_SPDO, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},

16
arch/arm/mach-tegra/pcie.c
View File

@ -585,10 +585,10 @@ static void tegra_pcie_setup_translations(void)
afi_writel(0, AFI_MSI_BAR_SZ); afi_writel(0, AFI_MSI_BAR_SZ);
} }
static void tegra_pcie_enable_controller(void) static int tegra_pcie_enable_controller(void)
{ {
u32 val, reg; u32 val, reg;
int i; int i, timeout;
/* Enable slot clock and pulse the reset signals */ /* Enable slot clock and pulse the reset signals */
for (i = 0, reg = AFI_PEX0_CTRL; i < 2; i++, reg += 0x8) { for (i = 0, reg = AFI_PEX0_CTRL; i < 2; i++, reg += 0x8) {
@ -639,8 +639,14 @@ static void tegra_pcie_enable_controller(void)
pads_writel(0xfa5cfa5c, 0xc8); pads_writel(0xfa5cfa5c, 0xc8);
/* Wait for the PLL to lock */ /* Wait for the PLL to lock */
timeout = 300;
do { do {
val = pads_readl(PADS_PLL_CTL); val = pads_readl(PADS_PLL_CTL);
usleep_range(1000, 1000);
if (--timeout == 0) {
pr_err("Tegra PCIe error: timeout waiting for PLL\n");
return -EBUSY;
}
} while (!(val & PADS_PLL_CTL_LOCKDET)); } while (!(val & PADS_PLL_CTL_LOCKDET));
/* turn off IDDQ override */ /* turn off IDDQ override */
@ -671,7 +677,7 @@ static void tegra_pcie_enable_controller(void)
/* Disable all execptions */ /* Disable all execptions */
afi_writel(0, AFI_FPCI_ERROR_MASKS); afi_writel(0, AFI_FPCI_ERROR_MASKS);
return; return 0;
} }
static void tegra_pcie_xclk_clamp(bool clamp) static void tegra_pcie_xclk_clamp(bool clamp)
@ -921,7 +927,9 @@ int __init tegra_pcie_init(bool init_port0, bool init_port1)
if (err) if (err)
return err; return err;
tegra_pcie_enable_controller(); err = tegra_pcie_enable_controller();
if (err)
return err;
/* setup the AFI address translations */ /* setup the AFI address translations */
tegra_pcie_setup_translations(); tegra_pcie_setup_translations();