leandrof/linux
1
0
Fork 0
forked from Minki/linux
Code Issues Pull Requests Packages Projects Releases Wiki Activity

ARM: ARMv4T/v5 multiplatform support for v5.19, part 1

Browse Source 
This series has been 12 years in the making, it mostly finishes the
 work that was started with the founding of Linaro to clean up platform
 support in the kernel.
 
 The largest change here is a cleanup of the omap1 platform, which
 is the final ARM machine type to get converted to the common-clk
 subsystem. All the omap1 specific drivers are now made independent of the
 mach/*.h headers to allow the platform to be part of a generic ARMv4/v5
 multiplatform kernel. The last bit that enables this support is still
 missing here while we wait for some last dependencies to make it into
 the mainline kernel through other subsystems.
 
 The s3c24xx, ixp4xx, iop32x, ep93xx and dove platforms were all almost
 at the point of allowing multiplatform kernels, this work gets completed
 here along with a few additional cleanup.  At the same time, the s3c24xx
 and s3c64xx are now deprecated and expected to get removed in the future.
 
 The PXA and OMAP1 bits are in a separate branch because of dependencies.
 Once both branches are merged, only the three Intel StrongARM platforms
 (RiscPC, Footbridge/NetWinder and StrongARM1100) need separate kernels,
 and there are no plans to include these.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmKOP3sACgkQmmx57+YA
 GNk+DhAAmrPNuS8JDlCRPa76Nd9PC9aitnnEGYytQ6bgwexKd3qdvP7gdUtr7jlV
 8k4KiGnnZZjEGd4i5cAVhSCyBbCt4oPKhato62KneEsO19xLsVmmTpQg1LPK75do
 mHYKpc+6932Lp6WrtI1F75id0phx684tpZp9P4ggXwMwgYkagq9rcO+mGUNZWDc8
 D9SdAmoObtSCoBCYYbq2VhAPA79mSKKVpLGehzd+Gq5cuf/jJQD0u1E00izkdyZc
 r/5acQ7PHQlVXqSONYgCpkvDTqmjg9cvVCKeKLpFspV3f6vBVRgV60UGfwhpdPHY
 N119KUJtPf81xnLSxsqBFA34LMSerrH72YM5cYupKiiYcTDr+Yw6zrtNR6ktkt/B
 F1Tc/QV+A9CGergxljy39G1smEuwKtNiVA//NSlUORCHxgwa5XUB0mQIzNcWARa4
 oMDLhBF7ES211CB7Yto2FR6gBQbh2A9HSpjOh6kxdHrRb4FCgoXjPhzBoMxPoSFu
 XIzJpMb18K4bI+hKRYddEOK5V0kHt9mzT7ViGT/2+n13IHKIGmKrZxwDH7mohAW9
 4GF77gGbQsE9szajkx5EG1t+PWextQeeMyYW05bXO/mbDwA0n7EdjGpBeedvTZw3
 6gUWVahfYp9hZWPdxJ4fbGnlbSovCq0y4tj5fbZHPh6AOAtmvWY=
 =CTtN
 -----END PGP SIGNATURE-----

Merge tag 'arm-multiplatform-5.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARMv4T/v5 multiplatform support from Arnd Bergmann:
 "This series has been 12 years in the making, it mostly finishes the
  work that was started with the founding of Linaro to clean up platform
  support in the kernel.

  The largest change here is a cleanup of the omap1 platform, which is
  the final ARM machine type to get converted to the common-clk
  subsystem. All the omap1 specific drivers are now made independent of
  the mach/*.h headers to allow the platform to be part of a generic
  ARMv4/v5 multiplatform kernel.

  The last bit that enables this support is still missing here while we
  wait for some last dependencies to make it into the mainline kernel
  through other subsystems.

  The s3c24xx, ixp4xx, iop32x, ep93xx and dove platforms were all almost
  at the point of allowing multiplatform kernels, this work gets
  completed here along with a few additional cleanup. At the same time,
  the s3c24xx and s3c64xx are now deprecated and expected to get removed
  in the future.

  The PXA and OMAP1 bits are in a separate branch because of
  dependencies. Once both branches are merged, only the three Intel
  StrongARM platforms (RiscPC, Footbridge/NetWinder and StrongARM1100)
  need separate kernels, and there are no plans to include these"

* tag 'arm-multiplatform-5.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (61 commits)
  ARM: ixp4xx: Consolidate Kconfig fixing issue
  ARM: versatile: Add missing of_node_put in dcscb_init
  ARM: config: Refresh IXP4xx config after multiplatform
  ARM: omap1: add back omap_set_dma_priority() stub
  ARM: omap: fix missing declaration warnings
  ARM: omap: fix address space warnings from sparse
  ARM: spear: remove include/mach/ subdirectory
  ARM: davinci: remove include/mach/ subdirectory
  ARM: omap2: remove include/mach/ subdirectory
  integrator: remove empty ap_init_early()
  ARM: s3c: fix include path
  MAINTAINERS: omap1: Add Janusz as an additional maintainer
  ARM: omap1: htc_herald: fix typos in comments
  ARM: OMAP1: fix typos in comments
  ARM: OMAP1: clock: Remove noop code
  ARM: OMAP1: clock: Remove unused code
  ARM: OMAP1: clock: Fix UART rate reporting algorithm
  ARM: OMAP1: clock: Fix early UART rate issues
  ARM: OMAP1: Prepare for conversion of OMAP1 clocks to CCF
  ARM: omap1: fix build with no SoC selected
  ...
This commit is contained in:
Linus Torvalds 2022-05-26 10:43:09 -07:00
commit ecf0aa5317
346 changed files with 3134 additions and 4111 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
MAINTAINERS
View File

@ -1526,10 +1526,7 @@ F: Documentation/devicetree/bindings/mtd/mtd-physmap.yaml
F: arch/arm/boot/dts/arm-realview-*
F: arch/arm/boot/dts/integrator*
F: arch/arm/boot/dts/versatile*
F: arch/arm/mach-integrator/
F: arch/arm/mach-realview/
F: arch/arm/mach-versatile/
F: arch/arm/plat-versatile/
F: drivers/bus/arm-integrator-lm.c
F: drivers/clk/versatile/
F: drivers/i2c/busses/i2c-versatile.c
@ -14510,6 +14507,7 @@ F: arch/arm/boot/dts/am335x-nano.dts
OMAP1 SUPPORT
M: Aaro Koskinen <aaro.koskinen@iki.fi>
M: Janusz Krzysztofik <jmkrzyszt@gmail.com>
M: Tony Lindgren <tony@atomide.com>
L: linux-omap@vger.kernel.org
S: Maintained

93
arch/arm/Kconfig
View File

@ -347,22 +347,9 @@ config ARCH_MULTIPLATFORM
select SPARSE_IRQ
select USE_OF
config ARCH_EP93XX
bool "EP93xx-based"
select ARCH_SPARSEMEM_ENABLE
select ARM_AMBA
imply ARM_PATCH_PHYS_VIRT
select ARM_VIC
select AUTO_ZRELADDR
select CLKSRC_MMIO
select CPU_ARM920T
select GPIOLIB
select COMMON_CLK
help
This enables support for the Cirrus EP93xx series of CPUs.
config ARCH_FOOTBRIDGE
bool "FootBridge"
depends on CPU_LITTLE_ENDIAN
select CPU_SA110
select FOOTBRIDGE
select NEED_MACH_MEMORY_H
@ -370,49 +357,9 @@ config ARCH_FOOTBRIDGE
Support for systems based on the DC21285 companion chip
("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
config ARCH_IOP32X
bool "IOP32x-based"
select CPU_XSCALE
select GPIO_IOP
select GPIOLIB
select FORCE_PCI
select PLAT_IOP
help
Support for Intel's 80219 and IOP32X (XScale) family of
processors.
config ARCH_IXP4XX
bool "IXP4xx-based"
select ARCH_SUPPORTS_BIG_ENDIAN
select ARM_PATCH_PHYS_VIRT
select CPU_XSCALE
select GPIO_IXP4XX
select GPIOLIB
select HAVE_PCI
select IXP4XX_IRQ
select IXP4XX_TIMER
select SPARSE_IRQ
select USB_EHCI_BIG_ENDIAN_DESC
select USB_EHCI_BIG_ENDIAN_MMIO
help
Support for Intel's IXP4XX (XScale) family of processors.
config ARCH_DOVE
bool "Marvell Dove"
select CPU_PJ4
select GPIOLIB
select HAVE_PCI
select MVEBU_MBUS
select PINCTRL
select PINCTRL_DOVE
select PLAT_ORION_LEGACY
select SPARSE_IRQ
select PM_GENERIC_DOMAINS if PM
help
Support for the Marvell Dove SoC 88AP510
config ARCH_PXA
bool "PXA2xx/PXA3xx-based"
depends on CPU_LITTLE_ENDIAN
select ARCH_MTD_XIP
select ARM_CPU_SUSPEND if PM
select AUTO_ZRELADDR
@ -432,6 +379,7 @@ config ARCH_PXA
config ARCH_RPC
bool "RiscPC"
depends on !CC_IS_CLANG && GCC_VERSION < 90100 && GCC_VERSION >= 60000
depends on CPU_LITTLE_ENDIAN
select ARCH_ACORN
select ARCH_MAY_HAVE_PC_FDC
select ARCH_SPARSEMEM_ENABLE
@ -450,6 +398,7 @@ config ARCH_RPC
config ARCH_SA1100
bool "SA1100-based"
depends on CPU_LITTLE_ENDIAN
select ARCH_MTD_XIP
select ARCH_SPARSEMEM_ENABLE
select CLKSRC_MMIO
@ -466,33 +415,15 @@ config ARCH_SA1100
help
Support for StrongARM 11x0 based boards.
config ARCH_S3C24XX
bool "Samsung S3C24XX SoCs"
select ATAGS
select CLKSRC_SAMSUNG_PWM
select GPIO_SAMSUNG
select GPIOLIB
select NEED_MACH_IO_H
select S3C2410_WATCHDOG
select SAMSUNG_ATAGS
select USE_OF
select WATCHDOG
help
Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
(<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
Samsung SMDK2410 development board (and derivatives).
config ARCH_OMAP1
bool "TI OMAP1"
select ARCH_OMAP
depends on CPU_LITTLE_ENDIAN
select CLKSRC_MMIO
select FORCE_PCI if PCCARD
select GENERIC_IRQ_CHIP
select GPIOLIB
select HAVE_LEGACY_CLK
select IRQ_DOMAIN
select NEED_MACH_IO_H if PCCARD
select NEED_MACH_MEMORY_H
select SPARSE_IRQ
help
Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
@ -561,7 +492,6 @@ config ARCH_VIRT
select ARM_GIC_V3_ITS if PCI
select ARM_PSCI
select HAVE_ARM_ARCH_TIMER
select ARCH_SUPPORTS_BIG_ENDIAN
config ARCH_AIROHA
bool "Airoha SoC Support"
@ -622,8 +552,6 @@ source "arch/arm/mach-hisi/Kconfig"
source "arch/arm/mach-imx/Kconfig"
source "arch/arm/mach-integrator/Kconfig"
source "arch/arm/mach-iop32x/Kconfig"
source "arch/arm/mach-ixp4xx/Kconfig"
@ -656,8 +584,6 @@ source "arch/arm/mach-npcm/Kconfig"
source "arch/arm/mach-nspire/Kconfig"
source "arch/arm/plat-omap/Kconfig"
source "arch/arm/mach-omap1/Kconfig"
source "arch/arm/mach-omap2/Kconfig"
@ -675,8 +601,6 @@ source "arch/arm/mach-rda/Kconfig"
source "arch/arm/mach-realtek/Kconfig"
source "arch/arm/mach-realview/Kconfig"
source "arch/arm/mach-rockchip/Kconfig"
source "arch/arm/mach-s3c/Kconfig"
@ -705,8 +629,6 @@ source "arch/arm/mach-ux500/Kconfig"
source "arch/arm/mach-versatile/Kconfig"
source "arch/arm/mach-vexpress/Kconfig"
source "arch/arm/mach-vt8500/Kconfig"
source "arch/arm/mach-zynq/Kconfig"
@ -739,9 +661,6 @@ config ARCH_MPS2
config ARCH_ACORN
bool
config PLAT_IOP
bool
config PLAT_ORION
bool
select CLKSRC_MMIO

6
arch/arm/Kconfig.debug
View File

@ -1859,9 +1859,9 @@ config DEBUG_UART_VIRT
default 0xfec00000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN
default 0xfec00003 if ARCH_IXP4XX && CPU_BIG_ENDIAN
default 0xfef36000 if DEBUG_HIGHBANK_UART
default 0xfefb0000 if DEBUG_OMAP1UART1 || DEBUG_OMAP7XXUART1
default 0xfefb0800 if DEBUG_OMAP1UART2 || DEBUG_OMAP7XXUART2
default 0xfefb9800 if DEBUG_OMAP1UART3 || DEBUG_OMAP7XXUART3
default 0xff0b0000 if DEBUG_OMAP1UART1 || DEBUG_OMAP7XXUART1
default 0xff0b0800 if DEBUG_OMAP1UART2 || DEBUG_OMAP7XXUART2
default 0xff0b9800 if DEBUG_OMAP1UART3 || DEBUG_OMAP7XXUART3
default 0xffd01000 if DEBUG_HIP01_UART
default DEBUG_UART_PHYS if !MMU
depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \

8
arch/arm/Makefile
View File

@ -179,7 +179,6 @@ machine-$(CONFIG_ARCH_FOOTBRIDGE) += footbridge
machine-$(CONFIG_ARCH_GEMINI) += gemini
machine-$(CONFIG_ARCH_HIGHBANK) += highbank
machine-$(CONFIG_ARCH_HISI) += hisi
machine-$(CONFIG_ARCH_INTEGRATOR) += integrator
machine-$(CONFIG_ARCH_IOP32X) += iop32x
machine-$(CONFIG_ARCH_IXP4XX) += ixp4xx
machine-$(CONFIG_ARCH_KEYSTONE) += keystone
@ -187,7 +186,6 @@ machine-$(CONFIG_ARCH_LPC18XX) += lpc18xx
machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx
machine-$(CONFIG_ARCH_MESON) += meson
machine-$(CONFIG_ARCH_MMP) += mmp
machine-$(CONFIG_ARCH_MPS2) += vexpress
machine-$(CONFIG_ARCH_MOXART) += moxart
machine-$(CONFIG_ARCH_MV78XX0) += mv78xx0
machine-$(CONFIG_ARCH_MVEBU) += mvebu
@ -207,7 +205,6 @@ machine-$(CONFIG_ARCH_PXA) += pxa
machine-$(CONFIG_ARCH_QCOM) += qcom
machine-$(CONFIG_ARCH_RDA) += rda
machine-$(CONFIG_ARCH_REALTEK) += realtek
machine-$(CONFIG_ARCH_REALVIEW) += realview
machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip
machine-$(CONFIG_ARCH_RPC) += rpc
machine-$(CONFIG_PLAT_SAMSUNG) += s3c
@ -220,18 +217,15 @@ machine-$(CONFIG_ARCH_STM32) += stm32
machine-$(CONFIG_ARCH_SUNXI) += sunxi
machine-$(CONFIG_ARCH_TEGRA) += tegra
machine-$(CONFIG_ARCH_U8500) += ux500
machine-$(CONFIG_ARCH_VERSATILE) += versatile
machine-$(CONFIG_ARCH_VEXPRESS) += vexpress
machine-$(CONFIG_ARCH_VT8500) += vt8500
machine-$(CONFIG_ARCH_ZYNQ) += zynq
machine-$(CONFIG_PLAT_VERSATILE) += versatile
machine-$(CONFIG_PLAT_SPEAR) += spear
# Platform directory name. This list is sorted alphanumerically
# by CONFIG_* macro name.
plat-$(CONFIG_ARCH_OMAP) += omap
plat-$(CONFIG_PLAT_ORION) += orion
plat-$(CONFIG_PLAT_PXA) += pxa
plat-$(CONFIG_PLAT_VERSATILE) += versatile
# The byte offset of the kernel image in RAM from the start of RAM.
TEXT_OFFSET := $(textofs-y)

70
arch/arm/mach-ep93xx/include/mach/uncompress.h → arch/arm/boot/compressed/misc-ep93xx.h
View File

@ -1,55 +1,25 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* arch/arm/mach-ep93xx/include/mach/uncompress.h
*
* Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
*/
#include <mach/ep93xx-regs.h>
#include <asm/mach-types.h>
static unsigned char __raw_readb(unsigned int ptr)
{
return *((volatile unsigned char *)ptr);
}
static unsigned int __raw_readl(unsigned int ptr)
static inline unsigned int __raw_readl(unsigned int ptr)
{
return *((volatile unsigned int *)ptr);
}
static void __raw_writeb(unsigned char value, unsigned int ptr)
static inline void __raw_writeb(unsigned char value, unsigned int ptr)
{
*((volatile unsigned char *)ptr) = value;
}
static void __raw_writel(unsigned int value, unsigned int ptr)
static inline void __raw_writel(unsigned int value, unsigned int ptr)
{
*((volatile unsigned int *)ptr) = value;
}
#define PHYS_UART_DATA (CONFIG_DEBUG_UART_PHYS + 0x00)
#define PHYS_UART_FLAG (CONFIG_DEBUG_UART_PHYS + 0x18)
#define UART_FLAG_TXFF 0x20
static inline void putc(int c)
{
int i;
for (i = 0; i < 10000; i++) {
/* Transmit fifo not full? */
if (!(__raw_readb(PHYS_UART_FLAG) & UART_FLAG_TXFF))
break;
}
__raw_writeb(c, PHYS_UART_DATA);
}
static inline void flush(void)
{
}
/*
* Some bootloaders don't turn off DMA from the ethernet MAC before
* jumping to linux, which means that we might end up with bits of RX
@ -59,7 +29,7 @@ static inline void flush(void)
#define PHYS_ETH_SELF_CTL 0x80010020
#define ETH_SELF_CTL_RESET 0x00000001
static void ethernet_reset(void)
static inline void ep93xx_ethernet_reset(void)
{
unsigned int v;
@ -76,15 +46,41 @@ static void ethernet_reset(void)
#define TS72XX_WDT_FEED_PHYS_BASE 0x23c00000
#define TS72XX_WDT_FEED_VAL 0x05
static void __maybe_unused ts72xx_watchdog_disable(void)
static inline void __maybe_unused ts72xx_watchdog_disable(void)
{
__raw_writeb(TS72XX_WDT_FEED_VAL, TS72XX_WDT_FEED_PHYS_BASE);
__raw_writeb(0, TS72XX_WDT_CONTROL_PHYS_BASE);
}
static void arch_decomp_setup(void)
static inline void ep93xx_decomp_setup(void)
{
if (machine_is_ts72xx())
ts72xx_watchdog_disable();
ethernet_reset();
if (machine_is_adssphere() ||
machine_is_edb9301() ||
machine_is_edb9302() ||
machine_is_edb9302a() ||
machine_is_edb9302a() ||
machine_is_edb9307() ||
machine_is_edb9307a() ||
machine_is_edb9307a() ||
machine_is_edb9312() ||
machine_is_edb9315() ||
machine_is_edb9315a() ||
machine_is_edb9315a() ||
machine_is_gesbc9312() ||
machine_is_micro9() ||
machine_is_micro9l() ||
machine_is_micro9m() ||
machine_is_micro9s() ||
machine_is_micro9m() ||
machine_is_micro9l() ||
machine_is_micro9s() ||
machine_is_sim_one() ||
machine_is_snapper_cl15() ||
machine_is_ts72xx() ||
machine_is_bk3() ||
machine_is_vision_ep9307())
ep93xx_ethernet_reset();
}

4
arch/arm/boot/compressed/misc.c
View File

@ -23,6 +23,7 @@ unsigned int __machine_arch_type;
#include <linux/types.h>
#include <linux/linkage.h>
#include "misc.h"
#include "misc-ep93xx.h"
static void putstr(const char *ptr);
@ -143,6 +144,9 @@ decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p,
free_mem_end_ptr = free_mem_ptr_end_p;
__machine_arch_type = arch_id;
#ifdef CONFIG_ARCH_EP93XX
ep93xx_decomp_setup();
#endif
arch_decomp_setup();
putstr("Uncompressing Linux...");

2
arch/arm/configs/dove_defconfig
View File

@ -8,6 +8,8 @@ CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_PARTITION_ADVANCED=y
# CONFIG_ARCH_MULTI_V6 is not set
CONFIG_ARCH_MULTI_V7=y
CONFIG_ARCH_DOVE=y
CONFIG_MACH_DOVE_DB=y
CONFIG_MACH_CM_A510=y

2
arch/arm/configs/ep93xx_defconfig
View File

@ -11,6 +11,8 @@ CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_PARTITION_ADVANCED=y
CONFIG_ARCH_MULTI_V4T=y
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_EP93XX=y
CONFIG_MACH_ADSSPHERE=y
CONFIG_MACH_EDB9301=y

1
arch/arm/configs/iop32x_defconfig
View File

@ -7,6 +7,7 @@ CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_IOP32X=y
CONFIG_MACH_GLANTANK=y
CONFIG_ARCH_IQ80321=y

88
arch/arm/configs/ixp4xx_defconfig
View File

@ -1,36 +1,22 @@
CONFIG_KERNEL_XZ=y
CONFIG_SYSVIPC=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CGROUPS=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_COMPRESSION_XZ=y
CONFIG_EXPERT=y
CONFIG_MODULES=y
CONFIG_MODVERSIONS=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_IXP4XX=y
CONFIG_MACH_NSLU2=y
CONFIG_MACH_AVILA=y
CONFIG_MACH_LOFT=y
CONFIG_ARCH_ADI_COYOTE=y
CONFIG_MACH_GATEWAY7001=y
CONFIG_MACH_WG302V2=y
CONFIG_ARCH_IXDP425=y
CONFIG_MACH_IXDPG425=y
CONFIG_MACH_IXDP465=y
CONFIG_MACH_KIXRP435=y
CONFIG_ARCH_PRPMC1100=y
CONFIG_MACH_NAS100D=y
CONFIG_MACH_DSMG600=y
CONFIG_MACH_FSG=y
CONFIG_MACH_GTWX5715=y
CONFIG_IXP4XX_QMGR=y
CONFIG_IXP4XX_NPE=y
# CONFIG_ARM_THUMB is not set
CONFIG_CPU_BIG_ENDIAN=y
CONFIG_AEABI=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="console=ttyS0,115200 ip=bootp root=/dev/nfs"
CONFIG_FPE_NWFPE=y
CONFIG_CMDLINE="console=ttyS0,115200"
CONFIG_STRICT_KERNEL_RWX=y
CONFIG_STRICT_MODULE_RWX=y
CONFIG_MODULES=y
CONFIG_MODVERSIONS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@ -43,8 +29,6 @@ CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_NET_IPGRE=m
CONFIG_NET_IPGRE_BROADCAST=y
CONFIG_IP_MROUTE=y
CONFIG_IP_PIMSM_V1=y
CONFIG_IP_PIMSM_V2=y
@ -65,7 +49,6 @@ CONFIG_IP_NF_IPTABLES=m
CONFIG_IP_NF_MATCH_TTL=m
CONFIG_IP_NF_FILTER=m
CONFIG_IP_NF_TARGET_REJECT=m
CONFIG_IP_NF_TARGET_LOG=m
CONFIG_IP_NF_MANGLE=m
CONFIG_IP_NF_ARPTABLES=m
CONFIG_IP_NF_ARPFILTER=m
@ -76,14 +59,12 @@ CONFIG_ATM_MPOA=m
CONFIG_ATM_BR2684=m
CONFIG_BRIDGE=m
CONFIG_VLAN_8021Q=m
CONFIG_IPX=m
CONFIG_ATALK=m
CONFIG_DEV_APPLETALK=m
CONFIG_IPDDP=m
CONFIG_IPDDP_ENCAP=y
CONFIG_X25=m
CONFIG_LAPB=m
CONFIG_WAN_ROUTER=m
CONFIG_NET_SCHED=y
CONFIG_NET_SCH_CBQ=m
CONFIG_NET_SCH_HTB=m
@ -104,91 +85,92 @@ CONFIG_NET_CLS_RSVP6=m
CONFIG_NET_CLS_ACT=y
CONFIG_NET_ACT_POLICE=y
CONFIG_NET_PKTGEN=m
CONFIG_DEVTMPFS=y
CONFIG_MTD=y
CONFIG_MTD_REDBOOT_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_IXP4XX=y
CONFIG_MTD_PHYSMAP_IXP4XX=y
CONFIG_MTD_RAW_NAND=m
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_EEPROM_AT24=y
CONFIG_EEPROM_LEGACY=y
# CONFIG_SCSI_PROC_FS is not set
CONFIG_BLK_DEV_SD=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_SCSI_LOWLEVEL is not set
CONFIG_ATA=y
CONFIG_SATA_VIA=y
CONFIG_PATA_ARTOP=y
CONFIG_PATA_CMD64X=y
CONFIG_PATA_HPT366=y
CONFIG_PATA_HPT37X=y
CONFIG_PATA_HPT3X2N=y
CONFIG_PATA_PDC2027X=y
CONFIG_PATA_IXP4XX_CF=y
CONFIG_NETDEVICES=y
CONFIG_DUMMY=y
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
CONFIG_ATM_TCP=m
CONFIG_IXP4XX_ETH=y
CONFIG_NET_PCI=y
CONFIG_WAN=y
CONFIG_HDLC=m
CONFIG_HDLC=y
CONFIG_HDLC_RAW=m
CONFIG_HDLC_CISCO=m
CONFIG_HDLC_FR=m
CONFIG_HDLC_PPP=m
CONFIG_HDLC_X25=m
CONFIG_WAN_ROUTER_DRIVERS=m
CONFIG_ATM_TCP=m
# CONFIG_INPUT_KEYBOARD is not set
CONFIG_IXP4XX_HSS=m
# CONFIG_KEYBOARD_ATKBD is not set
CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_MISC=y
CONFIG_INPUT_IXP4XX_BEEPER=y
# CONFIG_SERIO is not set
# CONFIG_VT is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=2
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_I2C=y
CONFIG_HW_RANDOM=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_GPIO=y
CONFIG_GPIO_GW_PLD=y
CONFIG_GPIO_PCA953X=y
CONFIG_SENSORS_AD7418=y
CONFIG_SENSORS_W83781D=y
CONFIG_WATCHDOG=y
CONFIG_IXP4XX_WATCHDOG=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_UHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_FSG=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_DISK=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_DS1672=y
CONFIG_RTC_DRV_ISL1208=y
CONFIG_RTC_DRV_X1205=y
CONFIG_RTC_DRV_PCF8563=y
CONFIG_IXP4XX_QMGR=y
CONFIG_IXP4XX_NPE=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
CONFIG_EXT3_FS=y
CONFIG_EXT3_FS_POSIX_ACL=y
CONFIG_OVERLAY_FS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_JFFS2_FS=y
CONFIG_SQUASHFS=y
CONFIG_SQUASHFS_XZ=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_ROOT_NFS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_CRYPTO_DEV_IXP4XX=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_LL=y
CONFIG_DEBUG_LL_UART_8250=y

2
arch/arm/configs/mini2440_defconfig
View File

@ -4,6 +4,8 @@ CONFIG_POSIX_MQUEUE=y
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
# CONFIG_COMPAT_BRK is not set
CONFIG_ARCH_MULTI_V4T=y
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_S3C24XX=y
CONFIG_S3C_ADC=y
# CONFIG_CPU_S3C2410 is not set

3
arch/arm/configs/s3c2410_defconfig
View File

@ -4,6 +4,9 @@ CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=16
CONFIG_BLK_DEV_INITRD=y
CONFIG_SLAB=y
CONFIG_ARCH_MULTI_V4T=y
CONFIG_ARCH_MULTI_V5=y
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_S3C24XX=y
CONFIG_S3C_ADC=y
CONFIG_CPU_S3C2412=y

2
arch/arm/configs/tct_hammer_defconfig
View File

@ -13,6 +13,8 @@ CONFIG_SLOB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_MULTI_V4T=y
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_S3C24XX=y
CONFIG_MACH_TCT_HAMMER=y
CONFIG_ZBOOT_ROM_TEXT=0x0

1
arch/arm/mach-asm9260/Kconfig
View File

@ -2,6 +2,7 @@
config MACH_ASM9260
bool "Alphascale ASM9260"
depends on ARCH_MULTI_V5
depends on CPU_LITTLE_ENDIAN
select CPU_ARM926T
select ASM9260_TIMER
help

2
arch/arm/mach-aspeed/Kconfig
View File

@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
menuconfig ARCH_ASPEED
bool "Aspeed BMC architectures"
depends on ARCH_MULTI_V5 || ARCH_MULTI_V6 || ARCH_MULTI_V7
depends on (CPU_LITTLE_ENDIAN && ARCH_MULTI_V5) || ARCH_MULTI_V6 || ARCH_MULTI_V7
select SRAM
select WATCHDOG
select ASPEED_WATCHDOG

3
arch/arm/mach-at91/Kconfig
View File

@ -1,7 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-only
menuconfig ARCH_AT91
bool "AT91/Microchip SoCs"
depends on ARCH_MULTI_V4T || ARCH_MULTI_V5 || ARCH_MULTI_V7 || ARM_SINGLE_ARMV7M
depends on (CPU_LITTLE_ENDIAN && (ARCH_MULTI_V4T || ARCH_MULTI_V5)) || \
ARCH_MULTI_V7 || ARM_SINGLE_ARMV7M
select ARM_CPU_SUSPEND if PM && ARCH_MULTI_V7
select COMMON_CLK_AT91
select GPIOLIB

1
arch/arm/mach-clps711x/Kconfig
View File

@ -2,6 +2,7 @@
menuconfig ARCH_CLPS711X
bool "Cirrus Logic EP721x/EP731x-based"
depends on ARCH_MULTI_V4T
depends on CPU_LITTLE_ENDIAN
select CLPS711X_TIMER
select CPU_ARM720T
select GPIOLIB

1
arch/arm/mach-davinci/Kconfig
View File

@ -3,6 +3,7 @@
menuconfig ARCH_DAVINCI
bool "TI DaVinci"
depends on ARCH_MULTI_V5
depends on CPU_LITTLE_ENDIAN
select DAVINCI_TIMER
select ZONE_DMA
select PM_GENERIC_DOMAINS if PM

4
arch/arm/mach-davinci/Makefile
View File

@ -3,9 +3,7 @@
# Makefile for the linux kernel.
#
#
ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
#
# Common objects
obj-y := serial.o usb.o common.o sram.o

7
arch/arm/mach-davinci/board-da830-evm.c
View File

@ -36,10 +36,9 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/common.h>
#include <mach/mux.h>
#include <mach/da8xx.h>
#include "common.h"
#include "mux.h"
#include "da8xx.h"
#include "irqs.h"
#define DA830_EVM_PHY_ID ""

7
arch/arm/mach-davinci/board-da850-evm.c
View File

@ -43,10 +43,9 @@
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#include <mach/common.h>
#include <mach/da8xx.h>
#include <mach/mux.h>
#include "common.h"
#include "da8xx.h"
#include "mux.h"
#include "irqs.h"
#include "sram.h"

5
arch/arm/mach-davinci/board-dm355-evm.c
View File

@ -33,9 +33,8 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/serial.h>
#include <mach/common.h>
#include "serial.h"
#include "common.h"
#include "davinci.h"
/* NOTE: this is geared for the standard config, with a socketed

5
arch/arm/mach-davinci/board-dm355-leopard.c
View File

@ -27,9 +27,8 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/common.h>
#include <mach/serial.h>
#include "common.h"
#include "serial.h"
#include "davinci.h"
/* NOTE: this is geared for the standard config, with a socketed

6
arch/arm/mach-davinci/board-dm365-evm.c
View File

@ -36,10 +36,7 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/mux.h>
#include <mach/common.h>
#include <linux/platform_data/i2c-davinci.h>
#include <mach/serial.h>
#include <linux/platform_data/mmc-davinci.h>
#include <linux/platform_data/mtd-davinci.h>
#include <linux/platform_data/keyscan-davinci.h>
@ -47,6 +44,9 @@
#include <media/i2c/ths7303.h>
#include <media/i2c/tvp514x.h>
#include "mux.h"
#include "common.h"
#include "serial.h"
#include "davinci.h"
static inline int have_imager(void)

7
arch/arm/mach-davinci/board-dm644x-evm.c
View File

@ -37,10 +37,6 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/common.h>
#include <mach/mux.h>
#include <mach/serial.h>
#include <linux/platform_data/i2c-davinci.h>
#include <linux/platform_data/mtd-davinci.h>
#include <linux/platform_data/mmc-davinci.h>
@ -49,6 +45,9 @@
#include <linux/platform_data/ti-aemif.h>
#include "davinci.h"
#include "common.h"
#include "mux.h"
#include "serial.h"
#include "irqs.h"
#define DM644X_EVM_PHY_ID "davinci_mdio-0:01"

5
arch/arm/mach-davinci/board-dm646x-evm.c
View File

@ -43,9 +43,8 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/common.h>
#include <mach/serial.h>
#include "common.h"
#include "serial.h"
#include "davinci.h"
#include "irqs.h"

8
arch/arm/mach-davinci/board-mityomapl138.c
View File

@ -28,12 +28,14 @@
#include <asm/io.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/common.h>
#include <mach/da8xx.h>
#include "common.h"
#include "da8xx.h"
#include "mux.h"
#include <linux/platform_data/mtd-davinci.h>
#include <linux/platform_data/mtd-davinci-aemif.h>
#include <linux/platform_data/ti-aemif.h>
#include <mach/mux.h>
#include <linux/platform_data/spi-davinci.h>
#define MITYOMAPL138_PHY_ID ""

7
arch/arm/mach-davinci/board-neuros-osd2.c
View File

@ -36,10 +36,9 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/common.h>
#include <mach/serial.h>
#include <mach/mux.h>
#include "common.h"
#include "serial.h"
#include "mux.h"
#include "davinci.h"
#define NEUROS_OSD2_PHY_ID "davinci_mdio-0:01"

6
arch/arm/mach-davinci/board-omapl138-hawk.c
View File

@ -27,9 +27,9 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/common.h>
#include <mach/da8xx.h>
#include <mach/mux.h>
#include "common.h"
#include "da8xx.h"
#include "mux.h"
#define HAWKBOARD_PHY_ID "davinci_mdio-0:07"

6
arch/arm/mach-davinci/board-sffsdr.c
View File

@ -22,12 +22,12 @@
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <mach/common.h>
#include <linux/platform_data/i2c-davinci.h>
#include <mach/serial.h>
#include <mach/mux.h>
#include <linux/platform_data/usb-davinci.h>
#include "common.h"
#include "serial.h"
#include "mux.h"
#include "davinci.h"
#define SFFSDR_PHY_ID "davinci_mdio-0:01"

4
arch/arm/mach-davinci/common.c
View File

@ -17,8 +17,8 @@
#include <asm/tlb.h>
#include <asm/mach/map.h>
#include <mach/common.h>
#include <mach/cputype.h>
#include "common.h"
#include "cputype.h"
struct davinci_soc_info davinci_soc_info;
EXPORT_SYMBOL(davinci_soc_info);

0
arch/arm/mach-davinci/include/mach/common.h → arch/arm/mach-davinci/common.h
View File

2
arch/arm/mach-davinci/include/mach/cputype.h → arch/arm/mach-davinci/cputype.h
View File

@ -16,7 +16,7 @@
#ifndef _ASM_ARCH_CPU_H
#define _ASM_ARCH_CPU_H
#include <mach/common.h>
#include "common.h"
struct davinci_id {
u8 variant; /* JTAG ID bits 31:28 */

11
arch/arm/mach-davinci/da830.c
View File

@ -16,14 +16,13 @@
#include <linux/irqchip/irq-davinci-cp-intc.h>
#include <linux/platform_data/gpio-davinci.h>
#include <asm/mach/map.h>
#include <mach/common.h>
#include <mach/cputype.h>
#include <mach/da8xx.h>
#include <clocksource/timer-davinci.h>
#include <asm/mach/map.h>
#include "common.h"
#include "cputype.h"
#include "da8xx.h"
#include "irqs.h"
#include "mux.h"

12
arch/arm/mach-davinci/da850.c
View File

@ -28,16 +28,14 @@
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <clocksource/timer-davinci.h>
#include <asm/mach/map.h>
#include <mach/common.h>
#include <mach/cputype.h>
#include <mach/da8xx.h>
#include <mach/pm.h>
#include <clocksource/timer-davinci.h>
#include "common.h"
#include "cputype.h"
#include "da8xx.h"
#include "pm.h"
#include "irqs.h"
#include "mux.h"

4
arch/arm/mach-davinci/da8xx-dt.c
View File

@ -7,8 +7,8 @@
#include <asm/mach/arch.h>
#include <mach/common.h>
#include <mach/da8xx.h>
#include "common.h"
#include "da8xx.h"
#ifdef CONFIG_ARCH_DAVINCI_DA850

5
arch/arm/mach-davinci/include/mach/da8xx.h → arch/arm/mach-davinci/da8xx.h
View File

@ -21,8 +21,9 @@
#include <linux/regmap.h>
#include <linux/videodev2.h>
#include <mach/serial.h>
#include <mach/pm.h>
#include "serial.h"
#include "pm.h"
#include <linux/platform_data/edma.h>
#include <linux/platform_data/i2c-davinci.h>
#include <linux/platform_data/mmc-davinci.h>

3
arch/arm/mach-davinci/davinci.h
View File

@ -25,7 +25,8 @@
#include <linux/platform_data/davinci_asp.h>
#include <linux/platform_data/edma.h>
#include <linux/platform_data/keyscan-davinci.h>
#include <mach/hardware.h>
#include "hardware.h"
#include <media/davinci/vpfe_capture.h>
#include <media/davinci/vpif_types.h>

7
arch/arm/mach-davinci/devices-da8xx.c
View File

@ -18,10 +18,9 @@
#include <linux/reboot.h>
#include <linux/serial_8250.h>
#include <mach/common.h>
#include <mach/cputype.h>
#include <mach/da8xx.h>
#include "common.h"
#include "cputype.h"
#include "da8xx.h"
#include "asp.h"
#include "cpuidle.h"
#include "irqs.h"

7
arch/arm/mach-davinci/devices.c
View File

@ -14,10 +14,9 @@
#include <linux/io.h>
#include <linux/reboot.h>
#include <mach/hardware.h>
#include <mach/cputype.h>
#include <mach/mux.h>
#include "hardware.h"
#include "cputype.h"
#include "mux.h"
#include "davinci.h"
#include "irqs.h"

12
arch/arm/mach-davinci/dm355.c
View File

@ -24,15 +24,13 @@
#include <linux/serial_8250.h>
#include <linux/spi/spi.h>
#include <asm/mach/map.h>
#include <mach/common.h>
#include <mach/cputype.h>
#include <mach/mux.h>
#include <mach/serial.h>
#include <clocksource/timer-davinci.h>
#include <asm/mach/map.h>
#include "common.h"
#include "cputype.h"
#include "serial.h"
#include "asp.h"
#include "davinci.h"
#include "irqs.h"

12
arch/arm/mach-davinci/dm365.c
View File

@ -29,15 +29,13 @@
#include <linux/serial_8250.h>
#include <linux/spi/spi.h>
#include <asm/mach/map.h>
#include <mach/common.h>
#include <mach/cputype.h>
#include <mach/mux.h>
#include <mach/serial.h>
#include <clocksource/timer-davinci.h>
#include <asm/mach/map.h>
#include "common.h"
#include "cputype.h"
#include "serial.h"
#include "asp.h"
#include "davinci.h"
#include "irqs.h"

12
arch/arm/mach-davinci/dm644x.c
View File

@ -21,15 +21,13 @@
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <asm/mach/map.h>
#include <mach/common.h>
#include <mach/cputype.h>
#include <mach/mux.h>
#include <mach/serial.h>
#include <clocksource/timer-davinci.h>
#include <asm/mach/map.h>
#include "common.h"
#include "cputype.h"
#include "serial.h"
#include "asp.h"
#include "davinci.h"
#include "irqs.h"

12
arch/arm/mach-davinci/dm646x.c
View File

@ -22,15 +22,13 @@
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <asm/mach/map.h>
#include <mach/common.h>
#include <mach/cputype.h>
#include <mach/mux.h>
#include <mach/serial.h>
#include <clocksource/timer-davinci.h>
#include <asm/mach/map.h>
#include "common.h"
#include "cputype.h"
#include "serial.h"
#include "asp.h"
#include "davinci.h"
#include "irqs.h"

0
arch/arm/mach-davinci/include/mach/hardware.h → arch/arm/mach-davinci/hardware.h
View File

990
arch/arm/mach-davinci/include/mach/mux.h
View File

@ -1,990 +0,0 @@
/*
* Table of the DAVINCI register configurations for the PINMUX combinations
*
* Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
*
* Based on linux/include/asm-arm/arch-omap/mux.h:
* Copyright (C) 2003 - 2005 Nokia Corporation
*
* Written by Tony Lindgren
*
* 2007 (c) MontaVista Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*
* Copyright (C) 2008 Texas Instruments.
*/
#ifndef __INC_MACH_MUX_H
#define __INC_MACH_MUX_H
struct mux_config {
const char *name;
const char *mux_reg_name;
const unsigned char mux_reg;
const unsigned char mask_offset;
const unsigned char mask;
const unsigned char mode;
bool debug;
};
enum davinci_dm644x_index {
/* ATA and HDDIR functions */
DM644X_HDIREN,
DM644X_ATAEN,
DM644X_ATAEN_DISABLE,
/* HPI functions */
DM644X_HPIEN_DISABLE,
/* AEAW functions */
DM644X_AEAW,
DM644X_AEAW0,
DM644X_AEAW1,
DM644X_AEAW2,
DM644X_AEAW3,
DM644X_AEAW4,
/* Memory Stick */
DM644X_MSTK,
/* I2C */
DM644X_I2C,
/* ASP function */
DM644X_MCBSP,
/* UART1 */
DM644X_UART1,
/* UART2 */
DM644X_UART2,
/* PWM0 */
DM644X_PWM0,
/* PWM1 */
DM644X_PWM1,
/* PWM2 */
DM644X_PWM2,
/* VLYNQ function */
DM644X_VLYNQEN,
DM644X_VLSCREN,
DM644X_VLYNQWD,
/* EMAC and MDIO function */
DM644X_EMACEN,
/* GPIO3V[0:16] pins */
DM644X_GPIO3V,
/* GPIO pins */
DM644X_GPIO0,
DM644X_GPIO3,
DM644X_GPIO43_44,
DM644X_GPIO46_47,
/* VPBE */
DM644X_RGB666,
/* LCD */
DM644X_LOEEN,
DM644X_LFLDEN,
};
enum davinci_dm646x_index {
/* ATA function */
DM646X_ATAEN,
/* AUDIO Clock */
DM646X_AUDCK1,
DM646X_AUDCK0,
/* CRGEN Control */
DM646X_CRGMUX,
/* VPIF Control */
DM646X_STSOMUX_DISABLE,
DM646X_STSIMUX_DISABLE,
DM646X_PTSOMUX_DISABLE,
DM646X_PTSIMUX_DISABLE,
/* TSIF Control */
DM646X_STSOMUX,
DM646X_STSIMUX,
DM646X_PTSOMUX_PARALLEL,
DM646X_PTSIMUX_PARALLEL,
DM646X_PTSOMUX_SERIAL,
DM646X_PTSIMUX_SERIAL,
};
enum davinci_dm355_index {
/* MMC/SD 0 */
DM355_MMCSD0,
/* MMC/SD 1 */
DM355_SD1_CLK,
DM355_SD1_CMD,
DM355_SD1_DATA3,
DM355_SD1_DATA2,
DM355_SD1_DATA1,
DM355_SD1_DATA0,
/* I2C */
DM355_I2C_SDA,
DM355_I2C_SCL,
/* ASP0 function */
DM355_MCBSP0_BDX,
DM355_MCBSP0_X,
DM355_MCBSP0_BFSX,
DM355_MCBSP0_BDR,
DM355_MCBSP0_R,
DM355_MCBSP0_BFSR,
/* SPI0 */
DM355_SPI0_SDI,
DM355_SPI0_SDENA0,
DM355_SPI0_SDENA1,
/* IRQ muxing */
DM355_INT_EDMA_CC,
DM355_INT_EDMA_TC0_ERR,
DM355_INT_EDMA_TC1_ERR,
/* EDMA event muxing */
DM355_EVT8_ASP1_TX,
DM355_EVT9_ASP1_RX,
DM355_EVT26_MMC0_RX,
/* Video Out */
DM355_VOUT_FIELD,
DM355_VOUT_FIELD_G70,
DM355_VOUT_HVSYNC,
DM355_VOUT_COUTL_EN,
DM355_VOUT_COUTH_EN,
/* Video In Pin Mux */
DM355_VIN_PCLK,
DM355_VIN_CAM_WEN,
DM355_VIN_CAM_VD,
DM355_VIN_CAM_HD,
DM355_VIN_YIN_EN,
DM355_VIN_CINL_EN,
DM355_VIN_CINH_EN,
};
enum davinci_dm365_index {
/* MMC/SD 0 */
DM365_MMCSD0,
/* MMC/SD 1 */
DM365_SD1_CLK,
DM365_SD1_CMD,
DM365_SD1_DATA3,
DM365_SD1_DATA2,
DM365_SD1_DATA1,
DM365_SD1_DATA0,
/* I2C */
DM365_I2C_SDA,
DM365_I2C_SCL,
/* AEMIF */
DM365_AEMIF_AR_A14,
DM365_AEMIF_AR_BA0,
DM365_AEMIF_A3,
DM365_AEMIF_A7,
DM365_AEMIF_D15_8,
DM365_AEMIF_CE0,
DM365_AEMIF_CE1,
DM365_AEMIF_WE_OE,
/* ASP0 function */
DM365_MCBSP0_BDX,
DM365_MCBSP0_X,
DM365_MCBSP0_BFSX,
DM365_MCBSP0_BDR,
DM365_MCBSP0_R,
DM365_MCBSP0_BFSR,
/* SPI0 */
DM365_SPI0_SCLK,
DM365_SPI0_SDI,
DM365_SPI0_SDO,
DM365_SPI0_SDENA0,
DM365_SPI0_SDENA1,
/* UART */
DM365_UART0_RXD,
DM365_UART0_TXD,
DM365_UART1_RXD,
DM365_UART1_TXD,
DM365_UART1_RTS,
DM365_UART1_CTS,
/* EMAC */
DM365_EMAC_TX_EN,
DM365_EMAC_TX_CLK,
DM365_EMAC_COL,
DM365_EMAC_TXD3,
DM365_EMAC_TXD2,
DM365_EMAC_TXD1,
DM365_EMAC_TXD0,
DM365_EMAC_RXD3,
DM365_EMAC_RXD2,
DM365_EMAC_RXD1,
DM365_EMAC_RXD0,
DM365_EMAC_RX_CLK,
DM365_EMAC_RX_DV,
DM365_EMAC_RX_ER,
DM365_EMAC_CRS,
DM365_EMAC_MDIO,
DM365_EMAC_MDCLK,
/* Key Scan */
DM365_KEYSCAN,
/* PWM */
DM365_PWM0,
DM365_PWM0_G23,
DM365_PWM1,
DM365_PWM1_G25,
DM365_PWM2_G87,
DM365_PWM2_G88,
DM365_PWM2_G89,
DM365_PWM2_G90,
DM365_PWM3_G80,
DM365_PWM3_G81,
DM365_PWM3_G85,
DM365_PWM3_G86,
/* SPI1 */
DM365_SPI1_SCLK,
DM365_SPI1_SDO,
DM365_SPI1_SDI,
DM365_SPI1_SDENA0,
DM365_SPI1_SDENA1,
/* SPI2 */
DM365_SPI2_SCLK,
DM365_SPI2_SDO,
DM365_SPI2_SDI,
DM365_SPI2_SDENA0,
DM365_SPI2_SDENA1,
/* SPI3 */
DM365_SPI3_SCLK,
DM365_SPI3_SDO,
DM365_SPI3_SDI,
DM365_SPI3_SDENA0,
DM365_SPI3_SDENA1,
/* SPI4 */
DM365_SPI4_SCLK,
DM365_SPI4_SDO,
DM365_SPI4_SDI,
DM365_SPI4_SDENA0,
DM365_SPI4_SDENA1,
/* Clock */
DM365_CLKOUT0,
DM365_CLKOUT1,
DM365_CLKOUT2,
/* GPIO */
DM365_GPIO20,
DM365_GPIO30,
DM365_GPIO31,
DM365_GPIO32,
DM365_GPIO33,
DM365_GPIO40,
DM365_GPIO64_57,
/* Video */
DM365_VOUT_FIELD,
DM365_VOUT_FIELD_G81,
DM365_VOUT_HVSYNC,
DM365_VOUT_COUTL_EN,
DM365_VOUT_COUTH_EN,
DM365_VIN_CAM_WEN,
DM365_VIN_CAM_VD,
DM365_VIN_CAM_HD,
DM365_VIN_YIN4_7_EN,
DM365_VIN_YIN0_3_EN,
/* IRQ muxing */
DM365_INT_EDMA_CC,
DM365_INT_EDMA_TC0_ERR,
DM365_INT_EDMA_TC1_ERR,
DM365_INT_EDMA_TC2_ERR,
DM365_INT_EDMA_TC3_ERR,
DM365_INT_PRTCSS,
DM365_INT_EMAC_RXTHRESH,
DM365_INT_EMAC_RXPULSE,
DM365_INT_EMAC_TXPULSE,
DM365_INT_EMAC_MISCPULSE,
DM365_INT_IMX0_ENABLE,
DM365_INT_IMX0_DISABLE,
DM365_INT_HDVICP_ENABLE,
DM365_INT_HDVICP_DISABLE,
DM365_INT_IMX1_ENABLE,
DM365_INT_IMX1_DISABLE,
DM365_INT_NSF_ENABLE,
DM365_INT_NSF_DISABLE,
/* EDMA event muxing */
DM365_EVT2_ASP_TX,
DM365_EVT3_ASP_RX,
DM365_EVT2_VC_TX,
DM365_EVT3_VC_RX,
DM365_EVT26_MMC0_RX,
};
enum da830_index {
DA830_GPIO7_14,
DA830_RTCK,
DA830_GPIO7_15,
DA830_EMU_0,
DA830_EMB_SDCKE,
DA830_EMB_CLK_GLUE,
DA830_EMB_CLK,
DA830_NEMB_CS_0,
DA830_NEMB_CAS,
DA830_NEMB_RAS,
DA830_NEMB_WE,
DA830_EMB_BA_1,
DA830_EMB_BA_0,
DA830_EMB_A_0,
DA830_EMB_A_1,
DA830_EMB_A_2,
DA830_EMB_A_3,
DA830_EMB_A_4,
DA830_EMB_A_5,
DA830_GPIO7_0,
DA830_GPIO7_1,
DA830_GPIO7_2,
DA830_GPIO7_3,
DA830_GPIO7_4,
DA830_GPIO7_5,
DA830_GPIO7_6,
DA830_GPIO7_7,
DA830_EMB_A_6,
DA830_EMB_A_7,
DA830_EMB_A_8,
DA830_EMB_A_9,
DA830_EMB_A_10,
DA830_EMB_A_11,
DA830_EMB_A_12,
DA830_EMB_D_31,
DA830_GPIO7_8,
DA830_GPIO7_9,
DA830_GPIO7_10,
DA830_GPIO7_11,
DA830_GPIO7_12,
DA830_GPIO7_13,
DA830_GPIO3_13,
DA830_EMB_D_30,
DA830_EMB_D_29,
DA830_EMB_D_28,
DA830_EMB_D_27,
DA830_EMB_D_26,
DA830_EMB_D_25,
DA830_EMB_D_24,
DA830_EMB_D_23,
DA830_EMB_D_22,
DA830_EMB_D_21,
DA830_EMB_D_20,
DA830_EMB_D_19,
DA830_EMB_D_18,
DA830_EMB_D_17,
DA830_EMB_D_16,
DA830_NEMB_WE_DQM_3,
DA830_NEMB_WE_DQM_2,
DA830_EMB_D_0,
DA830_EMB_D_1,
DA830_EMB_D_2,
DA830_EMB_D_3,
DA830_EMB_D_4,
DA830_EMB_D_5,
DA830_EMB_D_6,
DA830_GPIO6_0,
DA830_GPIO6_1,
DA830_GPIO6_2,
DA830_GPIO6_3,
DA830_GPIO6_4,
DA830_GPIO6_5,
DA830_GPIO6_6,
DA830_EMB_D_7,
DA830_EMB_D_8,
DA830_EMB_D_9,
DA830_EMB_D_10,
DA830_EMB_D_11,
DA830_EMB_D_12,
DA830_EMB_D_13,
DA830_EMB_D_14,
DA830_GPIO6_7,
DA830_GPIO6_8,
DA830_GPIO6_9,
DA830_GPIO6_10,
DA830_GPIO6_11,
DA830_GPIO6_12,
DA830_GPIO6_13,
DA830_GPIO6_14,
DA830_EMB_D_15,
DA830_NEMB_WE_DQM_1,
DA830_NEMB_WE_DQM_0,
DA830_SPI0_SOMI_0,
DA830_SPI0_SIMO_0,
DA830_SPI0_CLK,
DA830_NSPI0_ENA,
DA830_NSPI0_SCS_0,
DA830_EQEP0I,
DA830_EQEP0S,
DA830_EQEP1I,
DA830_NUART0_CTS,
DA830_NUART0_RTS,
DA830_EQEP0A,
DA830_EQEP0B,
DA830_GPIO6_15,
DA830_GPIO5_14,
DA830_GPIO5_15,
DA830_GPIO5_0,
DA830_GPIO5_1,
DA830_GPIO5_2,
DA830_GPIO5_3,
DA830_GPIO5_4,
DA830_SPI1_SOMI_0,
DA830_SPI1_SIMO_0,
DA830_SPI1_CLK,
DA830_UART0_RXD,
DA830_UART0_TXD,
DA830_AXR1_10,
DA830_AXR1_11,
DA830_NSPI1_ENA,
DA830_I2C1_SCL,
DA830_I2C1_SDA,
DA830_EQEP1S,
DA830_I2C0_SDA,
DA830_I2C0_SCL,
DA830_UART2_RXD,
DA830_TM64P0_IN12,
DA830_TM64P0_OUT12,
DA830_GPIO5_5,
DA830_GPIO5_6,
DA830_GPIO5_7,
DA830_GPIO5_8,
DA830_GPIO5_9,
DA830_GPIO5_10,
DA830_GPIO5_11,
DA830_GPIO5_12,
DA830_NSPI1_SCS_0,
DA830_USB0_DRVVBUS,
DA830_AHCLKX0,
DA830_ACLKX0,
DA830_AFSX0,
DA830_AHCLKR0,
DA830_ACLKR0,
DA830_AFSR0,
DA830_UART2_TXD,
DA830_AHCLKX2,
DA830_ECAP0_APWM0,
DA830_RMII_MHZ_50_CLK,
DA830_ECAP1_APWM1,
DA830_USB_REFCLKIN,
DA830_GPIO5_13,
DA830_GPIO4_15,
DA830_GPIO2_11,
DA830_GPIO2_12,
DA830_GPIO2_13,
DA830_GPIO2_14,
DA830_GPIO2_15,
DA830_GPIO3_12,
DA830_AMUTE0,
DA830_AXR0_0,
DA830_AXR0_1,
DA830_AXR0_2,
DA830_AXR0_3,
DA830_AXR0_4,
DA830_AXR0_5,
DA830_AXR0_6,
DA830_RMII_TXD_0,
DA830_RMII_TXD_1,
DA830_RMII_TXEN,
DA830_RMII_CRS_DV,
DA830_RMII_RXD_0,
DA830_RMII_RXD_1,
DA830_RMII_RXER,
DA830_AFSR2,
DA830_ACLKX2,
DA830_AXR2_3,
DA830_AXR2_2,
DA830_AXR2_1,
DA830_AFSX2,
DA830_ACLKR2,
DA830_NRESETOUT,
DA830_GPIO3_0,
DA830_GPIO3_1,
DA830_GPIO3_2,
DA830_GPIO3_3,
DA830_GPIO3_4,
DA830_GPIO3_5,
DA830_GPIO3_6,
DA830_AXR0_7,
DA830_AXR0_8,
DA830_UART1_RXD,
DA830_UART1_TXD,
DA830_AXR0_11,
DA830_AHCLKX1,
DA830_ACLKX1,
DA830_AFSX1,
DA830_MDIO_CLK,
DA830_MDIO_D,
DA830_AXR0_9,
DA830_AXR0_10,
DA830_EPWM0B,
DA830_EPWM0A,
DA830_EPWMSYNCI,
DA830_AXR2_0,
DA830_EPWMSYNC0,
DA830_GPIO3_7,
DA830_GPIO3_8,
DA830_GPIO3_9,
DA830_GPIO3_10,
DA830_GPIO3_11,
DA830_GPIO3_14,
DA830_GPIO3_15,
DA830_GPIO4_10,
DA830_AHCLKR1,
DA830_ACLKR1,
DA830_AFSR1,
DA830_AMUTE1,
DA830_AXR1_0,
DA830_AXR1_1,
DA830_AXR1_2,
DA830_AXR1_3,
DA830_ECAP2_APWM2,
DA830_EHRPWMGLUETZ,
DA830_EQEP1A,
DA830_GPIO4_11,
DA830_GPIO4_12,
DA830_GPIO4_13,
DA830_GPIO4_14,
DA830_GPIO4_0,
DA830_GPIO4_1,
DA830_GPIO4_2,
DA830_GPIO4_3,
DA830_AXR1_4,
DA830_AXR1_5,
DA830_AXR1_6,
DA830_AXR1_7,
DA830_AXR1_8,
DA830_AXR1_9,
DA830_EMA_D_0,
DA830_EMA_D_1,
DA830_EQEP1B,
DA830_EPWM2B,
DA830_EPWM2A,
DA830_EPWM1B,
DA830_EPWM1A,
DA830_MMCSD_DAT_0,
DA830_MMCSD_DAT_1,
DA830_UHPI_HD_0,
DA830_UHPI_HD_1,
DA830_GPIO4_4,
DA830_GPIO4_5,
DA830_GPIO4_6,
DA830_GPIO4_7,
DA830_GPIO4_8,
DA830_GPIO4_9,
DA830_GPIO0_0,
DA830_GPIO0_1,
DA830_EMA_D_2,
DA830_EMA_D_3,
DA830_EMA_D_4,
DA830_EMA_D_5,
DA830_EMA_D_6,
DA830_EMA_D_7,
DA830_EMA_D_8,
DA830_EMA_D_9,
DA830_MMCSD_DAT_2,
DA830_MMCSD_DAT_3,
DA830_MMCSD_DAT_4,
DA830_MMCSD_DAT_5,
DA830_MMCSD_DAT_6,
DA830_MMCSD_DAT_7,
DA830_UHPI_HD_8,
DA830_UHPI_HD_9,
DA830_UHPI_HD_2,
DA830_UHPI_HD_3,
DA830_UHPI_HD_4,
DA830_UHPI_HD_5,
DA830_UHPI_HD_6,
DA830_UHPI_HD_7,
DA830_LCD_D_8,
DA830_LCD_D_9,
DA830_GPIO0_2,
DA830_GPIO0_3,
DA830_GPIO0_4,
DA830_GPIO0_5,
DA830_GPIO0_6,
DA830_GPIO0_7,
DA830_GPIO0_8,
DA830_GPIO0_9,
DA830_EMA_D_10,
DA830_EMA_D_11,
DA830_EMA_D_12,
DA830_EMA_D_13,
DA830_EMA_D_14,
DA830_EMA_D_15,
DA830_EMA_A_0,
DA830_EMA_A_1,
DA830_UHPI_HD_10,
DA830_UHPI_HD_11,
DA830_UHPI_HD_12,
DA830_UHPI_HD_13,
DA830_UHPI_HD_14,
DA830_UHPI_HD_15,
DA830_LCD_D_7,
DA830_MMCSD_CLK,
DA830_LCD_D_10,
DA830_LCD_D_11,
DA830_LCD_D_12,
DA830_LCD_D_13,
DA830_LCD_D_14,
DA830_LCD_D_15,
DA830_UHPI_HCNTL0,
DA830_GPIO0_10,
DA830_GPIO0_11,
DA830_GPIO0_12,
DA830_GPIO0_13,
DA830_GPIO0_14,
DA830_GPIO0_15,
DA830_GPIO1_0,
DA830_GPIO1_1,
DA830_EMA_A_2,
DA830_EMA_A_3,
DA830_EMA_A_4,
DA830_EMA_A_5,
DA830_EMA_A_6,
DA830_EMA_A_7,
DA830_EMA_A_8,
DA830_EMA_A_9,
DA830_MMCSD_CMD,
DA830_LCD_D_6,
DA830_LCD_D_3,
DA830_LCD_D_2,
DA830_LCD_D_1,
DA830_LCD_D_0,
DA830_LCD_PCLK,
DA830_LCD_HSYNC,
DA830_UHPI_HCNTL1,
DA830_GPIO1_2,
DA830_GPIO1_3,
DA830_GPIO1_4,
DA830_GPIO1_5,
DA830_GPIO1_6,
DA830_GPIO1_7,
DA830_GPIO1_8,
DA830_GPIO1_9,
DA830_EMA_A_10,
DA830_EMA_A_11,
DA830_EMA_A_12,
DA830_EMA_BA_1,
DA830_EMA_BA_0,
DA830_EMA_CLK,
DA830_EMA_SDCKE,
DA830_NEMA_CAS,
DA830_LCD_VSYNC,
DA830_NLCD_AC_ENB_CS,
DA830_LCD_MCLK,
DA830_LCD_D_5,
DA830_LCD_D_4,
DA830_OBSCLK,
DA830_NEMA_CS_4,
DA830_UHPI_HHWIL,
DA830_AHCLKR2,
DA830_GPIO1_10,
DA830_GPIO1_11,
DA830_GPIO1_12,
DA830_GPIO1_13,
DA830_GPIO1_14,
DA830_GPIO1_15,
DA830_GPIO2_0,
DA830_GPIO2_1,
DA830_NEMA_RAS,
DA830_NEMA_WE,
DA830_NEMA_CS_0,
DA830_NEMA_CS_2,
DA830_NEMA_CS_3,
DA830_NEMA_OE,
DA830_NEMA_WE_DQM_1,
DA830_NEMA_WE_DQM_0,
DA830_NEMA_CS_5,
DA830_UHPI_HRNW,
DA830_NUHPI_HAS,
DA830_NUHPI_HCS,
DA830_NUHPI_HDS1,
DA830_NUHPI_HDS2,
DA830_NUHPI_HINT,
DA830_AXR0_12,
DA830_AMUTE2,
DA830_AXR0_13,
DA830_AXR0_14,
DA830_AXR0_15,
DA830_GPIO2_2,
DA830_GPIO2_3,
DA830_GPIO2_4,
DA830_GPIO2_5,
DA830_GPIO2_6,
DA830_GPIO2_7,
DA830_GPIO2_8,
DA830_GPIO2_9,
DA830_EMA_WAIT_0,
DA830_NUHPI_HRDY,
DA830_GPIO2_10,
};
enum davinci_da850_index {
/* UART0 function */
DA850_NUART0_CTS,
DA850_NUART0_RTS,
DA850_UART0_RXD,
DA850_UART0_TXD,
/* UART1 function */
DA850_NUART1_CTS,
DA850_NUART1_RTS,
DA850_UART1_RXD,
DA850_UART1_TXD,
/* UART2 function */
DA850_NUART2_CTS,
DA850_NUART2_RTS,
DA850_UART2_RXD,
DA850_UART2_TXD,
/* I2C1 function */
DA850_I2C1_SCL,
DA850_I2C1_SDA,
/* I2C0 function */
DA850_I2C0_SDA,
DA850_I2C0_SCL,
/* EMAC function */
DA850_MII_TXEN,
DA850_MII_TXCLK,
DA850_MII_COL,
DA850_MII_TXD_3,
DA850_MII_TXD_2,
DA850_MII_TXD_1,
DA850_MII_TXD_0,
DA850_MII_RXER,
DA850_MII_CRS,
DA850_MII_RXCLK,
DA850_MII_RXDV,
DA850_MII_RXD_3,
DA850_MII_RXD_2,
DA850_MII_RXD_1,
DA850_MII_RXD_0,
DA850_MDIO_CLK,
DA850_MDIO_D,
DA850_RMII_TXD_0,
DA850_RMII_TXD_1,
DA850_RMII_TXEN,
DA850_RMII_CRS_DV,
DA850_RMII_RXD_0,
DA850_RMII_RXD_1,
DA850_RMII_RXER,
DA850_RMII_MHZ_50_CLK,
/* McASP function */
DA850_ACLKR,
DA850_ACLKX,
DA850_AFSR,
DA850_AFSX,
DA850_AHCLKR,
DA850_AHCLKX,
DA850_AMUTE,
DA850_AXR_15,
DA850_AXR_14,
DA850_AXR_13,
DA850_AXR_12,
DA850_AXR_11,
DA850_AXR_10,
DA850_AXR_9,
DA850_AXR_8,
DA850_AXR_7,
DA850_AXR_6,
DA850_AXR_5,
DA850_AXR_4,
DA850_AXR_3,
DA850_AXR_2,
DA850_AXR_1,
DA850_AXR_0,
/* LCD function */
DA850_LCD_D_7,
DA850_LCD_D_6,
DA850_LCD_D_5,
DA850_LCD_D_4,
DA850_LCD_D_3,
DA850_LCD_D_2,
DA850_LCD_D_1,
DA850_LCD_D_0,
DA850_LCD_D_15,
DA850_LCD_D_14,
DA850_LCD_D_13,
DA850_LCD_D_12,
DA850_LCD_D_11,
DA850_LCD_D_10,
DA850_LCD_D_9,
DA850_LCD_D_8,
DA850_LCD_PCLK,
DA850_LCD_HSYNC,
DA850_LCD_VSYNC,
DA850_NLCD_AC_ENB_CS,
/* MMC/SD0 function */
DA850_MMCSD0_DAT_0,
DA850_MMCSD0_DAT_1,
DA850_MMCSD0_DAT_2,
DA850_MMCSD0_DAT_3,
DA850_MMCSD0_CLK,
DA850_MMCSD0_CMD,
/* MMC/SD1 function */
DA850_MMCSD1_DAT_0,
DA850_MMCSD1_DAT_1,
DA850_MMCSD1_DAT_2,
DA850_MMCSD1_DAT_3,
DA850_MMCSD1_CLK,
DA850_MMCSD1_CMD,
/* EMIF2.5/EMIFA function */
DA850_EMA_D_7,
DA850_EMA_D_6,
DA850_EMA_D_5,
DA850_EMA_D_4,
DA850_EMA_D_3,
DA850_EMA_D_2,
DA850_EMA_D_1,
DA850_EMA_D_0,
DA850_EMA_A_1,
DA850_EMA_A_2,
DA850_NEMA_CS_3,
DA850_NEMA_CS_4,
DA850_NEMA_WE,
DA850_NEMA_OE,
DA850_EMA_D_15,
DA850_EMA_D_14,
DA850_EMA_D_13,
DA850_EMA_D_12,
DA850_EMA_D_11,
DA850_EMA_D_10,
DA850_EMA_D_9,
DA850_EMA_D_8,
DA850_EMA_A_0,
DA850_EMA_A_3,
DA850_EMA_A_4,
DA850_EMA_A_5,
DA850_EMA_A_6,
DA850_EMA_A_7,
DA850_EMA_A_8,
DA850_EMA_A_9,
DA850_EMA_A_10,
DA850_EMA_A_11,
DA850_EMA_A_12,
DA850_EMA_A_13,
DA850_EMA_A_14,
DA850_EMA_A_15,
DA850_EMA_A_16,
DA850_EMA_A_17,
DA850_EMA_A_18,
DA850_EMA_A_19,
DA850_EMA_A_20,
DA850_EMA_A_21,
DA850_EMA_A_22,
DA850_EMA_A_23,
DA850_EMA_BA_1,
DA850_EMA_CLK,
DA850_EMA_WAIT_1,
DA850_NEMA_CS_2,
/* GPIO function */
DA850_GPIO2_4,
DA850_GPIO2_6,
DA850_GPIO2_8,
DA850_GPIO2_15,
DA850_GPIO3_12,
DA850_GPIO3_13,
DA850_GPIO4_0,
DA850_GPIO4_1,
DA850_GPIO6_9,
DA850_GPIO6_10,
DA850_GPIO6_13,
DA850_RTC_ALARM,
/* VPIF Capture */
DA850_VPIF_DIN0,
DA850_VPIF_DIN1,
DA850_VPIF_DIN2,
DA850_VPIF_DIN3,
DA850_VPIF_DIN4,
DA850_VPIF_DIN5,
DA850_VPIF_DIN6,
DA850_VPIF_DIN7,
DA850_VPIF_DIN8,
DA850_VPIF_DIN9,
DA850_VPIF_DIN10,
DA850_VPIF_DIN11,
DA850_VPIF_DIN12,
DA850_VPIF_DIN13,
DA850_VPIF_DIN14,
DA850_VPIF_DIN15,
DA850_VPIF_CLKIN0,
DA850_VPIF_CLKIN1,
DA850_VPIF_CLKIN2,
DA850_VPIF_CLKIN3,
/* VPIF Display */
DA850_VPIF_DOUT0,
DA850_VPIF_DOUT1,
DA850_VPIF_DOUT2,
DA850_VPIF_DOUT3,
DA850_VPIF_DOUT4,
DA850_VPIF_DOUT5,
DA850_VPIF_DOUT6,
DA850_VPIF_DOUT7,
DA850_VPIF_DOUT8,
DA850_VPIF_DOUT9,
DA850_VPIF_DOUT10,
DA850_VPIF_DOUT11,
DA850_VPIF_DOUT12,
DA850_VPIF_DOUT13,
DA850_VPIF_DOUT14,
DA850_VPIF_DOUT15,
DA850_VPIF_CLKO2,
DA850_VPIF_CLKO3,
};
#define PINMUX(x) (4 * (x))
#ifdef CONFIG_DAVINCI_MUX
/* setup pin muxing */
extern int davinci_cfg_reg(unsigned long reg_cfg);
extern int davinci_cfg_reg_list(const short pins[]);
#else
/* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */
static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; }
static inline int davinci_cfg_reg_list(const short pins[])
{
return 0;
}
#endif
#endif /* __INC_MACH_MUX_H */

97
arch/arm/mach-davinci/include/mach/uncompress.h
View File

@ -1,97 +0,0 @@
/*
* Serial port stubs for kernel decompress status messages
*
* Initially based on:
* arch/arm/plat-omap/include/mach/uncompress.h
*
* Original copyrights follow.
*
* Copyright (C) 2000 RidgeRun, Inc.
* Author: Greg Lonnon <glonnon@ridgerun.com>
*
* Rewritten by:
* Author: <source@mvista.com>
* 2004 (c) MontaVista Software, Inc.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#include <linux/types.h>
#include <linux/serial_reg.h>
#include <asm/mach-types.h>
#include <mach/serial.h>
#define IOMEM(x) ((void __force __iomem *)(x))
u32 *uart;
/* PORT_16C550A, in polled non-fifo mode */
static inline void putc(char c)
{
if (!uart)
return;
while (!(uart[UART_LSR] & UART_LSR_THRE))
barrier();
uart[UART_TX] = c;
}
static inline void flush(void)
{
if (!uart)
return;
while (!(uart[UART_LSR] & UART_LSR_THRE))
barrier();
}
static inline void set_uart_info(u32 phys)
{
uart = (u32 *)phys;
}
#define _DEBUG_LL_ENTRY(machine, phys) \
{ \
if (machine_is_##machine()) { \
set_uart_info(phys); \
break; \
} \
}
#define DEBUG_LL_DAVINCI(machine, port) \
_DEBUG_LL_ENTRY(machine, DAVINCI_UART##port##_BASE)
#define DEBUG_LL_DA8XX(machine, port) \
_DEBUG_LL_ENTRY(machine, DA8XX_UART##port##_BASE)
static inline void __arch_decomp_setup(unsigned long arch_id)
{
/*
* Initialize the port based on the machine ID from the bootloader.
* Note that we're using macros here instead of switch statement
* as machine_is functions are optimized out for the boards that
* are not selected.
*/
do {
/* Davinci boards */
DEBUG_LL_DAVINCI(davinci_evm, 0);
DEBUG_LL_DAVINCI(sffsdr, 0);
DEBUG_LL_DAVINCI(neuros_osd2, 0);
DEBUG_LL_DAVINCI(davinci_dm355_evm, 0);
DEBUG_LL_DAVINCI(dm355_leopard, 0);
DEBUG_LL_DAVINCI(davinci_dm6467_evm, 0);
DEBUG_LL_DAVINCI(davinci_dm365_evm, 0);
/* DA8xx boards */
DEBUG_LL_DA8XX(davinci_da830_evm, 2);
DEBUG_LL_DA8XX(davinci_da850_evm, 2);
DEBUG_LL_DA8XX(mityomapl138, 1);
DEBUG_LL_DA8XX(omapl138_hawkboard, 2);
} while (0);
}
#define arch_decomp_setup() __arch_decomp_setup(arch_id)

4
arch/arm/mach-davinci/mux.c
View File

@ -22,8 +22,8 @@
#include <linux/module.h>
#include <linux/spinlock.h>
#include <mach/mux.h>
#include <mach/common.h>
#include "mux.h"
#include "common.h"
static void __iomem *pinmux_base;

969
arch/arm/mach-davinci/mux.h
View File

@ -13,7 +13,974 @@
#ifndef _MACH_DAVINCI_MUX_H_
#define _MACH_DAVINCI_MUX_H_
#include <mach/mux.h>
struct mux_config {
const char *name;
const char *mux_reg_name;
const unsigned char mux_reg;
const unsigned char mask_offset;
const unsigned char mask;
const unsigned char mode;
bool debug;
};
enum davinci_dm644x_index {
/* ATA and HDDIR functions */
DM644X_HDIREN,
DM644X_ATAEN,
DM644X_ATAEN_DISABLE,
/* HPI functions */
DM644X_HPIEN_DISABLE,
/* AEAW functions */
DM644X_AEAW,
DM644X_AEAW0,
DM644X_AEAW1,
DM644X_AEAW2,
DM644X_AEAW3,
DM644X_AEAW4,
/* Memory Stick */
DM644X_MSTK,
/* I2C */
DM644X_I2C,
/* ASP function */
DM644X_MCBSP,
/* UART1 */
DM644X_UART1,
/* UART2 */
DM644X_UART2,
/* PWM0 */
DM644X_PWM0,
/* PWM1 */
DM644X_PWM1,
/* PWM2 */
DM644X_PWM2,
/* VLYNQ function */
DM644X_VLYNQEN,
DM644X_VLSCREN,
DM644X_VLYNQWD,
/* EMAC and MDIO function */
DM644X_EMACEN,
/* GPIO3V[0:16] pins */
DM644X_GPIO3V,
/* GPIO pins */
DM644X_GPIO0,
DM644X_GPIO3,
DM644X_GPIO43_44,
DM644X_GPIO46_47,
/* VPBE */
DM644X_RGB666,
/* LCD */
DM644X_LOEEN,
DM644X_LFLDEN,
};
enum davinci_dm646x_index {
/* ATA function */
DM646X_ATAEN,
/* AUDIO Clock */
DM646X_AUDCK1,
DM646X_AUDCK0,
/* CRGEN Control */
DM646X_CRGMUX,
/* VPIF Control */
DM646X_STSOMUX_DISABLE,
DM646X_STSIMUX_DISABLE,
DM646X_PTSOMUX_DISABLE,
DM646X_PTSIMUX_DISABLE,
/* TSIF Control */
DM646X_STSOMUX,
DM646X_STSIMUX,
DM646X_PTSOMUX_PARALLEL,
DM646X_PTSIMUX_PARALLEL,
DM646X_PTSOMUX_SERIAL,
DM646X_PTSIMUX_SERIAL,
};
enum davinci_dm355_index {
/* MMC/SD 0 */
DM355_MMCSD0,
/* MMC/SD 1 */
DM355_SD1_CLK,
DM355_SD1_CMD,
DM355_SD1_DATA3,
DM355_SD1_DATA2,
DM355_SD1_DATA1,
DM355_SD1_DATA0,
/* I2C */
DM355_I2C_SDA,
DM355_I2C_SCL,
/* ASP0 function */
DM355_MCBSP0_BDX,
DM355_MCBSP0_X,
DM355_MCBSP0_BFSX,
DM355_MCBSP0_BDR,
DM355_MCBSP0_R,
DM355_MCBSP0_BFSR,
/* SPI0 */
DM355_SPI0_SDI,
DM355_SPI0_SDENA0,
DM355_SPI0_SDENA1,
/* IRQ muxing */
DM355_INT_EDMA_CC,
DM355_INT_EDMA_TC0_ERR,
DM355_INT_EDMA_TC1_ERR,
/* EDMA event muxing */
DM355_EVT8_ASP1_TX,
DM355_EVT9_ASP1_RX,
DM355_EVT26_MMC0_RX,
/* Video Out */
DM355_VOUT_FIELD,
DM355_VOUT_FIELD_G70,
DM355_VOUT_HVSYNC,
DM355_VOUT_COUTL_EN,
DM355_VOUT_COUTH_EN,
/* Video In Pin Mux */
DM355_VIN_PCLK,
DM355_VIN_CAM_WEN,
DM355_VIN_CAM_VD,
DM355_VIN_CAM_HD,
DM355_VIN_YIN_EN,
DM355_VIN_CINL_EN,
DM355_VIN_CINH_EN,
};
enum davinci_dm365_index {
/* MMC/SD 0 */
DM365_MMCSD0,
/* MMC/SD 1 */
DM365_SD1_CLK,
DM365_SD1_CMD,
DM365_SD1_DATA3,
DM365_SD1_DATA2,
DM365_SD1_DATA1,
DM365_SD1_DATA0,
/* I2C */
DM365_I2C_SDA,
DM365_I2C_SCL,
/* AEMIF */
DM365_AEMIF_AR_A14,
DM365_AEMIF_AR_BA0,
DM365_AEMIF_A3,
DM365_AEMIF_A7,
DM365_AEMIF_D15_8,
DM365_AEMIF_CE0,
DM365_AEMIF_CE1,
DM365_AEMIF_WE_OE,
/* ASP0 function */
DM365_MCBSP0_BDX,
DM365_MCBSP0_X,
DM365_MCBSP0_BFSX,
DM365_MCBSP0_BDR,
DM365_MCBSP0_R,
DM365_MCBSP0_BFSR,
/* SPI0 */
DM365_SPI0_SCLK,
DM365_SPI0_SDI,
DM365_SPI0_SDO,
DM365_SPI0_SDENA0,
DM365_SPI0_SDENA1,
/* UART */
DM365_UART0_RXD,
DM365_UART0_TXD,
DM365_UART1_RXD,
DM365_UART1_TXD,
DM365_UART1_RTS,
DM365_UART1_CTS,
/* EMAC */
DM365_EMAC_TX_EN,
DM365_EMAC_TX_CLK,
DM365_EMAC_COL,
DM365_EMAC_TXD3,
DM365_EMAC_TXD2,
DM365_EMAC_TXD1,
DM365_EMAC_TXD0,
DM365_EMAC_RXD3,
DM365_EMAC_RXD2,
DM365_EMAC_RXD1,
DM365_EMAC_RXD0,
DM365_EMAC_RX_CLK,
DM365_EMAC_RX_DV,
DM365_EMAC_RX_ER,
DM365_EMAC_CRS,
DM365_EMAC_MDIO,
DM365_EMAC_MDCLK,
/* Key Scan */
DM365_KEYSCAN,
/* PWM */
DM365_PWM0,
DM365_PWM0_G23,
DM365_PWM1,
DM365_PWM1_G25,
DM365_PWM2_G87,
DM365_PWM2_G88,
DM365_PWM2_G89,
DM365_PWM2_G90,
DM365_PWM3_G80,
DM365_PWM3_G81,
DM365_PWM3_G85,
DM365_PWM3_G86,
/* SPI1 */
DM365_SPI1_SCLK,
DM365_SPI1_SDO,
DM365_SPI1_SDI,
DM365_SPI1_SDENA0,
DM365_SPI1_SDENA1,
/* SPI2 */
DM365_SPI2_SCLK,
DM365_SPI2_SDO,
DM365_SPI2_SDI,
DM365_SPI2_SDENA0,
DM365_SPI2_SDENA1,
/* SPI3 */
DM365_SPI3_SCLK,
DM365_SPI3_SDO,
DM365_SPI3_SDI,
DM365_SPI3_SDENA0,
DM365_SPI3_SDENA1,
/* SPI4 */
DM365_SPI4_SCLK,
DM365_SPI4_SDO,
DM365_SPI4_SDI,
DM365_SPI4_SDENA0,
DM365_SPI4_SDENA1,
/* Clock */
DM365_CLKOUT0,
DM365_CLKOUT1,
DM365_CLKOUT2,
/* GPIO */
DM365_GPIO20,
DM365_GPIO30,
DM365_GPIO31,
DM365_GPIO32,
DM365_GPIO33,
DM365_GPIO40,
DM365_GPIO64_57,
/* Video */
DM365_VOUT_FIELD,
DM365_VOUT_FIELD_G81,
DM365_VOUT_HVSYNC,
DM365_VOUT_COUTL_EN,
DM365_VOUT_COUTH_EN,
DM365_VIN_CAM_WEN,
DM365_VIN_CAM_VD,
DM365_VIN_CAM_HD,
DM365_VIN_YIN4_7_EN,
DM365_VIN_YIN0_3_EN,
/* IRQ muxing */
DM365_INT_EDMA_CC,
DM365_INT_EDMA_TC0_ERR,
DM365_INT_EDMA_TC1_ERR,
DM365_INT_EDMA_TC2_ERR,
DM365_INT_EDMA_TC3_ERR,
DM365_INT_PRTCSS,
DM365_INT_EMAC_RXTHRESH,
DM365_INT_EMAC_RXPULSE,
DM365_INT_EMAC_TXPULSE,
DM365_INT_EMAC_MISCPULSE,
DM365_INT_IMX0_ENABLE,
DM365_INT_IMX0_DISABLE,
DM365_INT_HDVICP_ENABLE,
DM365_INT_HDVICP_DISABLE,
DM365_INT_IMX1_ENABLE,
DM365_INT_IMX1_DISABLE,
DM365_INT_NSF_ENABLE,
DM365_INT_NSF_DISABLE,
/* EDMA event muxing */
DM365_EVT2_ASP_TX,
DM365_EVT3_ASP_RX,
DM365_EVT2_VC_TX,
DM365_EVT3_VC_RX,
DM365_EVT26_MMC0_RX,
};
enum da830_index {
DA830_GPIO7_14,
DA830_RTCK,
DA830_GPIO7_15,
DA830_EMU_0,
DA830_EMB_SDCKE,
DA830_EMB_CLK_GLUE,
DA830_EMB_CLK,
DA830_NEMB_CS_0,
DA830_NEMB_CAS,
DA830_NEMB_RAS,
DA830_NEMB_WE,
DA830_EMB_BA_1,
DA830_EMB_BA_0,
DA830_EMB_A_0,
DA830_EMB_A_1,
DA830_EMB_A_2,
DA830_EMB_A_3,
DA830_EMB_A_4,
DA830_EMB_A_5,
DA830_GPIO7_0,
DA830_GPIO7_1,
DA830_GPIO7_2,
DA830_GPIO7_3,
DA830_GPIO7_4,
DA830_GPIO7_5,
DA830_GPIO7_6,
DA830_GPIO7_7,
DA830_EMB_A_6,
DA830_EMB_A_7,
DA830_EMB_A_8,
DA830_EMB_A_9,
DA830_EMB_A_10,
DA830_EMB_A_11,
DA830_EMB_A_12,
DA830_EMB_D_31,
DA830_GPIO7_8,
DA830_GPIO7_9,
DA830_GPIO7_10,
DA830_GPIO7_11,
DA830_GPIO7_12,
DA830_GPIO7_13,
DA830_GPIO3_13,
DA830_EMB_D_30,
DA830_EMB_D_29,
DA830_EMB_D_28,
DA830_EMB_D_27,
DA830_EMB_D_26,
DA830_EMB_D_25,
DA830_EMB_D_24,
DA830_EMB_D_23,
DA830_EMB_D_22,
DA830_EMB_D_21,
DA830_EMB_D_20,
DA830_EMB_D_19,
DA830_EMB_D_18,
DA830_EMB_D_17,
DA830_EMB_D_16,
DA830_NEMB_WE_DQM_3,
DA830_NEMB_WE_DQM_2,
DA830_EMB_D_0,
DA830_EMB_D_1,
DA830_EMB_D_2,
DA830_EMB_D_3,
DA830_EMB_D_4,
DA830_EMB_D_5,
DA830_EMB_D_6,
DA830_GPIO6_0,
DA830_GPIO6_1,
DA830_GPIO6_2,
DA830_GPIO6_3,
DA830_GPIO6_4,
DA830_GPIO6_5,
DA830_GPIO6_6,
DA830_EMB_D_7,
DA830_EMB_D_8,
DA830_EMB_D_9,
DA830_EMB_D_10,
DA830_EMB_D_11,
DA830_EMB_D_12,
DA830_EMB_D_13,
DA830_EMB_D_14,
DA830_GPIO6_7,
DA830_GPIO6_8,
DA830_GPIO6_9,
DA830_GPIO6_10,
DA830_GPIO6_11,
DA830_GPIO6_12,
DA830_GPIO6_13,
DA830_GPIO6_14,
DA830_EMB_D_15,
DA830_NEMB_WE_DQM_1,
DA830_NEMB_WE_DQM_0,
DA830_SPI0_SOMI_0,
DA830_SPI0_SIMO_0,
DA830_SPI0_CLK,
DA830_NSPI0_ENA,
DA830_NSPI0_SCS_0,
DA830_EQEP0I,
DA830_EQEP0S,
DA830_EQEP1I,
DA830_NUART0_CTS,
DA830_NUART0_RTS,
DA830_EQEP0A,
DA830_EQEP0B,
DA830_GPIO6_15,
DA830_GPIO5_14,
DA830_GPIO5_15,
DA830_GPIO5_0,
DA830_GPIO5_1,
DA830_GPIO5_2,
DA830_GPIO5_3,
DA830_GPIO5_4,
DA830_SPI1_SOMI_0,
DA830_SPI1_SIMO_0,
DA830_SPI1_CLK,
DA830_UART0_RXD,
DA830_UART0_TXD,
DA830_AXR1_10,
DA830_AXR1_11,
DA830_NSPI1_ENA,
DA830_I2C1_SCL,
DA830_I2C1_SDA,
DA830_EQEP1S,
DA830_I2C0_SDA,
DA830_I2C0_SCL,
DA830_UART2_RXD,
DA830_TM64P0_IN12,
DA830_TM64P0_OUT12,
DA830_GPIO5_5,
DA830_GPIO5_6,
DA830_GPIO5_7,
DA830_GPIO5_8,
DA830_GPIO5_9,
DA830_GPIO5_10,
DA830_GPIO5_11,
DA830_GPIO5_12,
DA830_NSPI1_SCS_0,
DA830_USB0_DRVVBUS,
DA830_AHCLKX0,
DA830_ACLKX0,
DA830_AFSX0,
DA830_AHCLKR0,
DA830_ACLKR0,
DA830_AFSR0,
DA830_UART2_TXD,
DA830_AHCLKX2,
DA830_ECAP0_APWM0,
DA830_RMII_MHZ_50_CLK,
DA830_ECAP1_APWM1,
DA830_USB_REFCLKIN,
DA830_GPIO5_13,
DA830_GPIO4_15,
DA830_GPIO2_11,
DA830_GPIO2_12,
DA830_GPIO2_13,
DA830_GPIO2_14,
DA830_GPIO2_15,
DA830_GPIO3_12,
DA830_AMUTE0,
DA830_AXR0_0,
DA830_AXR0_1,
DA830_AXR0_2,
DA830_AXR0_3,
DA830_AXR0_4,
DA830_AXR0_5,
DA830_AXR0_6,
DA830_RMII_TXD_0,
DA830_RMII_TXD_1,
DA830_RMII_TXEN,
DA830_RMII_CRS_DV,
DA830_RMII_RXD_0,
DA830_RMII_RXD_1,
DA830_RMII_RXER,
DA830_AFSR2,
DA830_ACLKX2,
DA830_AXR2_3,
DA830_AXR2_2,
DA830_AXR2_1,
DA830_AFSX2,
DA830_ACLKR2,
DA830_NRESETOUT,
DA830_GPIO3_0,
DA830_GPIO3_1,
DA830_GPIO3_2,
DA830_GPIO3_3,
DA830_GPIO3_4,
DA830_GPIO3_5,
DA830_GPIO3_6,
DA830_AXR0_7,
DA830_AXR0_8,
DA830_UART1_RXD,
DA830_UART1_TXD,
DA830_AXR0_11,
DA830_AHCLKX1,
DA830_ACLKX1,
DA830_AFSX1,
DA830_MDIO_CLK,
DA830_MDIO_D,
DA830_AXR0_9,
DA830_AXR0_10,
DA830_EPWM0B,
DA830_EPWM0A,
DA830_EPWMSYNCI,
DA830_AXR2_0,
DA830_EPWMSYNC0,
DA830_GPIO3_7,
DA830_GPIO3_8,
DA830_GPIO3_9,
DA830_GPIO3_10,
DA830_GPIO3_11,
DA830_GPIO3_14,
DA830_GPIO3_15,
DA830_GPIO4_10,
DA830_AHCLKR1,
DA830_ACLKR1,
DA830_AFSR1,
DA830_AMUTE1,
DA830_AXR1_0,
DA830_AXR1_1,
DA830_AXR1_2,
DA830_AXR1_3,
DA830_ECAP2_APWM2,
DA830_EHRPWMGLUETZ,
DA830_EQEP1A,
DA830_GPIO4_11,
DA830_GPIO4_12,
DA830_GPIO4_13,
DA830_GPIO4_14,
DA830_GPIO4_0,
DA830_GPIO4_1,
DA830_GPIO4_2,
DA830_GPIO4_3,
DA830_AXR1_4,
DA830_AXR1_5,
DA830_AXR1_6,
DA830_AXR1_7,
DA830_AXR1_8,
DA830_AXR1_9,
DA830_EMA_D_0,
DA830_EMA_D_1,
DA830_EQEP1B,
DA830_EPWM2B,
DA830_EPWM2A,
DA830_EPWM1B,
DA830_EPWM1A,
DA830_MMCSD_DAT_0,
DA830_MMCSD_DAT_1,
DA830_UHPI_HD_0,
DA830_UHPI_HD_1,
DA830_GPIO4_4,
DA830_GPIO4_5,
DA830_GPIO4_6,
DA830_GPIO4_7,
DA830_GPIO4_8,
DA830_GPIO4_9,
DA830_GPIO0_0,
DA830_GPIO0_1,
DA830_EMA_D_2,
DA830_EMA_D_3,
DA830_EMA_D_4,
DA830_EMA_D_5,
DA830_EMA_D_6,
DA830_EMA_D_7,
DA830_EMA_D_8,
DA830_EMA_D_9,
DA830_MMCSD_DAT_2,
DA830_MMCSD_DAT_3,
DA830_MMCSD_DAT_4,
DA830_MMCSD_DAT_5,
DA830_MMCSD_DAT_6,
DA830_MMCSD_DAT_7,
DA830_UHPI_HD_8,
DA830_UHPI_HD_9,
DA830_UHPI_HD_2,
DA830_UHPI_HD_3,
DA830_UHPI_HD_4,
DA830_UHPI_HD_5,
DA830_UHPI_HD_6,
DA830_UHPI_HD_7,
DA830_LCD_D_8,
DA830_LCD_D_9,
DA830_GPIO0_2,
DA830_GPIO0_3,
DA830_GPIO0_4,
DA830_GPIO0_5,
DA830_GPIO0_6,
DA830_GPIO0_7,
DA830_GPIO0_8,
DA830_GPIO0_9,
DA830_EMA_D_10,
DA830_EMA_D_11,
DA830_EMA_D_12,
DA830_EMA_D_13,
DA830_EMA_D_14,
DA830_EMA_D_15,
DA830_EMA_A_0,
DA830_EMA_A_1,
DA830_UHPI_HD_10,
DA830_UHPI_HD_11,
DA830_UHPI_HD_12,
DA830_UHPI_HD_13,
DA830_UHPI_HD_14,
DA830_UHPI_HD_15,
DA830_LCD_D_7,
DA830_MMCSD_CLK,
DA830_LCD_D_10,
DA830_LCD_D_11,
DA830_LCD_D_12,
DA830_LCD_D_13,
DA830_LCD_D_14,
DA830_LCD_D_15,
DA830_UHPI_HCNTL0,
DA830_GPIO0_10,
DA830_GPIO0_11,
DA830_GPIO0_12,
DA830_GPIO0_13,
DA830_GPIO0_14,
DA830_GPIO0_15,
DA830_GPIO1_0,
DA830_GPIO1_1,
DA830_EMA_A_2,
DA830_EMA_A_3,
DA830_EMA_A_4,
DA830_EMA_A_5,
DA830_EMA_A_6,
DA830_EMA_A_7,
DA830_EMA_A_8,
DA830_EMA_A_9,
DA830_MMCSD_CMD,
DA830_LCD_D_6,
DA830_LCD_D_3,
DA830_LCD_D_2,
DA830_LCD_D_1,
DA830_LCD_D_0,
DA830_LCD_PCLK,
DA830_LCD_HSYNC,
DA830_UHPI_HCNTL1,
DA830_GPIO1_2,
DA830_GPIO1_3,
DA830_GPIO1_4,
DA830_GPIO1_5,
DA830_GPIO1_6,
DA830_GPIO1_7,
DA830_GPIO1_8,
DA830_GPIO1_9,
DA830_EMA_A_10,
DA830_EMA_A_11,
DA830_EMA_A_12,
DA830_EMA_BA_1,
DA830_EMA_BA_0,
DA830_EMA_CLK,
DA830_EMA_SDCKE,
DA830_NEMA_CAS,
DA830_LCD_VSYNC,
DA830_NLCD_AC_ENB_CS,
DA830_LCD_MCLK,
DA830_LCD_D_5,
DA830_LCD_D_4,
DA830_OBSCLK,
DA830_NEMA_CS_4,
DA830_UHPI_HHWIL,
DA830_AHCLKR2,
DA830_GPIO1_10,
DA830_GPIO1_11,
DA830_GPIO1_12,
DA830_GPIO1_13,
DA830_GPIO1_14,
DA830_GPIO1_15,
DA830_GPIO2_0,
DA830_GPIO2_1,
DA830_NEMA_RAS,
DA830_NEMA_WE,
DA830_NEMA_CS_0,
DA830_NEMA_CS_2,
DA830_NEMA_CS_3,
DA830_NEMA_OE,
DA830_NEMA_WE_DQM_1,
DA830_NEMA_WE_DQM_0,
DA830_NEMA_CS_5,
DA830_UHPI_HRNW,
DA830_NUHPI_HAS,
DA830_NUHPI_HCS,
DA830_NUHPI_HDS1,
DA830_NUHPI_HDS2,
DA830_NUHPI_HINT,
DA830_AXR0_12,
DA830_AMUTE2,
DA830_AXR0_13,
DA830_AXR0_14,
DA830_AXR0_15,
DA830_GPIO2_2,
DA830_GPIO2_3,
DA830_GPIO2_4,
DA830_GPIO2_5,
DA830_GPIO2_6,
DA830_GPIO2_7,
DA830_GPIO2_8,
DA830_GPIO2_9,
DA830_EMA_WAIT_0,
DA830_NUHPI_HRDY,
DA830_GPIO2_10,
};
enum davinci_da850_index {
/* UART0 function */
DA850_NUART0_CTS,
DA850_NUART0_RTS,
DA850_UART0_RXD,
DA850_UART0_TXD,
/* UART1 function */
DA850_NUART1_CTS,
DA850_NUART1_RTS,
DA850_UART1_RXD,
DA850_UART1_TXD,
/* UART2 function */
DA850_NUART2_CTS,
DA850_NUART2_RTS,
DA850_UART2_RXD,
DA850_UART2_TXD,
/* I2C1 function */
DA850_I2C1_SCL,
DA850_I2C1_SDA,
/* I2C0 function */
DA850_I2C0_SDA,
DA850_I2C0_SCL,
/* EMAC function */
DA850_MII_TXEN,
DA850_MII_TXCLK,
DA850_MII_COL,
DA850_MII_TXD_3,
DA850_MII_TXD_2,
DA850_MII_TXD_1,
DA850_MII_TXD_0,
DA850_MII_RXER,
DA850_MII_CRS,
DA850_MII_RXCLK,
DA850_MII_RXDV,
DA850_MII_RXD_3,
DA850_MII_RXD_2,
DA850_MII_RXD_1,
DA850_MII_RXD_0,
DA850_MDIO_CLK,
DA850_MDIO_D,
DA850_RMII_TXD_0,
DA850_RMII_TXD_1,
DA850_RMII_TXEN,
DA850_RMII_CRS_DV,
DA850_RMII_RXD_0,
DA850_RMII_RXD_1,
DA850_RMII_RXER,
DA850_RMII_MHZ_50_CLK,
/* McASP function */
DA850_ACLKR,
DA850_ACLKX,
DA850_AFSR,
DA850_AFSX,
DA850_AHCLKR,
DA850_AHCLKX,
DA850_AMUTE,
DA850_AXR_15,
DA850_AXR_14,
DA850_AXR_13,
DA850_AXR_12,
DA850_AXR_11,
DA850_AXR_10,
DA850_AXR_9,
DA850_AXR_8,
DA850_AXR_7,
DA850_AXR_6,
DA850_AXR_5,
DA850_AXR_4,
DA850_AXR_3,
DA850_AXR_2,
DA850_AXR_1,
DA850_AXR_0,
/* LCD function */
DA850_LCD_D_7,
DA850_LCD_D_6,
DA850_LCD_D_5,
DA850_LCD_D_4,
DA850_LCD_D_3,
DA850_LCD_D_2,
DA850_LCD_D_1,
DA850_LCD_D_0,
DA850_LCD_D_15,
DA850_LCD_D_14,
DA850_LCD_D_13,
DA850_LCD_D_12,
DA850_LCD_D_11,
DA850_LCD_D_10,
DA850_LCD_D_9,
DA850_LCD_D_8,
DA850_LCD_PCLK,
DA850_LCD_HSYNC,
DA850_LCD_VSYNC,
DA850_NLCD_AC_ENB_CS,
/* MMC/SD0 function */
DA850_MMCSD0_DAT_0,
DA850_MMCSD0_DAT_1,
DA850_MMCSD0_DAT_2,
DA850_MMCSD0_DAT_3,
DA850_MMCSD0_CLK,
DA850_MMCSD0_CMD,
/* MMC/SD1 function */
DA850_MMCSD1_DAT_0,
DA850_MMCSD1_DAT_1,
DA850_MMCSD1_DAT_2,
DA850_MMCSD1_DAT_3,
DA850_MMCSD1_CLK,
DA850_MMCSD1_CMD,
/* EMIF2.5/EMIFA function */
DA850_EMA_D_7,
DA850_EMA_D_6,
DA850_EMA_D_5,
DA850_EMA_D_4,
DA850_EMA_D_3,
DA850_EMA_D_2,
DA850_EMA_D_1,
DA850_EMA_D_0,
DA850_EMA_A_1,
DA850_EMA_A_2,
DA850_NEMA_CS_3,
DA850_NEMA_CS_4,
DA850_NEMA_WE,
DA850_NEMA_OE,
DA850_EMA_D_15,
DA850_EMA_D_14,
DA850_EMA_D_13,
DA850_EMA_D_12,
DA850_EMA_D_11,
DA850_EMA_D_10,
DA850_EMA_D_9,
DA850_EMA_D_8,
DA850_EMA_A_0,
DA850_EMA_A_3,
DA850_EMA_A_4,
DA850_EMA_A_5,
DA850_EMA_A_6,
DA850_EMA_A_7,
DA850_EMA_A_8,
DA850_EMA_A_9,
DA850_EMA_A_10,
DA850_EMA_A_11,
DA850_EMA_A_12,
DA850_EMA_A_13,
DA850_EMA_A_14,
DA850_EMA_A_15,
DA850_EMA_A_16,
DA850_EMA_A_17,
DA850_EMA_A_18,
DA850_EMA_A_19,
DA850_EMA_A_20,
DA850_EMA_A_21,
DA850_EMA_A_22,
DA850_EMA_A_23,
DA850_EMA_BA_1,
DA850_EMA_CLK,
DA850_EMA_WAIT_1,
DA850_NEMA_CS_2,
/* GPIO function */
DA850_GPIO2_4,
DA850_GPIO2_6,
DA850_GPIO2_8,
DA850_GPIO2_15,
DA850_GPIO3_12,
DA850_GPIO3_13,
DA850_GPIO4_0,
DA850_GPIO4_1,
DA850_GPIO6_9,
DA850_GPIO6_10,
DA850_GPIO6_13,
DA850_RTC_ALARM,
/* VPIF Capture */
DA850_VPIF_DIN0,
DA850_VPIF_DIN1,
DA850_VPIF_DIN2,
DA850_VPIF_DIN3,
DA850_VPIF_DIN4,
DA850_VPIF_DIN5,
DA850_VPIF_DIN6,
DA850_VPIF_DIN7,
DA850_VPIF_DIN8,
DA850_VPIF_DIN9,
DA850_VPIF_DIN10,
DA850_VPIF_DIN11,
DA850_VPIF_DIN12,
DA850_VPIF_DIN13,
DA850_VPIF_DIN14,
DA850_VPIF_DIN15,
DA850_VPIF_CLKIN0,
DA850_VPIF_CLKIN1,
DA850_VPIF_CLKIN2,
DA850_VPIF_CLKIN3,
/* VPIF Display */
DA850_VPIF_DOUT0,
DA850_VPIF_DOUT1,
DA850_VPIF_DOUT2,
DA850_VPIF_DOUT3,
DA850_VPIF_DOUT4,
DA850_VPIF_DOUT5,
DA850_VPIF_DOUT6,
DA850_VPIF_DOUT7,
DA850_VPIF_DOUT8,
DA850_VPIF_DOUT9,
DA850_VPIF_DOUT10,
DA850_VPIF_DOUT11,
DA850_VPIF_DOUT12,
DA850_VPIF_DOUT13,
DA850_VPIF_DOUT14,
DA850_VPIF_DOUT15,
DA850_VPIF_CLKO2,
DA850_VPIF_CLKO3,
};
#define PINMUX(x) (4 * (x))
#ifdef CONFIG_DAVINCI_MUX
/* setup pin muxing */
extern int davinci_cfg_reg(unsigned long reg_cfg);
extern int davinci_cfg_reg_list(const short pins[]);
#else
/* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */
static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; }
static inline int davinci_cfg_reg_list(const short pins[])
{
return 0;
}
#endif
#define MUX_CFG(soc, desc, muxreg, mode_offset, mode_mask, mux_mode, dbg)\
[soc##_##desc] = { \

4
arch/arm/mach-davinci/pdata-quirks.c
View File

@ -10,8 +10,8 @@
#include <media/i2c/tvp514x.h>
#include <media/i2c/adv7343.h>
#include <mach/common.h>
#include <mach/da8xx.h>
#include "common.h"
#include "da8xx.h"
struct pdata_init {
const char *compatible;

9
arch/arm/mach-davinci/pm.c
View File

@ -16,11 +16,10 @@
#include <asm/delay.h>
#include <asm/io.h>
#include <mach/common.h>
#include <mach/da8xx.h>
#include <mach/mux.h>
#include <mach/pm.h>
#include "common.h"
#include "da8xx.h"
#include "mux.h"
#include "pm.h"
#include "clock.h"
#include "psc.h"
#include "sram.h"

0
arch/arm/mach-davinci/include/mach/pm.h → arch/arm/mach-davinci/pm.h
View File

4
arch/arm/mach-davinci/serial.c
View File

@ -14,8 +14,8 @@
#include <linux/clk.h>
#include <linux/io.h>
#include <mach/serial.h>
#include <mach/cputype.h>
#include "serial.h"
#include "cputype.h"
static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
int value)

2
arch/arm/mach-davinci/include/mach/serial.h → arch/arm/mach-davinci/serial.h
View File

@ -13,7 +13,7 @@
#include <asm/memory.h>
#include <mach/hardware.h>
#include "hardware.h"
#define DAVINCI_UART0_BASE (IO_PHYS + 0x20000)
#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400)

2
arch/arm/mach-davinci/sram.c
View File

@ -9,7 +9,7 @@
#include <linux/io.h>
#include <linux/genalloc.h>
#include <mach/common.h>
#include "common.h"
#include "sram.h"
static struct gen_pool *sram_pool;

7
arch/arm/mach-davinci/usb-da8xx.c
View File

@ -15,10 +15,9 @@
#include <linux/platform_device.h>
#include <linux/usb/musb.h>
#include <mach/common.h>
#include <mach/cputype.h>
#include <mach/da8xx.h>
#include "common.h"
#include "cputype.h"
#include "da8xx.h"
#include "irqs.h"
#define DA8XX_USB0_BASE 0x01e00000

5
arch/arm/mach-davinci/usb.c
View File

@ -8,9 +8,8 @@
#include <linux/platform_data/usb-davinci.h>
#include <linux/usb/musb.h>
#include <mach/common.h>
#include <mach/cputype.h>
#include "common.h"
#include "cputype.h"
#include "irqs.h"
#define DAVINCI_USB_OTG_BASE 0x01c64000

16
arch/arm/mach-dove/Kconfig
View File

@ -1,7 +1,17 @@
# SPDX-License-Identifier: GPL-2.0
if ARCH_DOVE
menuconfig ARCH_DOVE
bool "Marvell Dove" if ARCH_MULTI_V7
select CPU_PJ4
select GPIOLIB
select MVEBU_MBUS
select PINCTRL
select PINCTRL_DOVE
select PLAT_ORION_LEGACY
select PM_GENERIC_DOMAINS if PM
help
Support for the Marvell Dove SoC 88AP510
menu "Marvell Dove Implementations"
if ARCH_DOVE
config DOVE_LEGACY
bool
@ -21,6 +31,4 @@ config MACH_CM_A510
Say 'Y' here if you want your kernel to support the
CompuLab CM-A510 Board.
endmenu
endif

2
arch/arm/mach-dove/Makefile
View File

@ -1,4 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/arch/arm/plat-orion/include
obj-y += common.o
obj-$(CONFIG_DOVE_LEGACY) += irq.o mpp.o
obj-$(CONFIG_PCI) += pcie.o

34
arch/arm/mach-dove/include/mach/uncompress.h
View File

@ -1,34 +0,0 @@
/*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#define UART0_PHYS_BASE (0xf1000000 + 0x12000)
#define UART_THR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x0))
#define UART_LSR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x14))
#define LSR_THRE 0x20
static inline void putc(const char c)
{
int i;
for (i = 0; i < 0x1000; i++) {
/* Transmit fifo not full? */
if (*UART_LSR & LSR_THRE)
break;
}
*UART_THR = c;
}
static inline void flush(void)
{
}
/*
* nothing to do
*/
#define arch_decomp_setup()

13
arch/arm/mach-ep93xx/Kconfig
View File

@ -1,4 +1,17 @@
# SPDX-License-Identifier: GPL-2.0-only
menuconfig ARCH_EP93XX
bool "EP93xx-based"
depends on ARCH_MULTI_V4T
depends on CPU_LITTLE_ENDIAN
select ARCH_SPARSEMEM_ENABLE
select ARM_AMBA
select ARM_VIC
select CLKSRC_MMIO
select CPU_ARM920T
select GPIOLIB
help
This enables support for the Cirrus EP93xx series of CPUs.
if ARCH_EP93XX
menu "Cirrus EP93xx Implementation Options"

1
arch/arm/mach-ep93xx/adssphere.c
View File

@ -32,6 +32,7 @@ static void __init adssphere_init_machine(void)
MACHINE_START(ADSSPHERE, "ADS Sphere board")
/* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
.atag_offset = 0x100,
.nr_irqs = NR_EP93XX_IRQS,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,

5
arch/arm/mach-ep93xx/core.c
View File

@ -47,6 +47,7 @@
#include <asm/mach/map.h>
#include "soc.h"
#include "irqs.h"
/*************************************************************************
* Static I/O mappings that are needed for all EP93xx platforms
@ -75,8 +76,8 @@ void __init ep93xx_map_io(void)
*************************************************************************/
void __init ep93xx_init_irq(void)
{
vic_init(EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0);
vic_init(EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0);
vic_init(EP93XX_VIC1_BASE, IRQ_EP93XX_VIC0, EP93XX_VIC1_VALID_IRQ_MASK, 0);
vic_init(EP93XX_VIC2_BASE, IRQ_EP93XX_VIC1, EP93XX_VIC2_VALID_IRQ_MASK, 0);
}

8
arch/arm/mach-ep93xx/edb93xx.c
View File

@ -243,6 +243,7 @@ static void __init edb93xx_init_machine(void)
MACHINE_START(EDB9301, "Cirrus Logic EDB9301 Evaluation Board")
/* Maintainer: H Hartley Sweeten <hsweeten@visionengravers.com> */
.atag_offset = 0x100,
.nr_irqs = NR_EP93XX_IRQS,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
@ -255,6 +256,7 @@ MACHINE_END
MACHINE_START(EDB9302, "Cirrus Logic EDB9302 Evaluation Board")
/* Maintainer: George Kashperko <george@chas.com.ua> */
.atag_offset = 0x100,
.nr_irqs = NR_EP93XX_IRQS,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
@ -267,6 +269,7 @@ MACHINE_END
MACHINE_START(EDB9302A, "Cirrus Logic EDB9302A Evaluation Board")
/* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
.atag_offset = 0x100,
.nr_irqs = NR_EP93XX_IRQS,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
@ -279,6 +282,7 @@ MACHINE_END
MACHINE_START(EDB9307, "Cirrus Logic EDB9307 Evaluation Board")
/* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */
.atag_offset = 0x100,
.nr_irqs = NR_EP93XX_IRQS,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
@ -291,6 +295,7 @@ MACHINE_END
MACHINE_START(EDB9307A, "Cirrus Logic EDB9307A Evaluation Board")
/* Maintainer: H Hartley Sweeten <hsweeten@visionengravers.com> */
.atag_offset = 0x100,
.nr_irqs = NR_EP93XX_IRQS,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
@ -303,6 +308,7 @@ MACHINE_END
MACHINE_START(EDB9312, "Cirrus Logic EDB9312 Evaluation Board")
/* Maintainer: Toufeeq Hussain <toufeeq_hussain@infosys.com> */
.atag_offset = 0x100,
.nr_irqs = NR_EP93XX_IRQS,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
@ -315,6 +321,7 @@ MACHINE_END
MACHINE_START(EDB9315, "Cirrus Logic EDB9315 Evaluation Board")
/* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
.atag_offset = 0x100,
.nr_irqs = NR_EP93XX_IRQS,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
@ -327,6 +334,7 @@ MACHINE_END
MACHINE_START(EDB9315A, "Cirrus Logic EDB9315A Evaluation Board")
/* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
.atag_offset = 0x100,
.nr_irqs = NR_EP93XX_IRQS,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,

4
arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h → arch/arm/mach-ep93xx/ep93xx-regs.h
View File

@ -1,8 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
*/
#ifndef __ASM_ARCH_EP93XX_REGS_H
#define __ASM_ARCH_EP93XX_REGS_H

1
arch/arm/mach-ep93xx/gesbc9312.c
View File

@ -32,6 +32,7 @@ static void __init gesbc9312_init_machine(void)
MACHINE_START(GESBC9312, "Glomation GESBC-9312-sx")
/* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
.atag_offset = 0x100,
.nr_irqs = NR_EP93XX_IRQS,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,

2
arch/arm/mach-ep93xx/gpio-ep93xx.h
View File

@ -4,7 +4,7 @@
#ifndef __GPIO_EP93XX_H
#define __GPIO_EP93XX_H
#include <mach/ep93xx-regs.h>
#include "ep93xx-regs.h"
#define EP93XX_GPIO_PHYS_BASE EP93XX_APB_PHYS(0x00040000)
#define EP93XX_GPIO_BASE EP93XX_APB_IOMEM(0x00040000)

79
arch/arm/mach-ep93xx/include/mach/irqs.h
View File

@ -1,79 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* arch/arm/mach-ep93xx/include/mach/irqs.h
*/
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H
#define IRQ_EP93XX_COMMRX 2
#define IRQ_EP93XX_COMMTX 3
#define IRQ_EP93XX_TIMER1 4
#define IRQ_EP93XX_TIMER2 5
#define IRQ_EP93XX_AACINTR 6
#define IRQ_EP93XX_DMAM2P0 7
#define IRQ_EP93XX_DMAM2P1 8
#define IRQ_EP93XX_DMAM2P2 9
#define IRQ_EP93XX_DMAM2P3 10
#define IRQ_EP93XX_DMAM2P4 11
#define IRQ_EP93XX_DMAM2P5 12
#define IRQ_EP93XX_DMAM2P6 13
#define IRQ_EP93XX_DMAM2P7 14
#define IRQ_EP93XX_DMAM2P8 15
#define IRQ_EP93XX_DMAM2P9 16
#define IRQ_EP93XX_DMAM2M0 17
#define IRQ_EP93XX_DMAM2M1 18
#define IRQ_EP93XX_GPIO0MUX 19
#define IRQ_EP93XX_GPIO1MUX 20
#define IRQ_EP93XX_GPIO2MUX 21
#define IRQ_EP93XX_GPIO3MUX 22
#define IRQ_EP93XX_UART1RX 23
#define IRQ_EP93XX_UART1TX 24
#define IRQ_EP93XX_UART2RX 25
#define IRQ_EP93XX_UART2TX 26
#define IRQ_EP93XX_UART3RX 27
#define IRQ_EP93XX_UART3TX 28
#define IRQ_EP93XX_KEY 29
#define IRQ_EP93XX_TOUCH 30
#define EP93XX_VIC1_VALID_IRQ_MASK 0x7ffffffc
#define IRQ_EP93XX_EXT0 32
#define IRQ_EP93XX_EXT1 33
#define IRQ_EP93XX_EXT2 34
#define IRQ_EP93XX_64HZ 35
#define IRQ_EP93XX_WATCHDOG 36
#define IRQ_EP93XX_RTC 37
#define IRQ_EP93XX_IRDA 38
#define IRQ_EP93XX_ETHERNET 39
#define IRQ_EP93XX_EXT3 40
#define IRQ_EP93XX_PROG 41
#define IRQ_EP93XX_1HZ 42
#define IRQ_EP93XX_VSYNC 43
#define IRQ_EP93XX_VIDEO_FIFO 44
#define IRQ_EP93XX_SSP1RX 45
#define IRQ_EP93XX_SSP1TX 46
#define IRQ_EP93XX_GPIO4MUX 47
#define IRQ_EP93XX_GPIO5MUX 48
#define IRQ_EP93XX_GPIO6MUX 49
#define IRQ_EP93XX_GPIO7MUX 50
#define IRQ_EP93XX_TIMER3 51
#define IRQ_EP93XX_UART1 52
#define IRQ_EP93XX_SSP 53
#define IRQ_EP93XX_UART2 54
#define IRQ_EP93XX_UART3 55
#define IRQ_EP93XX_USB 56
#define IRQ_EP93XX_ETHERNET_PME 57
#define IRQ_EP93XX_DSP 58
#define IRQ_EP93XX_GPIO_AB 59
#define IRQ_EP93XX_SAI 60
#define EP93XX_VIC2_VALID_IRQ_MASK 0x1fffffff
#define NR_EP93XX_IRQS (64 + 24)
#define EP93XX_BOARD_IRQ(x) (NR_EP93XX_IRQS + (x))
#define EP93XX_BOARD_IRQS 32
#define NR_IRQS (NR_EP93XX_IRQS + EP93XX_BOARD_IRQS)
#endif

76
arch/arm/mach-ep93xx/irqs.h Normal file
View File

@ -0,0 +1,76 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H
#define IRQ_EP93XX_VIC0 1
#define IRQ_EP93XX_COMMRX (IRQ_EP93XX_VIC0 + 2)
#define IRQ_EP93XX_COMMTX (IRQ_EP93XX_VIC0 + 3)
#define IRQ_EP93XX_TIMER1 (IRQ_EP93XX_VIC0 + 4)
#define IRQ_EP93XX_TIMER2 (IRQ_EP93XX_VIC0 + 5)
#define IRQ_EP93XX_AACINTR (IRQ_EP93XX_VIC0 + 6)
#define IRQ_EP93XX_DMAM2P0 (IRQ_EP93XX_VIC0 + 7)
#define IRQ_EP93XX_DMAM2P1 (IRQ_EP93XX_VIC0 + 8)
#define IRQ_EP93XX_DMAM2P2 (IRQ_EP93XX_VIC0 + 9)
#define IRQ_EP93XX_DMAM2P3 (IRQ_EP93XX_VIC0 + 10)
#define IRQ_EP93XX_DMAM2P4 (IRQ_EP93XX_VIC0 + 11)
#define IRQ_EP93XX_DMAM2P5 (IRQ_EP93XX_VIC0 + 12)
#define IRQ_EP93XX_DMAM2P6 (IRQ_EP93XX_VIC0 + 13)
#define IRQ_EP93XX_DMAM2P7 (IRQ_EP93XX_VIC0 + 14)
#define IRQ_EP93XX_DMAM2P8 (IRQ_EP93XX_VIC0 + 15)
#define IRQ_EP93XX_DMAM2P9 (IRQ_EP93XX_VIC0 + 16)
#define IRQ_EP93XX_DMAM2M0 (IRQ_EP93XX_VIC0 + 17)
#define IRQ_EP93XX_DMAM2M1 (IRQ_EP93XX_VIC0 + 18)
#define IRQ_EP93XX_GPIO0MUX (IRQ_EP93XX_VIC0 + 19)
#define IRQ_EP93XX_GPIO1MUX (IRQ_EP93XX_VIC0 + 20)
#define IRQ_EP93XX_GPIO2MUX (IRQ_EP93XX_VIC0 + 21)
#define IRQ_EP93XX_GPIO3MUX (IRQ_EP93XX_VIC0 + 22)
#define IRQ_EP93XX_UART1RX (IRQ_EP93XX_VIC0 + 23)
#define IRQ_EP93XX_UART1TX (IRQ_EP93XX_VIC0 + 24)
#define IRQ_EP93XX_UART2RX (IRQ_EP93XX_VIC0 + 25)
#define IRQ_EP93XX_UART2TX (IRQ_EP93XX_VIC0 + 26)
#define IRQ_EP93XX_UART3RX (IRQ_EP93XX_VIC0 + 27)
#define IRQ_EP93XX_UART3TX (IRQ_EP93XX_VIC0 + 28)
#define IRQ_EP93XX_KEY (IRQ_EP93XX_VIC0 + 29)
#define IRQ_EP93XX_TOUCH (IRQ_EP93XX_VIC0 + 30)
#define EP93XX_VIC1_VALID_IRQ_MASK 0x7ffffffc
#define IRQ_EP93XX_VIC1 (IRQ_EP93XX_VIC0 + 32)
#define IRQ_EP93XX_EXT0 (IRQ_EP93XX_VIC1 + 0)
#define IRQ_EP93XX_EXT1 (IRQ_EP93XX_VIC1 + 1)
#define IRQ_EP93XX_EXT2 (IRQ_EP93XX_VIC1 + 2)
#define IRQ_EP93XX_64HZ (IRQ_EP93XX_VIC1 + 3)
#define IRQ_EP93XX_WATCHDOG (IRQ_EP93XX_VIC1 + 4)
#define IRQ_EP93XX_RTC (IRQ_EP93XX_VIC1 + 5)
#define IRQ_EP93XX_IRDA (IRQ_EP93XX_VIC1 + 6)
#define IRQ_EP93XX_ETHERNET (IRQ_EP93XX_VIC1 + 7)
#define IRQ_EP93XX_EXT3 (IRQ_EP93XX_VIC1 + 8)
#define IRQ_EP93XX_PROG (IRQ_EP93XX_VIC1 + 9)
#define IRQ_EP93XX_1HZ (IRQ_EP93XX_VIC1 + 10)
#define IRQ_EP93XX_VSYNC (IRQ_EP93XX_VIC1 + 11)
#define IRQ_EP93XX_VIDEO_FIFO (IRQ_EP93XX_VIC1 + 12)
#define IRQ_EP93XX_SSP1RX (IRQ_EP93XX_VIC1 + 13)
#define IRQ_EP93XX_SSP1TX (IRQ_EP93XX_VIC1 + 14)
#define IRQ_EP93XX_GPIO4MUX (IRQ_EP93XX_VIC1 + 15)
#define IRQ_EP93XX_GPIO5MUX (IRQ_EP93XX_VIC1 + 16)
#define IRQ_EP93XX_GPIO6MUX (IRQ_EP93XX_VIC1 + 17)
#define IRQ_EP93XX_GPIO7MUX (IRQ_EP93XX_VIC1 + 18)
#define IRQ_EP93XX_TIMER3 (IRQ_EP93XX_VIC1 + 19)
#define IRQ_EP93XX_UART1 (IRQ_EP93XX_VIC1 + 20)
#define IRQ_EP93XX_SSP (IRQ_EP93XX_VIC1 + 21)
#define IRQ_EP93XX_UART2 (IRQ_EP93XX_VIC1 + 22)
#define IRQ_EP93XX_UART3 (IRQ_EP93XX_VIC1 + 23)
#define IRQ_EP93XX_USB (IRQ_EP93XX_VIC1 + 24)
#define IRQ_EP93XX_ETHERNET_PME (IRQ_EP93XX_VIC1 + 25)
#define IRQ_EP93XX_DSP (IRQ_EP93XX_VIC1 + 26)
#define IRQ_EP93XX_GPIO_AB (IRQ_EP93XX_VIC1 + 27)
#define IRQ_EP93XX_SAI (IRQ_EP93XX_VIC1 + 28)
#define EP93XX_VIC2_VALID_IRQ_MASK 0x1fffffff
#define NR_EP93XX_IRQS (IRQ_EP93XX_VIC1 + 32 + 24)
#define EP93XX_BOARD_IRQ(x) (NR_EP93XX_IRQS + (x))
#define EP93XX_BOARD_IRQS 32
#endif

4
arch/arm/mach-ep93xx/micro9.c
View File

@ -76,6 +76,7 @@ static void __init micro9_init_machine(void)
MACHINE_START(MICRO9, "Contec Micro9-High")
/* Maintainer: Hubert Feurstein <hubert.feurstein@contec.at> */
.atag_offset = 0x100,
.nr_irqs = NR_EP93XX_IRQS,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
@ -88,6 +89,7 @@ MACHINE_END
MACHINE_START(MICRO9M, "Contec Micro9-Mid")
/* Maintainer: Hubert Feurstein <hubert.feurstein@contec.at> */
.atag_offset = 0x100,
.nr_irqs = NR_EP93XX_IRQS,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
@ -100,6 +102,7 @@ MACHINE_END
MACHINE_START(MICRO9L, "Contec Micro9-Lite")
/* Maintainer: Hubert Feurstein <hubert.feurstein@contec.at> */
.atag_offset = 0x100,
.nr_irqs = NR_EP93XX_IRQS,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
@ -112,6 +115,7 @@ MACHINE_END
MACHINE_START(MICRO9S, "Contec Micro9-Slim")
/* Maintainer: Hubert Feurstein <hubert.feurstein@contec.at> */
.atag_offset = 0x100,
.nr_irqs = NR_EP93XX_IRQS,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,

1
arch/arm/mach-ep93xx/simone.c
View File

@ -119,6 +119,7 @@ static void __init simone_init_machine(void)
MACHINE_START(SIM_ONE, "Simplemachines Sim.One Board")
/* Maintainer: Ryan Mallon */
.atag_offset = 0x100,
.nr_irqs = NR_EP93XX_IRQS,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,

1
arch/arm/mach-ep93xx/snappercl15.c
View File

@ -153,6 +153,7 @@ static void __init snappercl15_init_machine(void)
MACHINE_START(SNAPPER_CL15, "Bluewater Systems Snapper CL15")
/* Maintainer: Ryan Mallon */
.atag_offset = 0x100,
.nr_irqs = NR_EP93XX_IRQS,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,

3
arch/arm/mach-ep93xx/soc.h
View File

@ -9,7 +9,8 @@
#ifndef _EP93XX_SOC_H
#define _EP93XX_SOC_H
#include <mach/ep93xx-regs.h>
#include "ep93xx-regs.h"
#include "irqs.h"
/*
* EP93xx Physical Memory Map:

3
arch/arm/mach-ep93xx/ts72xx.c
View File

@ -22,7 +22,6 @@
#include "gpio-ep93xx.h"
#include "hardware.h"
#include <mach/irqs.h>
#include <asm/mach-types.h>
#include <asm/mach/map.h>
@ -350,6 +349,7 @@ static void __init ts72xx_init_machine(void)
MACHINE_START(TS72XX, "Technologic Systems TS-72xx SBC")
/* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
.atag_offset = 0x100,
.nr_irqs = NR_EP93XX_IRQS,
.map_io = ts72xx_map_io,
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
@ -413,6 +413,7 @@ static void __init bk3_init_machine(void)
MACHINE_START(BK3, "Liebherr controller BK3.1")
/* Maintainer: Lukasz Majewski <lukma@denx.de> */
.atag_offset = 0x100,
.nr_irqs = NR_EP93XX_IRQS,
.map_io = ts72xx_map_io,
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,

1
arch/arm/mach-ep93xx/vision_ep9307.c
View File

@ -302,6 +302,7 @@ static void __init vision_init_machine(void)
MACHINE_START(VISION_EP9307, "Vision Engraving Systems EP9307")
/* Maintainer: H Hartley Sweeten <hsweeten@visionengravers.com> */
.atag_offset = 0x100,
.nr_irqs = NR_EP93XX_IRQS + EP93XX_BOARD_IRQS,
.map_io = vision_map_io,
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,

1
arch/arm/mach-exynos/Kconfig
View File

@ -8,7 +8,6 @@
menuconfig ARCH_EXYNOS
bool "Samsung Exynos"
depends on ARCH_MULTI_V7
select ARCH_SUPPORTS_BIG_ENDIAN
select ARM_AMBA
select ARM_GIC
select EXYNOS_IRQ_COMBINER

1
arch/arm/mach-gemini/Kconfig
View File

@ -2,6 +2,7 @@
menuconfig ARCH_GEMINI
bool "Cortina Systems Gemini"
depends on ARCH_MULTI_V4
depends on CPU_LITTLE_ENDIAN
select ARCH_HAS_RESET_CONTROLLER
select ARM_AMBA
select ARM_APPENDED_DTB # Old Redboot bootloaders deployed

1
arch/arm/mach-highbank/Kconfig
View File

@ -2,7 +2,6 @@
config ARCH_HIGHBANK
bool "Calxeda ECX-1000/2000 (Highbank/Midway)"
depends on ARCH_MULTI_V7
select ARCH_SUPPORTS_BIG_ENDIAN
select ARM_AMBA
select ARM_ERRATA_764369 if SMP
select ARM_ERRATA_775420

2
arch/arm/mach-hisi/Kconfig
View File

@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
config ARCH_HISI
bool "Hisilicon SoC Support"
depends on ARCH_MULTI_V7 || ARCH_MULTI_V5
depends on ARCH_MULTI_V7 || (ARCH_MULTI_V5 && CPU_LITTLE_ENDIAN)
select ARM_AMBA
select ARM_GIC if ARCH_MULTI_V7
select ARM_TIMER_SP804

4
arch/arm/mach-imx/Kconfig
View File

@ -1,8 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-only
menuconfig ARCH_MXC
bool "Freescale i.MX family"
depends on ARCH_MULTI_V4_V5 || ARCH_MULTI_V6_V7 || ARM_SINGLE_ARMV7M
select ARCH_SUPPORTS_BIG_ENDIAN
depends on (ARCH_MULTI_V4_V5 && CPU_LITTLE_ENDIAN) || \
ARCH_MULTI_V6_V7 || ARM_SINGLE_ARMV7M
select CLKSRC_IMX_GPT
select GENERIC_IRQ_CHIP
select GPIOLIB

125
arch/arm/mach-integrator/Kconfig
View File

@ -1,125 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
menuconfig ARCH_INTEGRATOR
bool "ARM Ltd. Integrator family"
depends on ARCH_MULTI_V4T || ARCH_MULTI_V5 || ARCH_MULTI_V6
select ARM_AMBA
select CMA
select DMA_CMA
select HAVE_TCM
select CLK_ICST
select MFD_SYSCON
select PLAT_VERSATILE
select POWER_RESET
select POWER_RESET_VERSATILE
select POWER_SUPPLY
select SOC_INTEGRATOR_CM
select VERSATILE_FPGA_IRQ
help
Support for ARM's Integrator platform.
if ARCH_INTEGRATOR
config ARCH_INTEGRATOR_AP
bool "Support Integrator/AP and Integrator/PP2 platforms"
select INTEGRATOR_AP_TIMER
select SERIAL_AMBA_PL010 if TTY
select SERIAL_AMBA_PL010_CONSOLE if TTY
select SOC_BUS
help
Include support for the ARM(R) Integrator/AP and
Integrator/PP2 platforms.
config INTEGRATOR_IMPD1
bool "Include support for Integrator/IM-PD1"
depends on ARCH_INTEGRATOR_AP
select ARM_VIC
select GPIO_PL061
select GPIOLIB
select REGULATOR
select REGULATOR_FIXED_VOLTAGE
help
The IM-PD1 is an add-on logic module for the Integrator which
allows ARM(R) Ltd PrimeCells to be developed and evaluated.
The IM-PD1 can be found on the Integrator/PP2 platform.
config INTEGRATOR_CM720T
bool "Integrator/CM720T core module"
depends on ARCH_INTEGRATOR_AP
depends on ARCH_MULTI_V4T
select CPU_ARM720T
config INTEGRATOR_CM920T
bool "Integrator/CM920T core module"
depends on ARCH_INTEGRATOR_AP
depends on ARCH_MULTI_V4T
select CPU_ARM920T
config INTEGRATOR_CM922T_XA10
bool "Integrator/CM922T-XA10 core module"
depends on ARCH_MULTI_V4T
depends on ARCH_INTEGRATOR_AP
select CPU_ARM922T
config INTEGRATOR_CM926EJS
bool "Integrator/CM926EJ-S core module"
depends on ARCH_INTEGRATOR_AP
depends on ARCH_MULTI_V5
select CPU_ARM926T
config INTEGRATOR_CM10200E_REV0
bool "Integrator/CM10200E rev.0 core module"
depends on ARCH_INTEGRATOR_AP && n
depends on ARCH_MULTI_V5
select CPU_ARM1020
config INTEGRATOR_CM10200E
bool "Integrator/CM10200E core module"
depends on ARCH_INTEGRATOR_AP && n
depends on ARCH_MULTI_V5
select CPU_ARM1020E
config INTEGRATOR_CM10220E
bool "Integrator/CM10220E core module"
depends on ARCH_INTEGRATOR_AP
depends on ARCH_MULTI_V5
select CPU_ARM1022
config INTEGRATOR_CM1026EJS
bool "Integrator/CM1026EJ-S core module"
depends on ARCH_INTEGRATOR_AP
depends on ARCH_MULTI_V5
select CPU_ARM1026
config INTEGRATOR_CM1136JFS
bool "Integrator/CM1136JF-S core module"
depends on ARCH_INTEGRATOR_AP
depends on ARCH_MULTI_V6
select CPU_V6
config ARCH_INTEGRATOR_CP
bool "Support Integrator/CP platform"
depends on ARCH_MULTI_V5 || ARCH_MULTI_V6
select ARM_TIMER_SP804
select SERIAL_AMBA_PL011 if TTY
select SERIAL_AMBA_PL011_CONSOLE if TTY
select SOC_BUS
help
Include support for the ARM(R) Integrator CP platform.
config INTEGRATOR_CT926
bool "Integrator/CT926 (ARM926EJ-S) core tile"
depends on ARCH_INTEGRATOR_CP
depends on ARCH_MULTI_V5
select CPU_ARM926T
config INTEGRATOR_CTB36
bool "Integrator/CTB36 (ARM1136JF-S) core tile"
depends on ARCH_INTEGRATOR_CP
depends on ARCH_MULTI_V6
select CPU_V6
config ARCH_CINTEGRATOR
depends on ARCH_INTEGRATOR_CP
def_bool y
endif

10
arch/arm/mach-integrator/Makefile
View File

@ -1,10 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
#
# Makefile for the linux kernel.
#
# Object file lists.
obj-y := core.o
obj-$(CONFIG_ARCH_INTEGRATOR_AP) += integrator_ap.o
obj-$(CONFIG_ARCH_INTEGRATOR_CP) += integrator_cp.o

18
arch/arm/mach-iop32x/Kconfig
View File

@ -1,10 +1,18 @@
# SPDX-License-Identifier: GPL-2.0
menuconfig ARCH_IOP32X
bool "IOP32x-based platforms"
depends on ARCH_MULTI_V5
depends on CPU_LITTLE_ENDIAN
select CPU_XSCALE
select GPIO_IOP
select GPIOLIB
select FORCE_PCI
help
Support for Intel's 80219 and IOP32X (XScale) family of
processors.
if ARCH_IOP32X
menu "IOP32x Implementation Options"
comment "IOP32x Platform Types"
config MACH_EP80219
bool
@ -42,6 +50,4 @@ config MACH_EM7210
board. Say also Y here if you have a SS4000e Baxter Creek NAS
appliance."
endmenu
endif

1
arch/arm/mach-iop32x/em7210.c
View File

@ -223,6 +223,7 @@ static void __init em7210_init_machine(void)
MACHINE_START(EM7210, "Lanner EM7210")
.atag_offset = 0x100,
.nr_irqs = IOP32X_NR_IRQS,
.map_io = em7210_map_io,
.init_irq = iop32x_init_irq,
.init_time = em7210_timer_init,

1
arch/arm/mach-iop32x/glantank.c
View File

@ -205,6 +205,7 @@ static void __init glantank_init_machine(void)
MACHINE_START(GLANTANK, "GLAN Tank")
/* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
.atag_offset = 0x100,
.nr_irqs = IOP32X_NR_IRQS,
.map_io = glantank_map_io,
.init_irq = iop32x_init_irq,
.init_time = glantank_timer_init,

14
arch/arm/mach-iop32x/include/mach/irqs.h
View File

@ -1,14 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* arch/arm/mach-iop32x/include/mach/irqs.h
*
* Author: Rory Bolt <rorybolt@pacbell.net>
* Copyright: (C) 2002 Rory Bolt
*/
#ifndef __IRQS_H
#define __IRQS_H
#define NR_IRQS 33
#endif

25
arch/arm/mach-iop32x/include/mach/uncompress.h
View File

@ -1,25 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* arch/arm/mach-iop32x/include/mach/uncompress.h
*/
#include <asm/types.h>
#include <asm/mach-types.h>
#include <linux/serial_reg.h>
#define uart_base ((volatile u8 *)0xfe800000)
#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
static inline void putc(char c)
{
while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
barrier();
uart_base[UART_TX] = c;
}
static inline void flush(void)
{
}
#define arch_decomp_setup() do { } while (0)

1
arch/arm/mach-iop32x/iq31244.c
View File

@ -324,6 +324,7 @@ MACHINE_END
MACHINE_START(EP80219, "Intel EP80219")
/* Maintainer: Intel Corp. */
.atag_offset = 0x100,
.nr_irqs = IOP32X_NR_IRQS,
.map_io = iq31244_map_io,
.init_irq = iop32x_init_irq,
.init_time = iq31244_timer_init,

1
arch/arm/mach-iop32x/iq80321.c
View File

@ -183,6 +183,7 @@ static void __init iq80321_init_machine(void)
MACHINE_START(IQ80321, "Intel IQ80321")
/* Maintainer: Intel Corp. */
.atag_offset = 0x100,
.nr_irqs = IOP32X_NR_IRQS,
.map_io = iq80321_map_io,
.init_irq = iop32x_init_irq,
.init_time = iq80321_timer_init,

2
arch/arm/mach-iop32x/irqs.h
View File

@ -43,4 +43,6 @@
#define IRQ_IOP32X_XINT3 IOP_IRQ(30)
#define IRQ_IOP32X_HPI IOP_IRQ(31)
#define IOP32X_NR_IRQS (IRQ_IOP32X_HPI + 1)
#endif

1
arch/arm/mach-iop32x/n2100.c
View File

@ -358,6 +358,7 @@ static void __init n2100_init_machine(void)
MACHINE_START(N2100, "Thecus N2100")
/* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
.atag_offset = 0x100,
.nr_irqs = IOP32X_NR_IRQS,
.map_io = n2100_map_io,
.init_irq = iop32x_init_irq,
.init_time = n2100_timer_init,

29
arch/arm/mach-ixp4xx/Kconfig
View File

@ -1,22 +1,19 @@
# SPDX-License-Identifier: GPL-2.0-only
if ARCH_IXP4XX
menu "Intel IXP4xx Implementation Options"
comment "IXP4xx Platforms"
config MACH_IXP4XX_OF
bool
prompt "Device Tree IXP4xx boards"
default y
menuconfig ARCH_IXP4XX
bool "IXP4xx-based platforms"
depends on ARCH_MULTI_V5
depends on CPU_BIG_ENDIAN
select ARM_APPENDED_DTB # Old Redboot bootloaders deployed
select CPU_XSCALE
select GPIO_IXP4XX
select GPIOLIB
select FORCE_PCI
select I2C
select I2C_IOP3XX
select PCI
select IXP4XX_IRQ
select IXP4XX_TIMER
select USB_EHCI_BIG_ENDIAN_DESC
select USB_EHCI_BIG_ENDIAN_MMIO
select USE_OF
help
Say 'Y' here to support Device Tree-based IXP4xx platforms.
endmenu
endif
Support for Intel's IXP4XX (XScale) family of processors.

4
arch/arm/mach-ixp4xx/Makefile.boot
View File

@ -1,4 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
zreladdr-y += 0x00008000
params_phys-y := 0x00000100

54
arch/arm/mach-ixp4xx/include/mach/uncompress.h
View File

@ -1,54 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* arch/arm/mach-ixp4xx/include/mach/uncompress.h
*
* Copyright (C) 2002 Intel Corporation.
* Copyright (C) 2003-2004 MontaVista Software, Inc.
*/
#ifndef _ARCH_UNCOMPRESS_H_
#define _ARCH_UNCOMPRESS_H_
#include <asm/mach-types.h>
#include <linux/serial_reg.h>
#define IXP4XX_UART1_BASE_PHYS 0xc8000000
#define IXP4XX_UART2_BASE_PHYS 0xc8001000
#define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE)
volatile u32* uart_base;
static inline void putc(int c)
{
/* Check THRE and TEMT bits before we transmit the character.
*/
while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
barrier();
*uart_base = c;
}
static void flush(void)
{
}
static __inline__ void __arch_decomp_setup(unsigned long arch_id)
{
/*
* Some boards are using UART2 as console
*/
if (machine_is_adi_coyote() || machine_is_gtwx5715() ||
machine_is_gateway7001() || machine_is_wg302v2() ||
machine_is_devixp() || machine_is_miccpt() || machine_is_mic256())
uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS;
else
uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS;
}
/*
* arch_id is a variable in decompress_kernel()
*/
#define arch_decomp_setup() __arch_decomp_setup(arch_id)
#endif

1
arch/arm/mach-keystone/Kconfig
View File

@ -8,7 +8,6 @@ config ARCH_KEYSTONE
select ARCH_HAS_RESET_CONTROLLER
select ARM_ERRATA_798181 if SMP
select COMMON_CLK_KEYSTONE
select ARCH_SUPPORTS_BIG_ENDIAN
select ZONE_DMA if ARM_LPAE
select PINCTRL
select PM_GENERIC_DOMAINS if PM

1
arch/arm/mach-lpc32xx/Kconfig
View File

@ -3,6 +3,7 @@
config ARCH_LPC32XX
bool "NXP LPC32XX"
depends on ARCH_MULTI_V5
depends on CPU_LITTLE_ENDIAN
select ARM_AMBA
select CLKSRC_LPC32XX
select CPU_ARM926T

2
arch/arm/mach-mmp/Kconfig
View File

@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
menuconfig ARCH_MMP
bool "Marvell PXA168/910/MMP2/MMP3"
depends on ARCH_MULTI_V5 || ARCH_MULTI_V7
depends on (CPU_LITTLE_ENDIAN && ARCH_MULTI_V5) || ARCH_MULTI_V7
select GPIO_PXA
select GPIOLIB
select PINCTRL

1
arch/arm/mach-moxart/Kconfig
View File

@ -2,6 +2,7 @@
menuconfig ARCH_MOXART
bool "MOXA ART SoC"
depends on ARCH_MULTI_V4
depends on CPU_LITTLE_ENDIAN
select CPU_FA526
select ARM_DMA_MEM_BUFFERABLE
select FARADAY_FTINTC010

1
arch/arm/mach-mv78xx0/Kconfig
View File

@ -2,6 +2,7 @@
menuconfig ARCH_MV78XX0
bool "Marvell MV78xx0"
depends on ARCH_MULTI_V5
depends on CPU_LITTLE_ENDIAN
select CPU_FEROCEON
select GPIOLIB
select MVEBU_MBUS

3
arch/arm/mach-mvebu/Kconfig
View File

@ -1,8 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
menuconfig ARCH_MVEBU
bool "Marvell Engineering Business Unit (MVEBU) SoCs"
depends on ARCH_MULTI_V7 || ARCH_MULTI_V5
select ARCH_SUPPORTS_BIG_ENDIAN
depends on ARCH_MULTI_V7 || (ARCH_MULTI_V5 && CPU_LITTLE_ENDIAN)
select CLKSRC_MMIO
select PINCTRL
select PLAT_ORION

Some files were not shown because too many files have changed in this diff Show More